How Materials and Device Factors Determine the Performance: A Unified Solution for Transistors with Nontrivial Gates and Transistor–Diode Hybrid Integration

Abstract Advanced field‐effect transistors (FETs) with nontrivial gates (e.g., offset‐gates, mid‐gates, split‐gates, or multi‐gates) or hybrid integrations (e.g., with diodes, photodetectors, or field‐emitters) have been extensively developed in pursuit for the “More‐than‐Moore” demand. But understanding their conduction mechanisms and predicting current–voltage relations is rather difficult due to countless combinations of materials and device factors. Here, it is shown that they could be understood within the same physical picture, i.e., charge transport from gated to nongated semiconductors. One proposes an indicator based on material and device factors for characterizing the transport and derives a unified and simplified solution for describing the current–voltage relations, current saturation, channel potentials, and drift field. It is verified by simulations and experiments of different types of devices with varied materials and device factors, employing organic, oxide, nanomaterial semiconductors in transistors or hybrid integrations. The concise and unified solution provides general rules for quick understanding and designing of these complex, innovative devices.

. Parameters of α and Q0 of the devices with varied donor-like or acceptor-like states. Figure S2. The extracted VD,SAT (dots) are plotted against ( − ℎ ), 1 0.5 ⁄ , and 1.5 0.5 ⁄ , respectively. Figure S3. Electric potential near the semiconductor-dielectric interface for devices with varied tSC or tox. Figure S4. The user interface of the index in the HTML file for calculating transistors. Figure S5. The user interface of the HTML file for calculating drain-offset transistors. Table S1. The TCAD simulation parameters of top-contact, bottom-gate transistors. Table S2. The parameters for I-V curves with donors or acceptors.  Figure S1. Parameters of α and Q0 of the simulated devices with varied donor-like or acceptor-like states, as a function of (a) n0 and (b) calculated η (VG-Vth= 3 V, Ci = 6.9×10 -8 F/cm 2 , tSC = 20 nm, V1 = 1.5 V). The values of α and Q0 are obtained by using Eq. (5) to the I-V data of simulated devices with varied density of donor-like or acceptor-like states, i.e., varying ND from 10 16 to 10 18 cm -3 with fixed at 0.4 eV, or varying NA from 5×10 16 to 5×10 18 cm -3 at fixed wA fixed at 0.1 eV. In particular, when ND = 10 18 cm -3 , n0 is 3.6×10 16 cm -3 , qn0 is 5.7×10 -3 C/cm 3 , and 0 is 5.9×10 -3 C/cm 3 , consistent with the predicted relation 0~q n0 in Ohmic conduction. When ND = 0 cm -3 , n0 is 8.5×10 13 cm -3 , 9 8 ⁄ is 1.0×10 -12 , and 0 is 1.3×10 -12 C/cm 3 , consistent with the predicted relation 0~9 8 ⁄ with SCLC in the non-gated channel. The general trend in (b) is presented in Figure 3a in the main context.  (VD, tox, d, and L) are found to increase linearly with (VG-Vth), 1 0.5 ⁄ , and 1.5 0.5 ⁄ , corresponding to Eq. (9) with SCLC. The same data are plotted together in Figure 5d in the main context. Figure S3. Electric potential near the semiconductor-dielectric interface for devices with varied tSC or tox by device simulation. In (a-c), tSC is varied from 2, 5, to 20 nm with tox fixed at 10 nm. In (c-e), tox is varied from 10, 30, to 20 nm with tSC fixed at 20 nm. The gate is from X = 1 to 9 μm and the drain is from X = 9 to 10 μm. ΔL is the distance from the position where the interfacial potential reaches VG -Vth (5 V, dashed line) to the drain.
denoting the density of carriers forming space charge regions, we could consider that: the carriers injected from the gated semiconductor will reach the end of the non-gated semiconductor within the transit time , therefore giving the total charges within the non-gated semiconductor as . Then, the average density of the injected carriers distributed within the volume of the non-gated semiconductor are characterized by ( ) ⁄ , where S is the current area and d is the transit length. Therefore, the average value of can be characterized as: Here, is the permittivity of the non-gated semiconductor, and μ1 and μ2 are the carrier mobility in the gated and non-gated semiconductors. V1 is the potential at the end of the gated-channel (with the upper limit VG-Vth or VD). In a drain-offset transistor, = with tsc as the thickness of the non-gated semiconductor. The value of increases if V1 increases. In the main context, − ℎ − 1 2 ⁄ is approximated as − ℎ for simplicity. In practice, when estimating the value of , 1 = ( − ℎ ) 2 ⁄ could be used.

Supporting Note 2 Equation derivation of trap-limited SCLC.
The current density is assumed to be: Here, = + and = + 2 .

Supporting Note 4
Drain-offset transistors. In Eq. (6) in the main context, the 2 nd order Taylor series is applied to the right as V1 < VD. Then we have Rearrange Eq. (7) and we have 1 2 + 1 + = 0, where = 1 + ( − 1) −2 , = −2( − ℎ + −1 ), and = 2 . The accurate solution is: 1 = (− − √ 2 − 4 ) (2 ) ⁄ . In particular, when is small, V1 << VD and the right of Eq. (7) becomes . Therefore, the approximate solution is: 1 ≈ ( − ℎ ) − √( − ℎ ) 2 − 2 . In calculation, the upper limit of |V1| is the minimum of |VG-Vth| and |VD|. The maximum electric field in the non-gated channel is obtained when x = L + d: . For a semiconductor with the breakdown field EB, we have |EMAX| ≤ EB and so the maximum voltage |∆ | across the non-gated semiconductor is |∆ | = ⁄ . The maximum current is: The maximum virtual power is: The local power density for Joule heating in the non-gated channel is calculated by using Eq. (8): The maximum value is obtained at x = L. Here, , is the saturated current: Supporting Note 5 Depletion region width. For Figure 5e in the main context, the device parameters are W = 1000 μm, L = 8 μm, d = 2 μm, tsc = 20 nm, μ1 = μ2 = 1 cm 2 /Vs, and Ci = 11 nF cm -2 . The bias condition is VG = 5 V and VD is from 7.5 V to 20 V (step 2.5 V). For the first three series of dots in Figure 5e, tSC is 2 nm, 5 nm, or 20 nm (with tox fixed at 10 nm). For the second three series of dots in Figure 5e, tox is 10 nm, 30 nm, or 70 nm (with tSC fixed at 20 nm). ΔL is the distance from the position where the interfacial potential reaches VG -Vth (5 V) to the drain. The channel potential of simulated devices is shown in Supporting Fig. 3.
Also, the TCAD simulation data show that Eq. (10) in the main context could be used to estimate ∆ by using = 1.9 when ( − ℎ ) ⁄ < 3. For example, when tSC = 20 nm and tox = 10 nm, the estimated ∆ by Eq. (10) is 88 nm and the TCAD simulated ∆ is 78 nm for VD = 10 V. According to Eq. (10), the channel length modulation effect is characterized by: Here, is a function of ( − ℎ ) ⁄ . Hence, ( − ∆ ) ⁄ will increase if L increases, but will decrease if decreases.
We could use Eq. (s7) for regular TFTs by replacing d by ∆ : It indicates that Joule heating in a saturated transistor is more severe in short-L devices even with the same J.

Supporting Note 6
Split-gate transistors. A split-gate transistor could be regarded as a Gated/Non-gated/Gated structure. Denote 1 = 1 − ℎ1 (near the source) and 2 = 2 − ℎ2 (near the drain) and, for generality, the current is: Usually, 1 = 3 and 1 = 3 . Denote 12 = ( 2 0 1 ) ( 1 1 ) ⁄ , 32 = ( 2 0 3 ) ( 3 3 i ) ⁄ , 31 = ( 1 1 3 ) ( 3 3 1 ) ⁄ , and ∆ = 2 − 1 . Assume ≈ 0 (Ohmic contact) so that Eq. (s11) is simplified as: We can simplify the problem when scanning VG1: (1) Treat the 2 nd (non-gated) and 3 rd (gated) channels as a whole and calculate V1 by the same method in the main texts with a VG2-dependent Q0 (i.e., 00 2 , r is the power of Q0); (2) Use V1 to calculate the corresponding V2 by equaling the 1 st and 3 rd term in Eq. (s12); (3) As the 3 rd (gated) channel with a fixed VG2 limits the current, the maximum V1,max can be calculated by equaling V1 and V2 in Eq. (s12). Notice that the upper limit of V1 is the minimum of V1,max, VGt1, VGt2, and VD, whereas the upper limit of V2 is VGt2 and VD. Such asymmetry is caused by the asymmetry of source and drain voltages. The calculated results are consistent with those from TCAD, indicating the simplification reveals the key physics. Readers could use the attached HTML file for practical calculations or fittings, including transfer or output characteristics. When calculating the split-gate transistors (Fig. 7 in the main context), the device has the dimension of L1 = 8 μm, d = 2 μm, and L2 = 8 μm, with other parameters as the same as those in the drain-offset transistors.