Versatile On‐Chip Programming of Circuit Hardware for Wearable and Implantable Biomedical Microdevices

Abstract Wearable and implantable microscale electronic sensors have been developed for a range of biomedical applications. The sensors, typically millimeter size silicon microchips, are sought for multiple sensing functions but are severely constrained by size and power. To address these challenges, a hardware programmable application‐specific integrated circuit design is proposed and post‐process methodology is exemplified by the design of battery‐less wireless microchips. Specifically, both mixed‐signal and radio frequency circuits are designed by incorporating metal fuses and anti‐fuses on the top metal layer to enable programmability of any number of features in hardware of the system‐on‐chip (SoC) designs. This is accomplished in post‐foundry editing by combining laser ablation and focused ion beam processing. The programmability provided by the technique can significantly accelerate the SoC chip development process by enabling the exploration of multiple internal circuit parameters without the requirement of additional programming pads or extra power consumption. As examples, experimental results are described for sub‐millimeter size complementary metal‐oxide‐semiconductor microchips being developed for wireless electroencephalogram sensors and as implantable microstimulators for neural interfaces. The editing technique can be broadly applicable for miniaturized biomedical wearables and implants, opening up new possibilities for their expedited development and adoption in the field of smart healthcare.

The utilization of downlink communication programming provides the advantage of adaptive and real-time adjustments for biomedical microchips.However, in any number of cases, the multiple limitations of downlink programming favor the utilization of the type of fuse programming described in this paper.To begin, downlink programming predominantly employs transistor-based switches that exhibit low "short" state resistance and moderate "open" state resistance.Yet, these switches cannot deliver equivalent control as compared to the fuse method due to the inadequate resistance of the "open" state in the transistor-based switches.Figure 2 illustrates such a situation, wherein a high impedance pseudo-resistor cannot be effectively managed by a conventional transistor switch, thus demanding the incorporation of the fuse/anti-fuse control approach.
Furthermore, there is the "Cold start" problem.If the initial state of the circuit is not optimal, a fully wireless circuit might fail to initiate.In such instances, utilizing downlink communication to program the chip is infeasible.For instance, if the regulated VDD is designed to be exceptionally low, the chip may not initiate from the initial state, making it impossible for downlink communication to resolve the issue.On the other hand, adopting the fuse method to increase the regulated VDD permits a shift from the initial starting point to enable functionality even without chip activation (as depicted in Figure 5).
Additionally, downlink programming necessitates the integration of a downlink demodulator which can consume extra space and power.By contrast, in fuse programming no further wireless remote or electronic control is required as the hardware itself has already been modified thereby mitigating complexity and power consumption.Our wireless EEG sensor chips, for example, were designed to function without downlink communication given the benefits of fuse programming for hardware modification.
However, downlink programming holds an advantage over fuse programming in scenarios requiring real-time adaptive programming-a capability that fuse programming lacks.Hence, depending on the ultimate complexity of microchip design and its intended biomedical application, an implant system might benefit from accommodating both methods.In contrast to the externally biased pseudo-resistor depicted in Figure 2a, this configuration employs a self-biased pseudo-resistor.

Figure S2 .Figure S4 .
Figure S2.SEM image and FIB cross-section image of the ablated top metal fuse Figure S3.Low cutoff frequency of the single-stage amplifier as a function of the gate bias voltage Figure S4.Circuit layout and connection geometry for anti-fuses, pseudo-resistors, and the neural signal amplifier Figure S5.Circuit configuration of a pseudo-resistor evaluated using anti-fuse programming Figure S6.FIB-based on-chip Pt microelectrode fabrication process Figure S7.Arrangement for fully wireless chip testing Figure S8.Integration of programmable fuses in relaxation oscillator subcircuits for on-chip clock frequency control TableS2.Types and parameters for self-biased pseudo-resistors selected by anti-fuse programming

Figure S1 .
Figure S1.Scanning electron microscope (SEM) image of the top metal fuse after ablating the dielectric passivation layer.The SEM image shows the top metal fuse exposed following the precise removal of the approximately 1 µm-thick dielectric passivation layer (silicon nitride and oxide).The passivation layer was etched using a UV laser pulse with a wavelength of 355 nm and an average power of 0.25 mJ, here after five repetitions.

Figure S2 .
Figure S2.SEM image and FIB cross-section image of the ablated top metal fuse.The SEM image on the left shows a top view of the ablated top metal fuse, with the size of 3 µm × 3 µm, while the image on the right presents a cross-sectional view achieved through focused ion beam (FIB) polishing.The yellow dashed line indicates the FIB cut.Notably, the size of the smallest fuse is restricted to 3 µm × 3 µm, according to the circuit design rule of the chosen process.The image demonstrates the high spatial resolution of the laser ablation technique, allowing for selective removal and cutting of fuse connections while minimizing damage to adjacent circuit structures.

Figure S3 .
Figure S3.Low cutoff frequency of the single-stage amplifier as a function of the gate bias voltage for the externally biased tunable pseudo-resistors (see main text).Results obtained from simulation and measurement are compared.

Figure S4 .
Figure S4.Circuit layout and connection geometry for anti-fuses, pseudo-resistors, and the neural signal amplifier.(a) Circuit photograph depicting 25 types of pseudo-resistors (left), where each pseudo-resistor is connected to a pair of anti-fuses.Circuit layout illustrating the arrangement of the pseudo-resistors and anti-fuses (right).(b) Illustration of the connection scheme between the anti-fuse, pseudo-resistor, and the amplifier shown in Figure 2a.Each antifuse comprises two isolated vias (each measuring 6 µm × 6 µm).The passivation layer is selectively removed through FIB milling, enabling Pt interconnect fabrication between the vias using IBID techniques.(c) SEM image showing the alignment of a row of four connected antifuses, corresponding to two pseudo-resistors, in the single-stage amplifier experiment.

Figure S5 .
Figure S5.Circuit configuration of a pseudo-resistor evaluated using anti-fuse programming.

Figure S6 .
Figure S6.FIB-based on-chip Pt microelectrode fabrication process.(a) FIB milling process was utilized to etch a 500 nm-deep layer, removing the aluminum oxide of the contact pad for access to the bare Al contact pad.A 300 nm-thick layer of platinum was then deposited on top of the Al pad using ion-beam-induced deposition (IBID).(b) Side view schematic illustrating the monolithic integration of the Pt microelectrode on the chip.

Figure S7 .
Figure S7.Arrangement for fully wireless chip testing.The image depicts a transmitting (Tx)coil and associated components mounted on an FR4 printed circuit board (PCB) with a salineholding wall in which the microchips were located.This experimental setup was designed to test chips in a completely wireless environment.During the resonance frequency testing process, the microchip was securely fixed in position, allowing for precise control of the tuning capacitance in a stable electromagnetic environment.To ensure impedance matching, two matching capacitors were utilized to match the impedance of the Tx coil to 50 ohms.The SMA connector was used to connect the Tx coil to the external RF hub and electronics for wireless power transfer and data communication.The SMA connector was tilted to facilitate the laser ablation process, allowing for the objective lens to approach the microchip closely.

Figure S8 .
Figure S8.Integration of programmable fuses in relaxation oscillator subcircuits for on-chip clock frequency control.(a) Circuit schematic of the relaxation oscillator utilized for generating a nominally 30 MHz on-chip clock, illustrating the integration of a programmable fuse structure within the oscillator.Cutting the fuse line impacts its time constant, resulting in a decrease in the oscillation frequency.This allows for precise control of the clock frequency within a fixed voltage supply.(b) Microphotograph showing the geometric design of the fuse lines, specifically engineered to avoid RF interference with underlying circuits.

Table S1 . Comparison between systems using discrete components and fully integrated systems
work Supplementary Note 1.Comparison between wireless downlink communication programming and post-process fuse/anti-fuse hardware modification approaches

Table S2 .
Types and parameters for self-biased pseudo-resistors selected by anti-fuse