Complementary Organic Logic Gates on Plastic Formed by Self‐Aligned Transistors with Gravure and Inkjet Printed Dielectric and Semiconductors

there is a lack of direct comparative studies of the impact of each process on the electrical performance of devices. Here, we explore gravure versus inkjet printing of semiconductors, gravure printing versus photolithographic patterning of the OFET dielectric, and long-channel (>1 μm) versus short channel (<1 μm) OFETs. Gravure printing enables very large-area, fast, roll-to-roll manufacturing, limited by the expense and time cost of fabricating clichés (printing plates). [ 16,17 ] Inkjet printing enables a computer-designed circuit to be printed readily and easily, limited by the relative throughput and speed of printing. [ 2 ] However, the resolution of both technologies is still restricted to the micrometer scale and larger by the challenge of reliably transferring inks onto a substrate without spreading or dewetting, while still maintaining electrical performance. While recent approaches are improving upon this limit, for example, the work of Kang et al. on gravure printed sub-5 μm gate electrodes, [ 18 ] or that of Sekitani et al. on 2 μm inkjet printed electrodes, [ 19 ] the options for patterning sub-micrometer electrode geometries are limited. We have previously demonstrated how ultraviolet nanoimprint lithography (UV-NIL) is a viable method for patterning sub-micrometer channel length OFETs on plastic. [ 20 ]

DOI: 10.1002/aelm.201500272 photo detectors. [ 10 ] Similarly gravure printing has been used to fabricate circuits such as: complementary ring oscillators, [ 11 ] logic gates, [ 12 ] unipolar fl ip-fl ops and half-adders. [ 13,14 ] Although previous reports have combined gravure and inkjet printing to fabricate p-type organic fi eld-effect transistors (OFETs), [ 15 ] there is a lack of direct comparative studies of the impact of each process on the electrical performance of devices. Here, we explore gravure versus inkjet printing of semiconductors, gravure printing versus photolithographic patterning of the OFET dielectric, and long-channel (>1 µm) versus short channel (<1 µm) OFETs.
Gravure printing enables very large-area, fast, roll-to-roll manufacturing, limited by the expense and time cost of fabricating clichés (printing plates). [ 16,17 ] Inkjet printing enables a computer-designed circuit to be printed readily and easily, limited by the relative throughput and speed of printing. [ 2 ] However, the resolution of both technologies is still restricted to the micrometer scale and larger by the challenge of reliably transferring inks onto a substrate without spreading or dewetting, while still maintaining electrical performance. While recent approaches are improving upon this limit, for example, the work of Kang et al. on gravure printed sub-5 µm gate electrodes, [ 18 ] or that of Sekitani et al. on 2 µm inkjet printed electrodes, [ 19 ] the options for patterning sub-micrometer electrode geometries are limited.
We have previously demonstrated how ultraviolet nanoimprint lithography (UV-NIL) is a viable method for patterning sub-micrometer channel length OFETs on plastic. [ 20 ] Our approach also uses self-aligned lithography to minimize the overlap between the gate-source and gate-drain electrodes, reducing parasitic overlap capacitances that reduce the switching speed of OFETs. [ 21,22 ] Self-alignment yields other benefi ts such as overcoming equipment alignment tolerances, reducing leakage currents, and is compatible with more complex circuitry such as self-aligned unipolar ring oscillators. [ 23 ] In this work, we have used bottom-gate bottom-contact architectures, to avoid exposing the semiconductor to both the ultraviolet light and processing chemicals used for self-alignment. In addition to self-alignment, here we extend the fabrication approach further by incorporating gravure printed dielectrics and semiconductors, as well as inkjet printed semiconductors. We demonstrate both p-and n-type devices patterned side-by-side on the same substrate along with complementary inverters and logic gates. Figure 1 illustrates the materials and architectures used in this work. Aluminum OFET gates were patterned either photolithographically (PL) or via UV-NIL. A cross-linkable proprietary dielectric (GSID 938109-1, BASF) [ 24,25 ] was either PL patterned or gravure printed. Self-aligned gold electrodes were patterned Organic electronics is a maturing fi eld, [ 1 ] replete with a large variety of devices and fabrication technologies. [ 2 ] Often these are viewed in isolation, however ultimately it is likely that a holistic approach involving multiple techniques will yield the best manufacturing results. This will use the particular advantages of each technology and apply it where best-suited. [ 3 ] As attention shifts to implementing complex circuit components, there is increasing focus on the use of complementary circuits. Complementary logic combines both p-and n-type semiconductors to yield circuits with better noise tolerance and lower power consumption, [ 4,5 ] although at expense of fabrication complexity (two semiconductors need to be deposited rather than one). This is where additive printing processes have the potential to yield dividends, allowing the selective deposition of materials onto the substrate. Among these techniques both inkjet and gravure printing have been widely adopted.
Inkjet printing has been used to fabricate a wide range of electrical components, including: complementary and ambipolar inverters, [ 6,7 ] quasistatic memory, [ 8 ] biosensors, [ 9 ] and organic via a bilayer liftoff process, before semiconductor patterning by either gravure or inkjet printing. Each substrate variant had two different semiconductors patterned on adjacent devices to facilitate complementary circuits. We chose two high performance polymeric semiconductors, based on previous demonstrations of transistor performance and printability. [ 2,8,26 ] These were the predominantly p-type polymer diketopyrrolopyrrole-thieno[3,2 -b ]thiophene (DPPT-TT); [ 27 ] and the n-type poly([ N,N′ -bis(2-octyldodecyl)naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′bithiophene)) (P(NDI2OD-T2)) (structures in Figure 1 a). [ 28 ] All devices are bottom-gate bottom-contact as necessitated by our selfaligned approach. The fabrication process is discussed in detail in the Supporting Information and also in our previous work. [ 20 ] Figure 1 c-f) show the predominantly PL patterned (variants A + B) and printed (variants G + H) devices. The edges of the dielectric square are just visible in the optical micrographs (Figure 1c,d). The relatively large size of the dielectric region is to compensate for a nominal alignment tolerance of ±0.5 mm in the gravure printer. These dimensions can be readily downscaled using a gravure printer featuring an alignment tool. We observed that gravure printing the dielectric yields a larger line-edge roughness compared to photopatterning. This rippling of the printed edge is common throughout gravure printing, emerging from a combination of hydrodynamic instability in ink during the printing process, [ 29 ] and as a consequence of the underlying cliché cell structure. [ 30 ] Surface profi lometry measurements indicated a slight 'coffee ring effect' at the edge of the gravure printed structure, [ 31 ] but an otherwise homogenous fl at fi lm in the device region. Although based on the same dielectric, the gravure printed ink formulation yielded a thinner dielectric layer (86 ± 14 nm) compared to the PL patterned layer (174 ± 26 nm) (see Figure S1 in the Supporting Information).
We used a meandering gate to give self-aligned interdigitated source-drain fi ngers with a nominal channel width of W = 5000 µm and length of L = 3 µm and L = 0.9 µm for PL and NIL patterned gates, respectively. Focussed-ion beam scanning electron microscopy (FIB-SEM) was used to verify the nanoscale structure of the devices, as shown in Figure 1 e,f. Substrates were milled by irradiation with gallium ions, before imaging the device cross-section using SEM. Exceptionally low gate-drain and gate-source electrode overlaps of ≤210 nm were observed. By comparison, conventionally aligned common-gate www.MaterialsViews.com www.advelectronicmat.de devices typically have overlaps on the order of many hundreds of micrometers. We also used the SEM images and image analysis software to calculate the effective channel length of each variant. [ 32 ] NIL patterned channels were found to be slightly smaller and PL patterned channels slightly larger than the nominal L values (see Table S1 in the Supporting Information for values). In the case of photopatterned dielectrics (variants A + B, E + F) exceptionally low leakage currents of <0.1 nA are observed, another advantage of self-aligned architectures. [ 22 ] Gravure printed dielectric (variants C + D, G + H) exhibit slightly greater leakage as a result of the ≈50% thinner layer deposited by printing (as discussed above). Despite this the relative ratio of drain to gate current remains in the range 10 2 -10 4 for these devices, yielding functioning OFETs and circuits.
From Figure 2 we note that the combination of sub-micrometer NIL-patterned channels, thin gravure printed dielectric and inkjet printed semiconductor (variant H) yield both p-and n-type devices with the highest effective mobilities, with median values of µ p = 0.173 cm 2 V −1 s −1 and µ n = 0.007 cm 2 V −1 s −1 , respectively. Similarly, the best performing gravure printed semiconductor devices (variant G) exhibit median values of µ p = 0.079 cm 2 V −1 s −1 and µ n = 0.005 cm 2 V −1 s −1 , respectively. The observed boost for NIL patterned short channel devices suggests the onset of shortchannel effects such as drain-induced barrier lowering, [ 5 ] which increase current fl ow through the device. [ 33 ] It is interesting to note from Figure 2 c that to within uncertainty there is no signifi cant difference in the extracted mobility for devices with PL patterned gates (variants A-D) for both DPPT-TT and P(NDI2OD-T2) semiconductors, unlike for NIL patterned gates (variants E-H). This suggests that at larger channel lengths the effective mobility obtainable is relatively process agnostic, while at shorter channel lengths the choice of deposition method has a greater infl uence. For the bottom-gate bottom-contact OFETs used here, the differing drying dynamics of gravure (simultaneous patterning and solvent evaporation) and inkjet (sequential deposition and drying, combined with partial re-dissolution of the semiconductor by consecutive drops) may be responsible for the differences observed here. [ 16,31,34 ] However, ultimately for larger channel length devices (typical in most applications) it appears for this material system that there is no electrical signifi cance to using either inkjet or gravure printing for semiconductor deposition. In this case other factors, such as process throughput or ability to rapidly modify the printed design, may favor one technique over the other.
Uniformity was found to be an issue for both gravure and inkjet printed semiconductors, irrespective of material. The spread of threshold voltages suggests this variation originates at the dielectric-semiconductor interface. Although we use a crosslinked dielectric system, a viscosity modifi er (high molecular weight poly(methyl methacrylate) (PMMA)) also forms part of the ink formulation and remains in the layer after cross-linking. Disordered dipoles in PMMA dielectrics have previously been observed to cause energetic disorder at the dielectric-semiconductor interface, yielding variation in device characteristics. [ 35 ] This represents one of the challenges of printed approaches; for example, for gravure printing reducing the PMMA content impacts ink viscosity and hence fi lm homogeneity. [ 36,37 ] Other methods for varying ink viscosity (concentration, long-chain solvent blends) are a possible approach to this issue. [ 29 ] Process yield was predominantly dictated by two factors. In the case of gravure printed dielectric (variant C + D, G + H), the thinner layer combined with process variation increased the probability of breakdown pathways forming, as refl ected in the higher leakage observed in functioning devices, which may be mitigated by increasing the layer thickness. For NIL patterned gates (E-H), the initial imprint step was signifi cantly hindered by a lack of NIL tool, we instead relied on a customized mask aligner. While useful for proof-of-concept testing, the imprint step was found to trap air, displacing the resist during patterning and limiting yield at this early step in the processing. This is a well-understood phenomenon and has been engineered out of modern NIL tools. [ 38,39 ] From our devices we were able to fabricate complementary inverters comprising DPPT-TT and P(NDI2OD-T2) OFETs to demonstrate the feasibility of complementary circuits, as shown in Figure 3 (implementation shown in Figure S3 in the Supporting Information). Other than the examples described below, variants E to G yielded few functioning devices due to the low NIL gate yield, as discussed above. Figure 3 a shows an example of the voltage transfer characteristics (VTCs) achieved by combining two NIL patterned gate devices (connected via external probing). By tuning the operating bias, highly abrupt switching behavior was observed at V dd = +9 V with a peak gain of 28. The current into the p-type load transistor was sub-30 nA in both the static on-and off-states, a direct result of the low leakage behavior obtained using self-alignment. Repeat testing of the inverter at multiple operating biases confi rmed stable behavior ( Figure S4 in the Supporting Information shows stability, current, and inkjet printed variant measurements).
According to classical CMOS theory the switching threshold is a function of operating bias, device geometry, dielectric specifi c capacitance, and the threshold voltages of the constituent OFETs. [ 4,40 ] In the ideal case V Th = V dd /2, helping to maximize the circuit noise margins. Here deviations from the ideal case are expected as a direct result of using a balanced OFET geometry, hence the switching threshold is strongly dictated by the relative p-and n-type mobilities ( µ p and µ n ), and can be further improved by tailoring the channel dimensions accordingly.
From Figure 3 b,c we note that inverters with inkjet printed semiconductor (variants B + D) gave the highest gains (median values of G = 8.0, G = 8.1, respectively), with a peak gain of G = 17.3 recorded. We also observe systematically lower switching thresholds for devices with gravure printed semiconductor (variants A + C) compared to inkjet printed (variants B + D). The origin of the shift is unclear, but is a consequence of the parameter spread observed in single OFET devices.
It is important to note the impact of the ambipolar behavior of both DPPT-TT and P(NDI2OD-T2), as observed in Figure 2 and in similar devices. [ 8 ] This, along with threshold voltage variation, can result in the P(NDI2OD-T2) OFET channel remaining partially conductive when the input is biased low, and vice versa for the DPPT-TT device. The consequence of this is a reduction in the output high ( V OH ) and increased output low ( V OL ) voltages, as seen in Figure 3 . Output high and output low voltages represent the voltage appearing at V OUT in both of the static inverter states. In the ideal case V OH = V dd , and V OL = 0 V, representing full inversion between the power supply voltage and ground. One method for preventing ambipolar behavior is through solution-processed selective contact engineering. [ 41,42 ] Finally, we fabricated complementary NAND and NOR logic gates as proof of concept for our technology. overlapping measurements, in which one input is held high, and the other switched, e.g., A in = +20 V and B in = + V in . The gate shows the expected response, with the output high when both inputs are low and vice versa. Given the symmetrical nature of the NAND and NOR gate implementation, we also fabricated a NOR logic gate (see Figures S5-S7 in the Supporting Information for implementations and NOR gate response).
In the ideal case the output voltage of each gate should be as close to the drive voltage as possible, i.e., V out ≈ V dd . In this case we note that the output in both cases is capped at just below V out = +10 V, and again this is as a result of deliberately using device geometries un-tuned to the specifi c characteristics of the semiconductor system. It is also noted that in Figure 3 d the output voltage differs by approximately V dd /4 depending on which input is performing the switching. This suggests slight variation in the two p-type OFETs that comprise the pull-up circuit. Despite this, these results demonstrate the feasibility of combining self-aligned OFETs on plastic to form functional complementary circuits.
In conclusion, we have shown how a holistic approach to device fabrication, combining the advantages of multiple technologies, can produce OFETs with enhanced electrical performance. For ≈3 µm channel length we observed no statistically signifi cant difference between the use of photolithography or gravure printing for patterning the dielectric layer. Similarly, no difference was observed between inkjet or gravure printed semiconductors. However, this was not true for sub-micrometer devices, whereby the combination of gravure printed dielectric and inkjet printed semiconductor yielded higher effective mobilities. From these results we recommend that gravure printing is an excellent substitute for lithographically patterned dielectric, helping to contribute to improved device performance. Self-aligned devices serve not only as a method for beating equipment alignment tolerances and achieving nanoscale aligned device structures, but also yield excellent low leakage performance. As organic circuit design becomes increasingly complex inevitably focus will shift to the downscaling of channel lengths. These fi ndings suggest that the differences in deposition methods will become more pronounced as a result; however, for large scale devices users should consider other factors, such as speed, practicality, and cost when considering which techniques to use.

Experimental Section
Full fabrication and characterization details are provided in the Supporting Information. www.MaterialsViews.com www.advelectronicmat.de

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.