Low‐Voltage Operation of Ring Oscillators Based on Room‐Temperature‐Deposited Amorphous Zinc‐Tin‐Oxide Channel MESFETs

Schottky diode FET logic (SDFL) ring oscillator circuits comprising metal‐semiconductor field‐effect transistors (MESFETs) based on amorphous zinc‐tin‐oxide (ZTO) n‐channels are presented. The ZTO channel layers are deposited entirely at room temperature by long‐throw magnetron sputtering. Best MESFETs exhibit on/off current ratios as high as 8.6 orders of magnitude, a sub‐threshold swing as low as 250 mV dec−1, and a maximum transconductance of 205 µS. Corresponding inverters show peakge gain magnitude (pgm) values of 83 with uncertainty levels as low as 0.5 V at an operating voltage of 5 V. Single stage delay times down to 277 ns are measured for three‐stage ring oscillators, corresponding to oscillation frequencies as high as 451 kHz. Oscillations are observed at operating voltages as low as 3 V. These results prove the feasibility of room‐temperature‐deposited, amorphous semiconducting oxide based integrated circuits with SDFL layout. The presented approach provides more efficient as well as fail‐safe device fabrication and similar oscillation frequencies at significantly lower operating voltages compared to conventional, high‐temperature processed logic circuits based on insulating gates.


Introduction
Transparent amorphous oxide semiconductors (TAOSs) exhibit remarkable transport properties despite their disordered structure. [1] Additionally, their high transparency in the visible range associated with the possibility of large-area deposition at low temperatures enables the cost-efficient fabrication of transparent and even bendable circuits. For instance, the TAOS indium-gallium-zinc-oxide (IGZO) is already commercially exploited, however, ongoing research is targeting toward replacing elements such as indium and gallium by abundant elements. [2] One promising material for sustainable, green

Results and Discussion
The static RT current-voltage characteristics of a ZTO-based MESFET as well as a schematic cross section through a MESFET sample, illustrating the basic material stacking order, are depicted in Figure 2. The gate width W and gate length L are 200 µm and 3 µm, respectively. Figure 2a displays the transfer characteristic as well as the gate leakage current for both voltage sweep directions. The MESFET exhibits a clear field effect with an on/off current ratio of 8.6 orders of magnitude and can be switched on and off within a voltage range of 3 V. The obtained sub-threshold swing and maximum transconductance are 250 mV dec −1 and 205 µS, respectively. A channel mobility of ≈1.8 cm 2 V −1 s −1 has been calculated using the relation µ = g max L/(eWnd). g max denotes the maximum transconductance derived from the transfer characteristic and the free-carrier density of n = 4.3 × 10 18 cm −3 was determined by Hall effect measurements. It should be noted the channel mobility clearly underestimates the free-carrier mobility of µ H = 5.4 cm 2 V −1 s −1 , obtained from Hall effect measurements, and hence has to be understood as a lower mobility limit, since the maximum transconductance cannot be determined due to the influence of gate leakage currents for positive gate voltages. The investigated MESFETs are normally-on with threshold voltages ranging from −0.6 to −0.3 V. Further, all investigated devices show a hysteresis of the drain current, especially for low gate voltages. The transfer characteristics obtained for different bias sweep directions cross around V G = 0 V. This dependence on the sweep direction can be attributed to localized states at the interface between the amorphous channel and the gate contact acting as charge traps. A similar effect has already been reported for ZnO-based junction field-effect transistors (JFETs) with amorphous ZnCo 2 O 4 gates. [14,15] Corresponding output characteristics for various gate voltages are depicted in Figure 2b. It is notable that the current does not fully saturate with further increasing the source-drain voltage. At V G = 0 V, which corresponds to the operational state of the pull-down transistor and pull-up transistor within the SDFL circuits (see Figure 1), the drain current increases with a slope of 0.15 µA V −1 . The shift of the output characteristic for V G > 0.5 V is caused by an increased leakage current flow over the gate diode and is a common phenomenon for MESFETs.
An essential step toward the realization of ring oscillators are investigations on the cascadability of the respective inverters. Here, we employ the SDFL approach that has already been Adv. Electron. Mater. 2019, 5,1900548   successfully demonstrated for ZTO-based inverters comprising depletion-type MESFETs and JFETs. [16] To achieve compatible output and input voltage levels, our SDFL circuits implement PtO x /i-ZTO/ZTO Schottky barrier diodes for shifting of the output voltage by means of a voltage drop across the diodes in order to switch a subsequent inverter. In addition to these diodes, the level shift configuration contains a transistor with its gate and source shorted, as depicted in Figure 1. This transistor is supplied with a negative operating voltage V bias and acts as constant-current bias source for the level shifting diodes, hence the denotation pull-down transistor.
Voltage transfer characteristics (VTCs) of a ZTO-based SDFL inverter without and with three level shifting diodes are depicted in Figure 3a for operating voltages V DD between 1 and 6 V. The pull-down transistor was supplied with a negative voltage of V bias = −2 V for all measurements. The gate width and length of the associated driving and pull-up transistor are 100 µm and 5 µm, respectively, while the pull-down transistor has a gate width-to-length ratio of 30 µm/5 µm. For negative input voltages, the output voltage approaches V DD . In the on-state of the driving transistor, the output voltage is still 0.5 V rather than the expected ground potential of 0 V. This can be attributed to the low threshold voltage, causing the pull-up transistor to increasingly operate in the saturation regime at higher I D . Consequently, V DD partly drops across the pull-up transistor and the driving transistor, resulting in a decreased logic swing. Fullswing ZTO-based inverters with sufficient level shift have previously been achieved using MESFETs and JFETs with threshold voltages approaching 0 V. [16] However, a decreased logic swing does not affect the cascadability of SDFL inverters as long as the total level shift V shift is sufficiently high. Further, the output voltage of the VTCs without level shift starts to increase once V IN exceeds 0.8 V due to current flow over the forward-biased gate diode. Characteristic parameters of the VTCs such as the peak gain magnitude (pgm), that is, the maximum gain, and the uncertainty level V UC are depicted in Figure 3a and have been determined for various operating voltages. The pgm can be calculated as max|∂V OUT / ∂V IN |. V UC is defined as the difference between both input voltages, where the gain equals −1. The presented inverter exhibits a pgm and V UC (level shift not considered) of 83 and 0.5 V for V DD = 5 V, respectively. Regarding the shifted VTCs in Figure 3a, a total voltage shift of V shift = 2.25 V is obtained for three level shifting diodes. In this case, the pgm slightly decreases to 75, whereas V UC remains 0.5 V at an operating voltage of 5 V. Previously reported ZTO-based SDFL inverters, comprising MESFETs, exhibited a remarkable pgm of 294 at V DD = 5 V. [16] This significant discrepancy in maximum gain can be attributed to the voltage dependency of the saturation current of the pull-up transistors and driving transistor at V G = 0 V for our devices (see Figure 2b). [17,18] Furthermore, we investigated the cascadability of our SDFL inverters within inverter chains consisting of four seriesconnected stages. Each SDFL inverter stage consists of three diodes for level shifting. For cascading of these inverters, V IN was applied at the input of the first inverter while V OUT was measured at the output of the last inverter stage. The corresponding VTCs are depicted in Figure 3b for various operating voltages and exhibit the expected inverting behavior. V DD ranges from 3 to 5 V and V bias was fixed at −2 V. Due to an observed level shift of approximately V shift = 2.5 V, operating voltages of V DD ≤ 2.5 V result in incompatible output driving voltages that do not match the input voltage range. Hence, a successful cascading with inverting behavior was only achieved for operating voltage of V DD > V shift . As expected, it was also observed that the VTCs become significantly steeper the more inverter stages are connected within the chain. In case of four series-connected inverters, the pgm increases up to 700 while simultaneously uncertainty levels as low as 0.08 V are obtained for V DD = 5 V.
Measured frequencies as a function of V DD as well as the typical time trace of a three-stage ZTO-based SDFL ring oscillator are depicted in   maximum oscillation frequency of 451 kHz is observed at V DD = 3 V, corresponding to single stage delay times of 277 ns. Oscillations start to occur at a minimum operating voltage of 3 V, which is attributed to the voltage drop V shift across the level shifting diodes. For V DD < V shift , no oscillations are observed since the output voltage range does not match the input voltage range of the subsequent inverter. Within the operating voltage range of approximately V shift < V DD < V shift + 1 V, a shift in the frequency can be observed for most of the investigated devices, which has also been reported for ZnO-based SDFL ring oscillators. [19] For V DD ≥ V shift + 1 V, the observed frequencies of ≈350 kHz stay constant as expected for SDFL circuits, since the supply current is limited by the pull-up and pull-down transistors which operate in saturation and act as constant current sources.
Klüpfel et al. developed an analytical model to estimate the single stage delay time τ D based on easily obtainable FET and inverter quantities. [19] τ D was calculated using the relation where C G , I PU , and F are the driving gate capacitance, the saturation current of the pull-up FET, and the fan-out, respectively. [19] ΔV = V shift /N diode -V bias denotes the voltage swing which is present at the input of each driving gate. N diode is the number of implemented level shifting diodes. If the previous inverter within the cascaded chain drives F gates, the maximum supply current available for recharging of gate capacitances is I PU /F. Since the presented ring oscillator circuits consist of (N-1) inverter stages with F = 1 and one inverter stage with F = 2 (see Figure 1), the oscillation frequency can be estimated by the relation f = (2(N+1)τ D F = 1 ) -1 . [19] The results in terms of expected maximum and minimum oscillation frequencies are represented by the dashed lines in Figure 4. The scattering of calculated frequencies results from variations of the device properties across the sample. C G was constant and ≈15 pF and ΔV was determined from the VTCs of the corresponding inverters. I PU ranged from 50 to 200 µA, resulting in estimated oscillation frequencies between 170 and 670 kHz. The slight deviations in observed frequencies for various V DD can be attributed to the saturation current dependence on the source-drain potential.

Conclusion
In summary, we have realized ring oscillators comprising MESFETs based on room-temperature-deposited amorphous zinc-tin-oxide. Oscillation frequencies up to 451 kHz with single stage delay times of 277 ns have been observed for threestage ring oscillators with W = 100 µm and L = 5 µm at V DD = 3 V and V bias = −2 V. Demonstrated ring oscillators operated at voltages as low as 3 V, which is significantly lower compared to previously reported high-temperature processed, ZTO-based three-stage ring oscillators, exhibiting similar single stage delay times at V DD between 8 and 60 V. [9,10] In case of amorphous IGZO, similar single stage delay times have been achieved for TFT-based ring oscillators, operating at V DD between ≈8 and 80 V. [20][21][22][23][24][25] Since the single stage delay time of SDFL circuits is strongly dependent on device layout parameters, high-frequency circuits at low operating voltages based on amorphous semiconducting oxides are feasible. By scaling down the gate length by a factor of 10 (leading to a gate length of 0.5 µm) using state-of-the-art photolithographic patterning techniques, an increase of oscillation frequencies up to 100 times higher is expected due to the linear dependency of the gate length on the driving gate capacitance as well as the total driving current. To operate in the desired ISM band frequency range of for instance 13.56 MHz, a reduction of the gate length to ≈0.4 µm (under otherwise constant device parameters) is necessary.
Overall, the presented results prove that room-temperaturedeposited amorphous ZTO is a suitable candidate for more cost-efficient, sustainable green circuitry, and an indium-free and gallium-free alternative to the commercially exploited, far more mature amorphous representative IGZO. Furthermore, it was shown that low-temperature-processed ZTO thin films and associated integrated circuits can compete with previously reported high-temperature-treated devices concerning their performance. Additionally, room-temperature-deposited of entire device structures offers the possibility of utilization of organic substrates, allowing the realization and investigation of flexible and even transparent integrated circuits.

Experimental Section
The integrated circuits presented in this study comprise MESFETs based on amorphous n-ZTO channels fabricated by radio frequency, long-throw magnetron sputtering. To ensure amorphous growth, the ZTO thin films were deposited at RT using a ceramic target with a 33 wt% ZnO and 67 wt% SnO 2 composition. [4] A comparatively large target-to-substrate distance of 25 cm was chosen to prevent the impingement of high energetic particles and droplets allowing growth of homogeneous thin films without sputter induced damage. All thin films were deposited on 10 × 10 mm 2 SiO 2 substrates. Since all thin films were deposited at RT, photolithography was used for patterning of transistor structures as well as inverters and ring oscillator circuits.
Previous investigations on ZTO-based MESFETs indicated the formation of a highly conductive layer at the interface close to the substrate, preventing a sufficient depletion of the channels. [13] Thus, ZTO mesa structures were deposited in two steps: first the sputtering process was ignited in a 25/30 sccm O 2 /Ar flow atmosphere and subsequently an ≈13 nm thick conductive ZTO layer was sputter-deposited under pure argon flow, resulting in a nominal thickness of 25 nm. The basic material stacking order that was present in all investigated devices is illustrated in Figure 2c. The channel fabrication step was followed by the deposition of source and drain contacts, using DC-sputtered Au. Between the two necessary SDFL design-related metallization steps, a 200 nm thick insulating HfO 2 layer was deposited at RT. This insulating layer has also been used to realize multi-gate FET structures, that were implemented in inverters and ring oscillator circuits to increase the maximum current flow through the channel. The gate contact was deposited in a single final step. Reactive sputtered PtO x with a Pt capping was used as gate material to reduce the free-carrier density close to the ZTO/PtO x interface due to a saturation of under-coordinated cation bonds via transfer of oxygen from PtO x to ZTO. [26] The resulting increase in depletion layer width leads to a decrease in tunneling current through the gate diode. Schlupp et al. showed that an additional thin intrinsic ZTO layer (i-ZTO) between channel and gate contact significantly enhances this effect without affecting the device properties otherwise. [2,27] Hence, an ≈10 nm thin i-ZTO layer was sputtered underneath the gate contact and on top of the conducting ZTO channel in a 25/5 sccm O 2 /Ar atmosphere prior to the deposition of the PtO x /Pt gate contact. Eventually, all gate contacts and their corresponding conduction paths were shorted by a final deposition of a thin Au layer in order to obtain ideal ohmic behavior within the circuits.
Current-voltage measurements and quasi-static capacitance-voltage measurements were carried out using an Agilent 4155C semiconductor parameter analyzer to obtain static current-voltage characteristics and the driving gate capacitance C G , respectively. The capacitance values, necessary for calculating the single stage delay times of the presented ring oscillators, were estimated for gate voltages between 0 and −0.5 V where the capacitance was nearly constant. All measurements were performed in the dark at ambient temperature. Electrical parameters of the ZTO channel layers such as the free-carrier concentration of n = 4.3 × 10 18 cm −3 and a free-carrier mobility of µ H = 5.4 cm 2 V −1 s −1 were determined by Hall effect measurements. Voltage oscillations of the presented ring oscillators were recorded using a Tiepie Engineering Handyscope HS3 oscilloscope. For signal outcoupling, a high input impedance active probe by GGB Industries Inc. was used to connect the output of ring oscillators to the input of the oscilloscope.