Interfacial Band Engineering of MoS2/Gold Interfaces Using Pyrimidine‐Containing Self‐Assembled Monolayers: Toward Contact‐Resistance‐Free Bottom‐Contacts

Bottom‐contact architectures with common electrode materials such as gold are crucial for the integration of 2D semiconductors into existing device concepts. The high contact resistance to gold—especially for bottom contacts—is, however, a general problem in 2D semiconductor thin‐film transistors. Pyrimidine‐containing self‐assembled monolayers on gold electrodes are investigated for tuning the electrode work functions in order to minimize that contact resistance. Their frequently ignored asymmetric and bias‐dependent nature is recorded by Kelvin probe force microscopy through a direct mapping of the potential drop across the channel during device operation. A reduction of the contact resistances exceeding two orders of magnitude is achieved via a suitable self‐assembled monolayer, which vastly improves the overall device performance.

the device-fabrication procedure and, thus, allows for a straightforward integration of 2D semiconductors into established technologies.
Implementing self-assembled monolayers (SAMs) to modify surface properties of electrodes has been demonstrated in organic electronics. [20][21][22][23][24][25][26] The SAM formation process is scalable and fully compatible with flexible substrates. [20] By a proper choice of the molecules, their anchoring, and their functional groups it is possible to fine-tune the electrode's WF. [23][24][25][26] Although the implementation of SAMs in organic electronics is well-understood, there is a lack of knowledge transfer to the field of 2D materials. This would, however, be highly attractive, as devices based on 2D semiconductors have already demonstrated GHz operation speeds, which is much more challenging to achieve in organic or metal-oxide TFTs. [5] The devices employed in this study constitute of gold (Au) source and drain electrodes with channel lengths of ≈10 µm, and aluminum bottom-gates with Al 2 O 3 gate dielectrics (see Figure 1a). This architecture allows low operation voltages due to the particularly small thickness (18 nm) of the gate dielectric, which is also crucial for simultaneously performing electrical and Kelvin probe force microscopy (KPFM) measurements. MoS 2 flakes were prepared by micromechanical exfoliation. Selected single-crystalline flakes were aligned with the transistor-substrates such that only one flake bridges the source and drain pads. [16] A step-by-step fabrication scheme is provided in Figure S1 (Supporting Information). 3-10 nm thick multilayer MoS 2 flakes (4-14 layers; see also Figure S2, Supporting Information) were selected since in this thickness range only small flake-to-flake variations of the electron affinity are expected. [3] Further, within the selected thickness range, the dependence of carrier mobility on thickness in the MoS 2 -TFTs is much less pronounced [3] and the mechanical robustness of the flakes is enhanced (compared to monolayers) allowing easier sample handling and higher transfer yield. Moreover, multilayer flakes are less sensitive to their environment than monolayers. This makes them particularly well suited for the present study, where the SAMs are used to change the electronic properties of the electrodes (especially their work functions) rather than to chemically alter the MoS 2 layers. [17] For more details on the suitability of multilayer MoS 2 , see Section S2 (Supporting Information).
As carrier layer for the transfer, either the tape commonly used for exfoliation with acrylic-based adhesives (Nitto) or polydimethylsiloxane (PDMS) films were employed. In most experiments, the carrier layers remained on the device for encapsulation. For KPFM measurements, the transfer layers were peeled off, leaving the top surface of the flake accessible.
WF engineering of Au electrodes was carried out prior to the transfer of MoS 2 by functionalization with aromatic SAMs. The SAM-forming molecules covalently anchor to the top-most gold atoms via a thiolate group, and the resulting SAM is sufficiently robust for allowing ambient exposure and MoS 2 transfer without compromising its functionality. A SAM backbone introduces a small tunneling barrier between Au and MoS 2 , but the impact of this barrier can be minimized by avoiding aliphatic spacers in the SAM-forming molecule and by keeping the aromatic backbones short. [26,27] The SAMs employed here exactly follow that design principle. In the parent SAM, the backbone consists of biphenyl; by substituting one of the phenyl-rings with a pyrimidine, a permanent dipole is embedded, which points along the long axis of the molecule and whose orientation can be  ) . controlled by the arrangement of the pyrimidine (see Figure 1b). The dipoles in the SAM pointing downward (upward) cause a WF increase (decrease) with respect to the dipole-free SAMtreated electrodes. [26,27] Overall, four different electrode treatments were tested: O 2 + H 2 plasma treated gold without SAMs as a reference, as well as 2-phenylpyrimidine-5-thiol (BP0-down), biphenyl-thiol (BP0), and 4-(2-mercaptophenyl)pyrimidine (BP0up) treated Au electrodes. The expected WF range for the SAMtreated Au electrodes [26,27] is presented in Figure 1b. Assuming vacuum-level alignment and an electron affinity of MoS 2 between 4.2 and 4.6 eV, [3] either BP0 or BP0-up should provide suitable band alignment with a low Schottky barrier. Notably, the exact magnitude of the electron affinity of MoS 2 depends on both, the layer number and possible doping of a particular flake. BP0-down SAMs serve as "negative example" to highlight the importance of the Schottky barrier between the electrodes and the MoS 2 layer for device operation. Typical electrical output characteristics (I D (V SD )) of MoS 2 -TFTs are presented in Figure 1c-f. A clear "S" shape of the output characteristics at lower V SD is observed, both for the bare Au reference and BP0-down treated electrodes (red arrows). This indicates a large Schottky barrier at the carrier injection point (grounded source electrode). [28] In order to extract ohmic and nonlinear components of the contact resistances, a fitting approach-as described in Refs. [26,29]-was applied to the sets of electrical output and transfer characteristics for the devices presented in Figure 1c-f. This fitting approach allows for a direct comparison to contact resistances obtained by KPFM, and provides data comparable to the transfer line method (TLM). [26,29] The details on the fitting of electrical characteristics and their relation to TLM are provided in Section S3 (Supporting Information). A hysteresis between forward and backward sweeps (Figure 1d) was observed in the case of Nitto-tape encapsulated devices, with more details provided in Section S4 (Supporting Information). Besides output characteristics, transfer curves (I D (V SG )) and extracted apparent linear electron mobilities (µ lin (V SG )) are presented in Figures S5 and S6 (Supporting Information). An aging experiment (in an Ar glovebox) is presented in Figure S7 (Supporting Information).
A detailed analysis of the transfer characteristics was conducted to extract performance parameters of MoS 2 -TFTs (see Figure 2). The scatter in the data mainly results from flake-toflake variations in width, thickness, and doping, originating from the exfoliation process. Figure 2a presents the ON/OFF ratios as a function of electrode treatment, taken from transfer curves at V SD = 1 V as: I D (V on +2 V)/I D (V on ), where V on represents the turn-on voltage. BP0 or BP0-up SAMs increase the ON/OFF ratio by over one order of magnitude compared to BP0-down and over two orders of magnitude compared to the Au-reference. Flake-width scaled ON/OFF ratios and ON-state I D 's are provided in Figure S8 (Supporting Information).
The corresponding apparent linear mobility (µ lin ) values (obtained employing the gradual channel approximation without explicitly considering the contact resistance) are presented in Figure 2b. µ lin values were taken at a specific operation point: Figure  S5, Supporting Information). The highest apparent mobility values (between 7.8 and 11.6 cm 2 V −1 s −1 ) were obtained for BP0treated electrodes, while devices containing reference Au and BP0-down treated electrodes exhibit µ lin < 1 cm 2 V −1 s −1 .
Besides the impact on device-hysteresis ( Figure S4, Supporting Information), the choice of the top encapsulation layer of the device primarily affects the turn-on voltages (Figure 2c), which were extracted from the transfer characteristics (at V SD = 0.2 V) as the source-gate voltage, V SG , at which I D starts to continuously rise above the gate-leakage current. charge transfer doping [30] from the acrylic-based adhesive to the MoS 2 flake. Threshold voltage engineering in MoS 2 -TFTs has already been demonstrated via molecular doping or SAMfunctionalization of the MoS 2 , [31,32] modifications of the gatedielectric surface, [33] or using ferroelectrics. [34] To directly measure the potential drops across the channels, KPFM measurements have been performed in organic-, graphene-, and MoS 2 -TFTs. [35][36][37][38] Here, we employed KPFM during device operation to obtain contact resistances at well-defined points of operation of our devices. Contact potential difference (CPD) profiles (V CPD ) across both electrodes and the active area of the device were recorded at each of these points of operation, while recording transfer and output characteristics. The V CPD profiles were then normalized [36] (further technical details are provided in Figures S9-S13, Supporting Information).
For the Au-reference and BP0-down treated samples, asymmetric V CPD profiles were observed (Figure 3a,b). Most of the applied potential drops at the source (V S ) as a result of a high injection barrier. Changing the direction of the applied bias results in a similarly high voltage drop at the other electrode ( Figure S12, Supporting Information). For BP0-treated electrodes (Figure 3c), the applied bias drops mainly across the channel (V ch ), exhibiting almost negligible contact resistances, supporting the notion mentioned above that BP0 SAMs are ideally suited for realizing bottom-contact MoS 2 TFTs. For BP0-up treated electrodes (Figure 3d), V S and the potential drop at the drain contact (V D ) are symmetric for the chosen operation conditions. This is insofar surprising, as the WF of BP0-up SAM covered contacts is expected to be resonant with or even smaller than the electron affinity of MoS 2 (where the latter in thermodynamic equilibrium ought to trigger interfacial charge transfer processes). Notably, the contact resistances for BP0-up SAMs also display a nonlinearly bias-dependent component, as discussed in Section S13 of the Supporting Information (c.f., Figure S13, Supporting Information). This points to more complex interfacial processes governing the properties of this particular interface.
Additional features-like wrinkles-occasionally introduced during the transfer, become apparent only in cases with low contact resistances. As shown in Figure 3c, changes in the slope of V CPD across the channel coincide with positions of the wrinkles. Considering all samples, where it was possible to observe V CPD drops that correspond to wrinkles, the width-scaled resistance of the wrinkles was estimated to be 20-40 Ω cm. Similar topographical features are also shown in Figure 3a. However, due to the much smaller values of I D the associated potential drops could not be observed.
In Figure 3e, the observed potential drops were converted to width-scaled resistance values for better comparison, where relative contributions of the injection (R S ) and extraction electrodes (R D ) are presented (note the logarithmic scale). The contact resistance drops by two orders of magnitude between BP0-down and BP0 treated electrodes and by almost three orders of magnitude when comparing Au-reference devices and devices containing BP0-treated electrodes. The lowest contact resistance values observed are on the order of 10 Ω cm, i.e., comparable to top-contact architectures. [1,14] Black circles with horizontal lines in Figure 3e represent the width-scaled contact resistances obtained from the device characteristics with the abovedescribed fitting procedure (see also Section S3, Supporting Information). They are reported for the same point of operation used for the KPFM measurements. The fitting analysis fully corroborates the distinction between large, mostly nonohmic resistances for Au and BP0-down treated contacts and profoundly reduced resistances for BP0 and BP0-up treated contacts. The differences between the contact resistances (especially in the BP0 case) obtained by the fitting approach and those measured by KPFM fall within the observed sample-to-sample variation (see also Figure 2). All W⋅R S/D values obtained by the fitting approach are listed in Table S1 (Supporting Information).
In summary, minimization of contact resistances between Au bottom-contacts and MoS 2 was demonstrated via electrode WF engineering employing dipolar SAMs. For the best matching SAMs, a reduction of the contact resistance exceeding two orders of magnitude was achieved compared to bare Au reference electrodes. This increases the ON/OFF ratio of the transistors by over two orders of magnitude and the apparent linear mobility by more than one order of magnitude. KPFM measurements during device operation-and independently the fitting of the electrical characteristics-revealed nonohmic contribution to contact resistances, highlighting the influence of the SAM-treatment on the reduction of the injection barrier. The proposed concept of SAM-based electrode modification is fully scalable, allowing a reliable integration of 2D semiconductors into bottom-contact architectures, while avoiding high-temperature annealing. It allows the realization of low contact resistance values (≈10 Ω cm) comparable even to carefully engineered top-contact devices. [1,14]

Experimental Section
Transistor Substrates: Transistor substrates were fabricated in a bottom-gate, bottom-contact architecture following the process-flow illustrated in Figure S1 (Supporting Information).
SAM Treatment: SAM treatment was done by immersion of freshly prepared samples into 100-500 × 10 −6 m ethanol (≈99.9 %, HPLC grade, VWR) solutions, for 18-72 h. Subsequently, the samples were rinsed several times with the pure solvent and dried in N 2 flow. Longer immersion times improved adhesion of MoS 2 , however, for immersions longer than 72 h, a roughening of the surface suggested the formation of molecular clusters. Data on surface energies (from contact angle measurements) and high-resolution X-ray photoelectron (XP) spectroscopy of SAM-treated Au electrode surfaces can be found in Refs. [26,27]. The XP spectra testify to the integrity of the films and the bonding of the thiols to the Au surface. [27] They also provide in-depth insight into the electronic structure of the SAMs. [26] The surface energies for BP0-down and BP0 SAMs are virtually identical (≈44 mJ m −2 ), while the surface energy of BP0-up is somewhat larger (≈57 mJ m −2 ). [26] This is primarily a consequence of a larger polar component of the surface energy, which is expected, as in BP0-up SAMs the polar bonds around the N-atoms in the pyrimidine ring are closer to the surface. Further, contact angle measurements, comparing reference to BP0-treated Au and Al 2 O 3 surfaces are provided in Section S14 and Table S2 (Supporting  Information). MoS 2 Flakes: MoS 2 flakes were prepared by exfoliation of a singlecrystal MoS 2 (HQ_graphene) with Nitto-Denko ELPBT150ECM. Some of the samples were then transferred to PDMS (GelPak_X4), by a single rapid peeling step of the prepared tape against PDMS. Areas of interest were selected by optical microscopy. They contained single flakes (common flake-size ≈10 × 20 µm 2 ) with the desired thickness. Cracks, folds, and flakes with nonuniform thickness were avoided. The areas-of-interest surrounding the selected flake (usually 500 × 500 µm 2 ) were cut from the remaining PDMS (or Nitto) film by a microtome blade, mounted on a micromanipulator, aligned relative to the transistor-substrate, and finally lowered into contact (see Figure  S1, Supporting Information). In cases where the transfer layer was kept as encapsulation, the whole stack was simply detached from the micromanipulator. In the case of nonencapsulated devices, the transfer layer (PDMS) was peeled off by heating the stack to 50-60 °C in order to release the flakes.
Electrical Characterization: Electrical characterization of the transistors was done under inert conditions in an Ar glove-box (MBraun with below 0.01 ppm of O 2 in Ar at ambient pressure) by means of a parametric analyzer from mb technologies. The samples were contacted with electrical microprobes from Suess Micro Tec (Micro Manipulator -PH150) on a vacuum chuck. Electrical measurements performed simultaneously with KPFM were carried out in air (under atomic force microscope -AFM) using a Keithley 2636A SourceMeter.
KPFM Measurements: KPFM measurements were carried out in amplitude modulation using Asylum research MFP3D and AIST-NT AFM systems. Top-visual AppNano AccessEFM probes with a spring constant of ≈2.7 Nm −1 and a tip radius of ≈30 nm were used. Lift heights were minimized for each measurement to reduce parasitic capacitance, with typical values below 20 nm. For each simultaneous KPFM and electrical output/transfer experiment, at least ten line profiles were measured for each point of operation (V SD , V SG ) of the device and exactly ten lines were averaged. Profile lines measured while changing the point of operation of the device were excluded from the analysis. Further, before and after each simultaneous KPFM and electrical output/transfer experiment, scans with grounded S and D electrodes were measured and their mean value was used to correct for stray fields. If V CPD crosssections of the measurement with grounded electrodes before and after the simultaneous KPFM and electrical output/transfer experiment were found to deviate from each other by more than 5%, the experiment was repeated. This procedure ensures stable measurement conditions, where during measurements no significant changes occur either to the device or to the probe. For more details, see also Figures S9-S13 (Supporting Information).

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.