Large-Scale-Compatible Stabilization of a 2D Semiconductor Platform toward Discrete Components

− 1 for some devices), which represents an increase by a 40-fold factor compared to a conventional process carried on the large scale platform. This work represents an important step toward the integration of 2D TMDCs in discrete RF circuits and components. defined on the substrate. These were designed to resist the gold layer etching step during 2D deposition process. Further device structures were defined by PVD metal depositions and lift-off processes. Dielectric Deposition : For the PVD deposition, the samples were transferred under inert atmosphere into an ultra-high vacuum evaporator system (base pressure10 –8 mbar). A 1 nm-thick layer of metallic Al was evaporated on the sample (the deposited thickness and the deposition rate of 40 pm s − 1 were controlled using a quartz crystal microbalance) and was then exposed to air so that the Al was oxidized instantly to form an Al 2 O 3 passivation layer. Electrical Characterization : All electrical measurements were performed under ambient conditions at room temperature using a Keithley 4200 electrical characterization bench.

In this study, we introduce a large-scale compatible fabrication process-flow leading to properties stabilization of the prototypical MoS 2 . In our work we focused on the fabrication process with this early technological implementation in mind. Thus, to properly develop the early technological bricks essential for our device realization, we defined four key requirements: i) work on relatively large surfaces of material (>1000 µm²) to realistically integrate properties over large-scale material and extract a mean value relevant to the considered platform exploitation compatible with discrete component fabrication (Figure 1). ii) Be compatible with targeted applications (CMOS and RF) relying on a low-loss low-cost substrate already used in many RF applications. [10,[22][23][24][25][26] For this reason we selected an already known substrate, highly-resistive silicon covered by 780 nm of SiO 2 (HR-Si/SiO 2 ). iii) Develop processes that are compatible with large-scale integration (at least 4-inches wafer). All our processes need to be scalable in terms of passivation, lithography processes for contacts deposition or etching. This is why we chose to focus on scalable physical vapor deposition (PVD) and atomic layer deposition (ALD) processes (Figures 2 and 3). iv) Stabilize the 2D material's electronical properties with clear ON/OFF states (Figure 4). In the following, we detail our process step by step considering the necessary requirements stated above.

Results and Discussion
Following the first requirement (i), we focused on a large MoS 2 surface with a size on par with crystals domains reached by CVD processes, [27,28] but achieved from bulk crystals thanks to an adapted exfoliation process as exfoliated material an RF compatible substrate. The whole surface is covered with MoS 2 . A specific zone with a scratch is selected for the Raman map in (d) to show some contrast. c) Corresponding Raman spectrum of MoS 2 monolayer. d) Large Raman mapping of the A′ 1 mode intensity (red for high intensity to black for zero intensity) performed on the highlighted part of the image in (b) and showing high homogeneity of the MoS 2 monolayer. e) Photoluminescence spectrum corresponding to MoS 2 monolayer. www.advelectronicmat.de quality remains the reference for the field. Crucially, we took care that our process remained fully compatible with any future emerging large-scale 2D material source. Since interlayer force for MoS 2 [29] (29 × 10 18 N m −3 ) is stronger than for graphene [30] (12.8 × 10 18 N m −3 ), the yield of thin flakes of MoS 2 resulting from tape method exfoliation [1] is poor. [31] To alleviate this issue we opted for a modified exfoliation process flow following the work of Desai and coworkers. [32] This process is schematized in Figure 1a. First, bulk material is exfoliated from the crystal using a standard scotch tape exfoliation technique. We then evaporate a layer of gold (≈100 nm) on top of the MoS 2 which bonds with the chalcogen (sulfur) atoms of the upper layer. This is the key step of this process as the interaction between chalcogen and gold is known to be stronger than van der Waals forces between the MoS 2 layers. [33] This allows us to selectively exfoliate the topmost monolayer of MoS 2 using a thermal release tape (TRT). Then, we transfer the MoS 2 /Au/ TRT stack onto the targeted HR-Si/SiO 2 substrate. The TRT is heated (≈90 °C) to release Au and underlying MoS 2 onto the substrate. We used a KI/I 2 wet etch diluted in water to etch Au without damaging MoS 2 . Finally, we end up with large monolayers of MoS 2 on HR-Si/SiO 2 substrate. TRT process is a solution we adopted to derive a reference exfoliated crystal on scales large enough to assess our encapsulation approach. While this whole approach already allows to produce devices on small-scale for discrete components demonstrators-a crucial starting point for industrial developments-we envision it to be applied to any emerging large scale 2D fabrication.
We present in Figure 1b-e characterization of the MoS 2 transferred on the HR-Si/SiO 2 substrate. Figure 1b displays an optical image of the derived MoS 2 layer with a feeble contrast pointing to its monolayer nature. The Raman spectrum of this layer (514 nm laser) under ambient conditions is shown in Figure 1c. The difference between A′ 1 and E′ modes (Δω ≈ 17.5 cm -1 ) confirms the presence of a monolayer. [34] Additionally, a map of the Raman A′ 1 mode intensity is presented in Figure 1d highlighting the flake homogeneity. In Figure 1e the flake photoluminescence (PL) spectrum is presented where a direct bandgap of ≈1.85 eV, consistent with reported literature value for the monolayer, can be clearly observed. [35] All these characterizations confirm the presence of a monolayer with a surface of about 10 4 µm 2 , 3-4 orders of magnitude larger than the standard exfoliation approach.
Since conventional O 2 plasma treatment classically used in microelectronics to remove residual resist after lithographic processes would lead to etch the MoS 2 , [36] a classical fabrication process (Figure 2a) resulted in devices with really high contact resistances (>10 GΩ µm) not allowing electrical characterization. To overcome this issue, we developed the protection/passivation process described in Figure 2b starting from the 2D layer on HR-Si substrates to follow requirement (ii). The next steps were developed following requirement (iii) of choosing processes that are compatible with large-scale integration. First, we deposited a thin aluminum layer by PVD and we further oxidized it in air, resulting in a continuous protection layer of ≈1 nm of alumina (Al 2 O 3 ) over the sample. This protection layer was shown not to damage 2D materials [10,37] but also to prevent their degradation under ambient atmosphere. [38] This allows to protect MoS 2 ahead of the technological steps. For example, during a lift-off process, the MoS 2 layer is never directly in contact with the resist. The MoS 2 layer was then etched to define the device channel. The next step was contact metal deposition. Here, the protection layer was removed by using tetramethylammonium hydroxide (TMAH) diluted in water (1:4) before performing the metal evaporation. Finally, we encapsulated the device in a passivation layer consisting in 10 nm of Al 2 O 3 grown by atomic layer deposition (ALD). In the following we describe the characterization of this protection/ passivation process and show that it leads to a MoS 2 platform stabilized against environment.
We performed Raman and PL spectroscopies after both the protection and passivation steps in order to see how the MoS 2 properties were influenced. We observed that Raman spectra (see Figure 3b) were affected by the protection/passivation process. The process induced a red-shift of the A′ 1 mode but no obvious modification for the E′ mode which could correspond to a decrease of the environmental p-type dopant. [39] A special representation allows extraction of the MoS 2 doping variation by taking into account strain variations. [40] It consists in representing the A′ 1 as a function of the E′ mode (see Figure 3a). In our case, we obtain a reduction of the environmental p-type Adv. Electron. Mater. 2021, 7, 2001109   Figure 2. a) Standard process compared to b) protection/passivation process used for our device fabrication: the use of Al 2 O 3 layers before and after fabrication allows to preserve the transport characteristics of the 2D semiconductor.
www.advelectronicmat.de doping. In Figure 3c,d the PL spectroscopy of monolayer MoS 2 is presented at each process step and we can see a PL intensity drop as well as red-shift of the bandgap which can be attributed to the same doping modification observed in Raman spectroscopy. [39] This is in-line with previous studies showing that this protection/passivation process affects graphene doping, [37] reducing the p-doping caused by ambient conditions. Finally, we present electrical transport characterization. Thanks to this protection/passivation process, we could observe a contact resistance improvement allowing to electrically characterize our device. We chose to realize a Hall bar design where probes are deported as shown in Figure 4a: this results in more robust non-invasive measurements. [41,42] We use a backgate voltage applied directly to the substrate that allows us to extract the threshold voltage (V T ), I ON /I OFF ratio and four-probe field-effect carrier mobility (μ eff ) of the device. Figure 4b shows the drain-source current versus backgate voltage with a constant drain-source bias of 5 V. We can notice that adding the passivation layer on top of the channel, reduces the absolute value of the electric field corresponding to the threshold voltage V T by 50% from 0.26 V nm −1 to approximately 0.13 V nm −1 (for a 780 nm SiO 2 layer). More importantly, the passivation layer increases the I ON /I OFF ratio by two orders of magnitude to a value of ≈10 6 , allowing higher current intensity through the channel. Already an I ON /I OFF ratio in the range of 10 4 to 5 × 10 7 (depending on requirements, high performances or low-power) is in-line with requirements for FETs to be used in CMOS logic, [43,44] and we note that even further improvements can be foreseen. [45,46] This is well in agreement with the observed reduction of environmental p-doping of the n-type MoS 2 channel by Raman and PL analyses, as explained before (Figure 3) allowing us to reach higher I ON . We note that this Adv. Electron. Mater. 2021, 7, 2001109   Figure 3. Raman and photoluminescence characterizations of MoS 2 : as exfoliated (black), with protection layer (dark purple) and with protection + passivation layers (light purple). a) ω(A′ 1 ) versus ω(E′) recorded at various positions at each step of the process. Arrow represents the increase of p-type doping for unprotected channels and the dotted lines are just a guide for the eye representing strain and doping variations. b) Raman spectra taken at each step, dotted lines represent the Raman shifts of the as exfoliated sample. c) Photoluminescence intensity versus peak energy at various positions taken at each step. Arrow represents the increase of p-type doping for unprotected channels. d) Photoluminescence spectra taken at each step.

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result has been well reproduced showing the stabilization of the properties with similar mobility, threshold voltage, and saturation velocity being extracted: the variability is reduced when using our protection/passivation scheme (see Figure S1, Supporting Information). This result has been well confirmed on >10 devices without noticing a change in extracted characteristics, confirming that fabricated long devices give a reliable averaged response. Next, we extracted the four-probe fieldeffect carrier mobility (μ eff ) of our devices following Lembke et al. [42] The four-probe conductivity σ of the MoS 2 monolayer was found from L W where L CH is the length of the channel separating the voltage probes (≈12 µm), W is the width of this channel (≈3 µm), I DS is the drain-source current, and ΔV is the potential drop between the two central voltage probes (see Figure 4a). From this conductivity, the extracted four-probe field-effect carrier mobility was derived using 1 d d eff OX BG µ σ = C V where C OX is the oxide capacitance and V BG is the applied backgate voltage. In the following discussion, we assume the capacitance to be 4.5 10 F m In the inset of Figure 4b, we can see a comparison of the different four-probe field-effect mobilities that can be extracted as a function of the different fabrication processes used. The standard process without any protection is given as reference. As expected, this process gives rise to a limited four-probe fieldeffect mobility ≈0.5 cm 2 V −1 s −1 in average. As a comparison, the mobility obtained on small non passivated exfoliated MoS 2 are on the range of 0.1-13 cm 2 V −1 s −1 . [45,47] For CVD material, the mobility is approximately in the same range. [48,49] Using our protection layer during the process leads to a higher mobility of ≈6 cm 2 V −1 s −1 for our long channel 2D device, highlighting an increase of more than one order of magnitude compared to standard process. This shows the importance of protecting the MoS 2 right from the beginning. Remarkably, the final passivation layer, which is the last step of our process, leads to an additional three-fold increase of the averaged mobility to ≈20 cm 2 V −1 s −1 (up to 35 cm 2 V −1 s −1 for some devices, see Supporting Information). While working with constraints i) large 2D layers, ii) CMOS and RF compatible substrate, iii) large scale processing, and iv) stabilized ON/OFF conditions, we are thus able to observe device characteristics on par with those obtained with much shorter exfoliated 2D channels in similar ambient atmosphere at room-temperature (see Figure S1, Supporting Information). [46,[50][51][52][53] Beyond this positive result, further improvements are foreseen for such 2D platforms: high mobility values have been reported for instance using an additional chemical treatment [46,54] or vacuum conditions. [42,54] Moreover, while exfoliated material remain the acknowledged reference, some studies have already shown the striking potential of CVD grown layers with large mobilities. [55][56][57][58]

Conclusion
In conclusion, we present in this study a process flow toward the implementation of a large-scale compatible 2D semiconductor platform constrained by key technical requirements toward integration in small series of discrete functional devices. The results we present in this study would certainly benefit many different fields such as RF, [12,13] digital applications, [59] analogic devices, [60] optoelectronics, [61] spintronics, [8] and beyond. We made use of large 2D layers compatible with the definition of discrete components and basic cascading, CMOS and RF compatible substrates, scalable PVD and ALD processing, and aimed stabilized ON/OFF conditions. Following these requirements, we already measured transport characteristics equivalent to much shorter exfoliated 2D MoS 2 channels previously reported and a 40-fold improvement of the four-probe field-effect mobility. Our successful protection/passivation results, complementary to first large-scale 2D semiconductor growths [27,28] and test-line wafer scale device integrations [4,6] reported recently, highlight a very positive path for the definition of highly-efficient large-scale 2D semiconductor platforms.

Experimental Section
Device Fabrication: Devices were fabricated on relevant SiO 2 /HR-Si substrate. As an initial fabrication step, Ti/Pt alignment marks were Adv. Electron  applied with a constant source-drain bias (V DS ) of 5 V for the protected sample with and without passivation. The protection/passivation process allows to restore a large ON/OFF ratio. Inset: relative four-probes field-effect mobility (μ eff ) comparison for the different fabrication processes. The protection/passivation process leads to a 40-fold increase in the mobility.

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Adv. Electron. Mater. 2021, 7, 2001109 defined on the substrate. These were designed to resist the gold layer etching step during 2D deposition process. Further device structures were defined by PVD metal depositions and lift-off processes.
Dielectric Deposition: For the PVD deposition, the samples were transferred under inert atmosphere into an ultra-high vacuum evaporator system (base pressure10 -8 mbar). A 1 nm-thick layer of metallic Al was evaporated on the sample (the deposited thickness and the deposition rate of 40 pm s −1 were controlled using a quartz crystal microbalance) and was then exposed to air so that the Al was oxidized instantly to form an Al 2 O 3 passivation layer.
Electrical Characterization: All electrical measurements were performed under ambient conditions at room temperature using a Keithley 4200 electrical characterization bench.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.