Polycrystalline Ge Nanosheets Embedded in Metal‐Semiconductor Heterostructures Enabling Wafer‐Scale 3D Integration of Ge Nanodevices with Self‐Aligned Al Contacts

The ability to stack nanosheet transistors is an important prerequisite for the realization of vertically monolithic 3D integrated circuits enabling higher integration densities of functions and novel circuit topologies that relax miniaturization constraints. In this respect, a wafer‐scale platform is presented embedding high‐quality nanoscale polycrystalline Ge channels into monolithic metal‐semiconductor heterostructures. Thereto, a fabrication scheme comprising a combination of flash lamp annealing, crystallizing ultra‐thin amorphous Ge nanosheets, and a thermally induced Al‐Ge exchange reaction is demonstrated, facilitating the formation of self‐aligned Al leads enabling sharp Al‐Ge heterojunctions. The high quality of the obtained polycrystalline Al‐Ge‐Al heterostructure nanosheets is confirmed by µ‐Raman, scanning transmission electron microscopy, energy‐dispersive X‐ray spectroscopy, and electron backscatter diffraction measurements. Embedded in back‐ and top‐gate field‐effect transistor architectures, the electrical transport in polycrystalline Al‐Ge‐Al heterostructures is systematically analyzed. Enabling a complementary metal‐oxide‐semiconductor compatible wafer‐scale accessibility of high‐quality polycrystalline Ge with self‐aligned Al contacts, the proposed platform significantly contributes to the development of a broad spectrum of emerging 3D integrated Ge nanodevices.

like self-aligned germanide [19] contacts and pure metal-semiconductor junctions like Al-Ge heterostructures [20,21] were developed. As scaling limitations of the gate length affect these devices likewise to metal-oxide-semiconductor (MOS) FETs, the stacking of such high-speed low-power thin-film transistors on interlayer dielectrics is attractive for the realization of vertically monolithic 3D integrated circuits with higher functional integration relaxing sizing constrains of the individual semiconductor devices. [22,23]

Results and Discussion
In this paper, we present a wafer-scale approach to achieve polycrystalline Ge nanosheets crystallized by FLA embedded in monolithic Al-Ge-Al heterostructures as formed via a thermally induced Al-Ge exchange reaction. Figure 1a shows exemplarily the fabrication scheme for an individual polycrystalline Al-Ge-Al heterostructure device. However, without restrictions, this technique enables the parallel processing of arrays of structures of different geometry on a wafer-scale. First, nanosheets are patterned onto a highly p-doped Si wafer using electron beam lithography (EBL), evaporation of 2 to 50 nm thin amorphous Ge, and lift-off techniques. Next, plasma-enhanced chemical vapor deposition (PECVD) is used to deposit a SiO 2 capping layer before FLA is applied to initiate the crystallization of the amorphous Ge nanosheets. Al contact pads are fabricated by optical lithography, native oxide removal, sputter deposition, and lift-off techniques. Finally, the actual heterostructure formation is induced by rapid thermal annealing (RTA) at a temperature of T = 624 K in forming gas atmosphere. Figure 1b shows SEM images of Ge structures with different widths (W) of the Ge pattern contacted by Al pads after RTA. The images reveal dark segments emerging from the contacts, which prolonged along the Ge structures during RTA. Overlaying the SEM image of the upper left nanosheet heterostructure with its energy-dispersive X-ray spectroscopy (EDX) map confirms an Al-Ge-Al structure comprising Al contacts connecting a Ge segment of length L. Additional EDX maps of Al-Ge-Al heterostructure nanosheets with different width are shown in Figure S1, Supporting Information.
To achieve short Ge channels, we use consecutive annealing steps, accompanied by ex situ SEM imaging. Figure 1c shows SEM images of a typical annealing sequence, finally resulting in a 100 nm long Ge channel embedded in a monolithic polycrystalline Al-Ge-Al heterostructure. To demonstrate that the proposed heterostructure formation process enables the formation of short Ge channels embedded in Al-Ge-Al heterostructures with abrupt Al-Ge junctions, Figure S2, Supporting Information shows a SEM image of a heterostructure nanosheet with a width of W = 50 nm, a height of h = 25 nm and a metallurgic Ge channel length of L = 40 nm.
To prove the crystallinity of the Ge segment embedded in the Al-Ge-Al heterostructure, a cross-sectional scanning transmission electron microscopy (STEM) at one of the Al-Ge interfaces of a 1 µm wide, 25 nm thick and 1.5 µm long Ge segment was conducted (Figure 2a). The enlarged view shows a closeup high-angle annular dark-field (HADF) STEM image of the Al-Ge junction. Figure 2b shows an EDX line-scan revealing a sharp Al-Ge interface. The grain-size of the Ge segment with h = 25 nm is ≈20 nm × 20 nm ( Figure S3, Supporting Information). This is in agreement with studies on polycrystalline Ge layers formed by SPC, showing that the grain size dramatically decreases for thinner structures. [22[ Further, Figure 2c shows a comparison of the normalized µ-Raman spectrum of an amorphous (black) and different Ge nanosheets flashed with energies between E = 60 and 90 J cm − ² (maximum energy of the FLA system). While the amorphous Ge nanosheet shows a broad peak, signs of crystallization are observable for FLA Ge nanosheets with the peak becoming sharper and more symmetric for increased FLA energies. The µ-Raman spectra of the FLA Ge nanosheet reveal a distinct peak assigned to the Stokes transverse optical (TO) modes of Ge at ≈301 cm -1 . [24][25][26] For benchmarking, Figure S4, Supporting Information compares the µ-Raman spectra of our polycrystalline Ge nanosheets obtained by FLA, with ones that we have crystallized using a more common SPC procedure (T = 773 K for t = 10 h in N 2 atmosphere). [13] Indicating a higher quality polycrystalline Ge, a much narrower Ge TO mode was found for the FLA based polycrystalline Ge nanosheets (E = 90 J cm −2 ). Further, the successful FLA crystallization approach is advantageous to enable an overstacking of functional polycrystalline Ge layers in a CMOS fabrication environment, as only the surface is highly heated without substantially altering the substrate temperature. An example for such a process flow is supplied in the supporting information. Further, one of the key advantages of the FLA process is its ultrashort heating time, which prohibits significant dopant diffusion commonly observed for SPC. In particular, intermixing and diffusion in the proposed device fabrication scheme are further excluded by the encapsulation of the amorphous Ge nanosheets by SiO 2 .
Further, Figure 2d reveals that the full width at half maximum (FWHM) of the Ge mode approaches the bulk value of crystalline Ge (Γ = 3.4 cm -1 ), [27] which indicates a higher degree of crystallinity by increasing the applied FLA energy. [28] Moreover, in agreement with quantum confinement, Figure 2e reveals that a thinner polycrystalline Ge results in a down-shift of the Ge TO mode. [29] To investigate the electrical transport properties of our polycrystalline Al-Ge-Al heterostructures, Figure 3a shows the resistivity calculated from temperature-dependent I/V measurements as a function of temperature in the range between T = 77.5 and 400 K compared to a polycrystalline Al nanosheet. Two-terminal measurements were conducted, given the intruding nature of the Al contacts that hinders the validity of four-probe measurements. The extracted resistivity includes a series resistance originating from the polycrystalline Al leads of the heterostructure, as well as the one related to the expected Schottky junctions. To determine the influence of this series resistance, the resistivity of a fully transformed polycrystalline Al nanosheet with a width of W = 2 µm, a height of h = 5 nm, and a length of L Al = 3.3 µm was evaluated. Based on these investigations, a resistivity ρ = 100 × 10 -9 Ωm was calculated, which is ≈7.5 times larger than the bulk value of Al. [30] This might be related to an increased influence of surface scattering in nanostructures [31] as well as to the sizeeffect of polycrystalline interconnects given by the contribution of scattering at crystallite grain boundaries as observed in Cu nano-interconnects [32] or due to current crowding at the www.advelectronicmat.de Al-lead/Al nanosheet interface as seen in metallic nanocrystalline carbon vias. [33] Upon cooling, the resistivity of the polycrystalline Al nanosheet is decreasing, which is associated with a decrease of phonon scattering at lower temperatures and is typical for metals. [34] As the resistance of an Al nanosheet is approximately six orders of magnitude smaller compared to polycrystalline Al-Ge-Al heterostructures, the parasitic resistance of the Al leads to the Ge channel is in our case negligible.
Indicating diffusive transport, the resistivity of the polycrystalline Al-Ge-Al devices reveals a distinct temperature dependency. In such long Ge channels, the device resistance originates from scattering with phonons, crystal defects, and impurities. [35] While, upon cool-down to T = 200 K, a gradual increase of resistivity was www.advelectronicmat.de measured, below this temperature, the resistivity appeared to decrease again. As polycrystalline Ge nanostructures obtained by FLA are known to be naturally p-type, [36] we associate this effect to the extrinsic nature of the material, which exhibits a relatively constant carrier concentration and a significant mobility increase in this temperature regime. [37,38] To investigate the quality of our polycrystalline Al nanosheets, we determined the current-carrying capacity by gradually increasing the current through the nanosheets in a two-terminal configuration while monitoring the voltage across the device.
The inset of Figure 3b shows exemplary I/V characteristics recorded for three polycrystalline Al nanosheets with widths of W = 2, 1, and 0.3 µm. The step-like decrease of the current indicates the breakdown of the nanosheet. For all investigated Al nanosheets, the slope of the I/V curve, that is, the resistance, increased right before the point of failure, which is an indication of effective Joule heating ultimately leading to a melting induced failure. [39] Calculating the maximum current density (J max ) leads to the remarkable result, that narrower nanosheets reveal a significantly higher failure current density compared to wider ones, with a peak value of J max = 4.8 × 10 12 A m −2 for a width of W = 100 nm. Such exceptional ampacity values of thin metallic nanostructures were also observed for Au NWs [40,41] and Cu NWs [39] and are attributed to the combination of efficient heat dissipation due to the high surface-to-volume ratio and the high quality of the polycrystalline Al nanosheets. [39] Thus, to investigate the crystal structure and interface morphology of the formed Al-Ge heterostructures in more detail, we performed an electron backscatter diffraction (EBSD) analysis. The insets of Figure 3b show the EBSD maps of representative structures with widths between www.advelectronicmat.de W = 2 µm and 300 nm. For wider structures, the Al contacts appeared to be polycrystalline with grain sizes in the µm range. For narrower structures, the number of grains decreases. Thus, for structures with widths below W = 400 nm and Al contacts on both sides, long annealing times result in a full transformation of the Ge nanosheets in pure Al consisting of only two monocrystalline segments. Commonly observed, deposited Al contacts are known to show strong electromigration. [42] However, as Al nanosheets with W < 400 nm fabricated from Al-Ge exchange show only two grains (one growing from each side) and reveal significantly higher J max compared to wider structures, electromigration could be strongly diminished. In this respect, reliability tests of monocrystalline Al nanowires fabricated by Al-Ge exchange have shown a long-term stability exceeding the maximum current densities of bulk Al. [43] Despite the advantages of our monocrystalline Al contacts, we want to note that the use of our Al material should be restricted to the intimate metal/ semiconductor contact, and that conventional, for example, Cu materials shall be used for the remaining interconnects.
Importantly, for Al-Ge-Al devices with W < 400 nm, we have also noticed a flatter and sharper Al-Ge interface (see Figure 1b and Figure S2, Supporting Information).
Next, transfer characteristic measurements were conducted to determine the modulation capability of the charge-carrier type and concentration in the Ge channel using the p-doped Si substrate as a common back-gate. The upper inset of Figure 4a provides a schematic illustration of the device architecture and the respective biasing. The main plot of Figure 4a shows the typical transfer characteristic of a FET device with a 5 nm thick Ge channel and a length of L = 100 nm recorded with a gate voltage sweeping rate of 0.25 V s −1 at T = 295 K.
Biasing with V D = 1, 10, and 100 mV (Figure 4b), the device exhibits a weak ambipolar transfer characteristic, with hole accumulation for V G < 20 V and moderate inversion for Figure S8, Supporting Information shows a contour plot of an I/V measurement between V D = −1 to 1 V for sweeping the back-gate voltages between V BG = −40 and 40 V. At V D = 1 V peak current densities of J h = 1.5 × 10 8 A m −2 (holes) and J e = 2 × 10 6 A m −2 (electrons) were calculated.
Further, we observed a pronounced hysteresis not only dependent on V BG , but also the gate voltage sweeping direction. This behavior should be related to the commonly observed surface-doping [44,45] effect of Ge based nanodevices where acceptor-like traps shift the energy band structure throughout the Ge channel, causing the usual p-type behavior of nominally intrinsic Ge nanodevices. [44,46] Further, the transfer characteristic remarkably reveals that even applying low drain voltages down to V D = 1 mV, an I ON /I OFF ratio of ≈10 2 can be achieved. Assuming thermionic emission, the effective Schottky barrier height (SBH) for electrons of the Al-Ge junction can be obtained from the slope of the activation energy plot of ln(J/T 2 ) versus 1000/T at various bias voltages (see supporting information). The thereof calculated SBH in the sub-threshold region of electron-driven transport was estimated to be 102 ± 10 meV. Further, as shown in Figure S9, Supporting Information, the overall resistance of the polycrystalline Al-Ge-Al heterostructure devices with a structural width of W = 2 µm is directly proportional to the Ge segment length corresponding to a resistivity of ρ = 2 ± 1 Ωm, which is almost a decade lower compared to similar devices without FLA treatment (see Figure S10, Supporting Information). We associate the dominant p-type conduction and the observed small effective Schottky barrier of our Al-Ge-Al heterostructure nanosheets to defects in the polycrystalline Ge channel providing shallow acceptor levels generating holes at room temperature, which is in agreement with previous studies. [47] Notably, this effect appeared to be more pronounced with increasing layer thickness as only negative effective Schottky barriers could be found for heterostructures with www.advelectronicmat.de a sheet height of h = 25 nm, indicating a barrier thin enough for tunneling resulting in a quasi-ohmic contact. [48] Figure 4c shows the temperature dependence of the transfer characteristic for V D = 100 mV between T = 295 and 380 K, indicating a positive variation with increasing temperature. As expected from theory, the characteristic flattens and an increase of the OFF-current with temperature is evident, which can be attributed to thermally generated carriers. [12,35] Nevertheless, ambipolar device operation can still be observed for all investigated temperatures.
To improve the electrostatic control of the Ge channel and to decrease the absolute value of the applied gate voltage, an omega-shaped top-gate (TG) was fabricated. Thereto, the Al-Ge-Al heterostructure nanosheets were coated with a 14 nm thick Al 2 O 3 passivation grown by atomic layer deposition (ALD) and a source/drain (S/D) overlapping gate-contact was fabricated (see Figure 5a).
At this point, we want to note that although intrinsic Ge was used for device fabrication, negative surface charges accumulating in interband trap levels [44,49] contribute to an overall p-type behavior of the FET devices for both the bare as well as the Al 2 O 3 passivated Ge nanosheets. Further, as adsorbates influence the electrical behavior, it was mandatory to passivate the Ge channel prior to the Al-Ge heterostructure formation to reduce interface traps and surface disorder. [50] In agreement with previous reports, [51] using a high-k passivation layer results in less pronounced hysteresis effects. However, according to Zhang et al., [52] we assume that during the ALD process, a thin GeO x layer is formed at the interface between the Ge nanosheet and the Al 2 O 3 passivation. Thereto advanced measures are required to reduce interface trap densities by the appropriate use of interlayer dielectrics. This could for instance include the removal/desorption of native GeO x and the subsequent ordered stoichiometric thermal growth of GeO 2 and/or posterior Ge oxy-nitride formation in order to reduce the level of interface states at the dielectric/germanium interface. [53] Transfer characteristics of a polycrystalline Al-Ge-Al heterostructure nanosheet with W = 2 µm, h = 5 nm, and L = 300 nm a bias voltage of V D = 100 mV are shown in Figure 5b. Similar to polycrystalline Al-Ge-Al heterostructure nanosheets in backgate configuration, a hysteresis not only dependent on V TG , but also the gate voltage sweeping direction and a slight ambipolar behavior was observed. Remarkably, as shown in Figure 5c, comparing the transfer characteristics recorded for bias voltages between V D = 100 µV and 1 V, reveals that even applying ultra-low drain voltages down to V D = 100 µV, an I ON /I OFF ratio of ≈5 × 10 4 can be achieved. At V D = 1 V, we calculated peak current densities J h = 3.6 × 10 9 A m − ² and J e = 3.7 × 10 6 A m −2 (see Figure S11, Supporting Information). Compared to the backgated device architecture, the current densities have improved by a factor of 24 and 1.8 respectively. Applying V D = 100 µV, it was still possible to achieve J h = 0.6 × 10 5 A m −2 and J e = 5.7 × 10 2 A m − ². For our top-gated (TG) devices an enhanced subthreshold swing of SS = d[log(I D )]/dV TG = 1.1 ± 0.2 V per decade was extracted. Figure S12, Supporting Information shows a contour plot of an I/V measurement between V D = −1 to 1 V for sweeping the TG voltages between V TG = −5 and 5 V.
As drain-induced barrier lowering (DIBL) could be a problem of small channel devices, advanced devices will have substantially thinner physical thicknesses of the gate dielectric. In the case of our polycrystalline Ge devices, the small bandgap comes on top in further deteriorating the off-state. However, our device platform is intended to be used to facilitate emerging device concepts such as reconfigurable FETs [8,54] with gate-electrodes covering the metal-semiconductor interfaces to change the device operation from an ambipolar characteristic to either a unipolar p-or n-type characteristic. As typical channel lengths The performed systematic investigation of polycrystalline Al-Ge-Al heterostructure nanosheets embedded in back-and TG FET architectures confirmed their quality and revealed their high potential as a wafer-scale platform for the cost-efficient implementation of novel electronic devices and may pave the way for an unprecedented realization of circuits comprising stacked ultra-thin-body Ge FETs for 3D large-scale integration.

Conclusion
In conclusion, combining fully CMOS compatible Ge evaporation, FLA crystallization, and RTA annealing techniques, we explored a platform enabling a wafer-scale approach for the formation of nanoscale polycrystalline Ge nanosheets monolithically embedded in a metal-semiconductor architecture comprising self-aligned Al contacts and sharp Al-Ge heterojunctions enabling source/drain overlapping gate-contacts. A structural analysis of the obtained polycrystalline Al-Ge-Al heterostructure nanosheets was confirmed by µ-Raman, EDX, and EBSD measurements. Embedded in back-and TG FET architectures, the electrical transport properties of the proposed polycrystalline Al-Ge-Al heterojunctions were systematically probed and analyzed. We associate the p-type conduction and the observed small effective Schottky barrier of only 102 ± 10 meV to defects in the polycrystalline Ge channel providing shallow acceptor levels. At V D = 1 V, we calculated peak current densities of J h = 3.6 × 10 9 A m −2 and J e = 3.7 × 10 6 A m −2 . Remarkably, even applying ultra-low drain voltages down to V D = 100 µV, an I ON /I OFF ratio of 10 4 can be achieved. Further, the Al nanosheets connecting the Ge channel withstand remarkably high current densities of up to 5 × 10 12 A m −2 , www.advelectronicmat.de important for their application as interconnects. Most notably, enabling a wafer-scale accessibility of nanoscale polycrystalline Ge with self-aligned Al contacts, the proposed architecture is perfectly suited for emerging device platforms such as stacked 3D integrated circuits, system-on-glass, or flexible electronics.

Experimental Section
Device Fabrication: Amorphous Ge nanosheets with adjustable layer thicknesses between h = 2 and 50 nm were grown onto a 100 nm thick thermally grown SiO 2 layer atop of a 500 µm thick highly p-doped Si substrate. Thereto, a combination of EBL, electron beam assisted evaporation (10 kV, base pressure 2.5 × 10 -8 mbar, intrinsic Ge with 99.999% purity), and lift-off techniques were used. The amorphous Ge structures were capped with 100 nm of PECVD grown SiO 2 deposited at T = 573 K in order to provide a protective layer. Crystallization of the amorphous Ge structures was achieved by FLA at a pre-heat temperature of T = 473 K in Ar atmosphere and pulse energies between E = 40 and 90 J cm − ² for t = 20 ms. The SiO 2 capping layer was etched using a buffered HF (7:1) dip for 30 s. The polycrystalline Ge nanosheets were posteriorly contacted by Al pads fabricated by optical lithography, 125 nm Al sputter deposition, and lift-off techniques. A successive thermally induced exchange reaction by RTA at a temperature of T = 624 K in forming gas (10% H 2 , 90% N 2 ) atmosphere initiated the substitution of Ge by Al in accordance with the reactions involving single crystal Ge. [20,21] Facilitating this heterostructure formation scheme allows the integration of polycrystalline Al-Ge-Al heterostructures with tunable metallurgic channel lengths in a back-gated FET architecture using p-doped Si substrate as a common back-gate. Further, omegashaped Ti/Au TGs were fabricated atop Al-Ge-Al heterostructure nanosheets coated with 14 nm of Al 2 O 3 as gate insulator deposited by ALD, using a combination of EBL, Ti/Au evaporation (7 nm Ti, 100 nm Au), and lift-off techniques.
EDX and EBSD Measurements: To prevent drift due to charging effects, the samples had been coated with 2 nm of carbon prior to EDX and EBSD mapping. EDX and EBSD were performed in a Tescan MIRA SEM using a Digiview 5 camera from EDAX (UK), with beam conditions of 20 kV and 5 nA. A step size of 50 nm had been used for the mapping.
TEM Measurements: TEM lamella preparation was performed using a Tescan Lyra FIB/SEM. The TEM images were acquired using a Thermo Fisher Scientific Titan Themis 200 G3 outfitted with a SuperX detector used for the EDX maps.
µ-Raman Characterization: A confocal multi-functional microscope setup (Alpha300, WITec) equipped with a frequency doubled Nd:YAG laser emitting linearly polarized light at λ = 532 nm was used. For confocal µ-Raman measurements, a setup in backscattering geometry with a grating monochromator and a CCD camera (DV401-BV, Andor) was employed. An achromatic Nikon EPI EPlan 100× objective (NA = 0.9, WD = 0.23 mm), enabling a diffraction limited spot size of ≈720 nm was used.
Electrical Characterization: The electrical measurements were carried out at room temperature and ambient conditions using a combination of a semiconductor analyzer (HP 4156B) and a probe station. To minimize the influence of ambient light as well as electromagnetic fields, the probe station was placed in a shielded dark box. Temperature-dependent measurements (80-380 K) were performed in vacuum at a background pressure of ≈5 × 10 −6 mbar using a cryogenic probe station (LakeShore PS-100) and a semiconductor analyzer (Keysight B1500A).

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.