Designing wake-up free ferroelectric capacitors based on the HfO 2 /ZrO 2 superlattice structure

The wake-up phenomenon widely exists in hafnia-based ferroelectric capacitors, which causes device parameter variation over time. Crystallization at higher temperatures have been reported to be effective in eliminating wake-up, but high temperature may yield the monoclinic phase or generate high concentration oxygen vacancies. In this work, a unidirectional annealing method is proposed for the crystallization of Hf 0.5 Zr 0.5 O 2 (HZO) superlattice ferroelectrics, which involves heating from the Pt/ZrO 2 interface side. Nanoscale ZrO 2 is selected to resist the formation of monoclinic phase, and the chemically inert Pt electrode can avoid the continuous generation of oxygen vacancies during annealing. It is demonstrated that 600 o C annealing only leads to a moderate content of monoclinic phase in HZO, and the TiN/HZO/Pt capacitor exhibits wake-up free nature and a 2 P r value of 27.4 µC/cm 2 . On the other hand, heating from the TiN/HfO 2 side, or using 500 o C annealing temperature, both yield ferroelectric devices that require a wake-up process. The special configuration of Pt/ZrO 2 is verified by comparative studies with several other superlattice structures and HZO solid-state solutions. It is discovered that heating from the Pt


I. Introduction
The ferroelectricity observed in hafnia (HfO2)-based oxides, especially Hf0.5Zr0.5O23][4][5][6][7][8][9][10][11][12] In contrast to traditional ferroelectrics such as perovskite Pb(Zr,Ti)O3, SrBi2Ta2O9 and organic polyvinylidene fluoride polymers, a special wake-up phenomenon has been widely observed in hafniabased ferroelectric capacitors, which implies that the switchable polarization is subject to variation during the initial period of capacitor lifetime. [13]Although the spontaneous polarization is actually being enhanced during wake-up, [14] the variable device parameter can cause severe problems in applications.][17] In particular, a high crystallization temperature could effectively render wake-up-free ferroelectric capacitors based on HZO. [17]Therefore, raising the processing temperature is a potential solution to get rid of the wake-up phenomenon.
Nevertheless, using high crystallization temperature leads to other serious problems.
On the one hand, hafnia-ferroelectric capacitors usually involve TiN or TaN electrodes, which are oxygen scavenger materials at high temperature. [18]On the other hand, high temperature crystallization tends to generate the thermodynamically stable monoclinic (P21/c) phase (m-phase) for HfO2 or HZO, which are paraelectric. [16,19]The robust stability of monoclinic phase hinders its transformation into the ferroelectric orthorhombic Pca21 phase (o-phase).Hence, in most published works, the crystallization temperature was controlled at around 500 o C. [17,20,21] In this work, we attempt a special design for the ferroelectric layer that can avoid the above two problems, thus permitting a higher crystallization temperature.First of all, the concept of HfO2/ZrO2 superlattice enables crystallization from the ZrO2 side.This is possible when ZrO2 is adjacent to an inert electrode and the heat source is only from that electrode side during rapid thermal annealing (RTA).Standard RTA instruments typically possess heating modes from upper lamps, lower lamps and both.4] Hence, even high temperature RTA may not transform nanoscale ZrO2 into m-phase.
Secondly, an inert electrode like Pt can be selected in conjunction with the ZrO2 layer that is closest to the heat source, in order to suppress the generation of new oxygen vacancies during crystallization annealing.In our experiments, the as-designed samples have been shown to possess the desired properties.Experimental details and mechanism analysis are given in the following sections.

II. Wake-up Free Ferroelectric Capacitors through Design
Our prototype device structure is illustrated in Figure 1(a), with a TiN/HfO2-ZrO2 superlattice/Pt capacitor structure.The 12-nm HfO2/ZrO2 superlattice was grown on TiN through thermal atomic layer deposition (ALD).The 100 nm-thick Pt top electrode (TE) was deposited using DC sputtering.Detailed experimental parameters are specified in the Experimental section.The two interfaces formed by the ferroelectric layer with the TE and the bottom electrode (BE) therefore experienced quite different processes.The bottom interface went through a mild ALD process, but the top interface has experienced a high energy bombardment during sputtering.Such asymmetric treatment is quite common and recently it was reported that the abundant oxygen vacancies around the top interface may be related to the imprint phenomenon in HZOferroelectrics. [25]In our device, the impact of bombardment is only prominent in the topmost ZrO2 layer of ~2 nm thick.The underneath HfO2 layer is well maintained after TE sputtering, as evidenced from the scanning transmission electron microscopy (STEM) analysis in Figures 1(d)-1(e).When heating from the top (bottom) side, the local temperature changes from high (low) to low (high) when scanning from TE (Pt) to BE (TiN).The device consists of HfO2/ZrO2/HfO2/ZrO2/HfO2/ZrO2, each of ~2 nm thickness, as illustrated in Figure 1(d).The bottom and top layers are HfO2 and ZrO2, respectively.To understand the effect of different RTA processes on ferroelectric properties, a triangular wave voltage signal with 1 kHz frequency was applied to both samples.
Figure 2(a) demonstrates the pristine ferroelectric hysteresis loops, where that of Sample B is pinched.[28] Applying a triangular wave pulse signal 1000 times, the P-E curves become that shown in Figure 2(b).The 2Pr values are 27.4µC/cm 2 and 20.3µC/cm 2 for Sample T and Sample B, respectively, at 3V operation voltage.Wake-up-free characteristics have been revealed in Sample T only.The positive coercive field (Ec + ) of Sample T (~1.11MV/cm) is also slightly larger than its Ec -(-0.88MV/cm) as well as the Ec + of Sample B (~0.98 MV/cm), which is consistent with its enhanced spontaneous polarization (PS), and reflects certain internal bias field in Sample T. DC leakage test results show that the strong polarization in Sample T is achieved at a cost of stronger leakage current density (9.3 mA/cm 2 at 2.5 MV/cm), but the overall leakage deterioration of Sample T is not severe.Furthermore, to eliminate any non-intrinsic contribution to the polarization, the positive-up-negative-down (PUND) measurement was conducted, with a double triangular wave of 1 kHz (methodology explained in Supplementary Note S1).The double triangular wave consists of a positive switching pulse, a positive non-switching pulse, a negative switching pulse and a negative non-switching pulse.[31] The value of intrinsic Pr -is obtained by the same means. [32]The rectified values of 2Pr are 27.13 µC/cm 2 and 18.58 µC/cm 2 for Sample T and Sample B as illustrated in Figure 2(d), confirming the intrinsic ferroelectric property of both samples.
A non-centrosymmetric Pca21 orthorhombic phase (o-phase) has been widely accepted as the origin of ferroelectricity in hafnia-based dielectrics. [33,34] he impact of RTA scheme on the crystal structure of the dielectric is therefore our immediate concern.We further analyzed the crystallization of the HZO films with grazing incidence X-ray diffraction (GIXRD) characterization.As illustrated in Figure 3  The abundant existence of t-phase may explain the need of wake-up in Sample B and the possible antiferroelectric-like hysteresis loop at pristine.To further evaluate this point, we subsequently explored the distribution of the internal field of the samples.
The first-order reversal curves (FORCs) were measured to reveal the contribution of the internal field by switching density. [35,36] s shown in Figures 4(a)-4(b), the switching densities for Sample T at the first and the 1000 th cycles are very similar.
Nevertheless, two opposite internal biases appear in the pristine Sample B, located near -0.16MV/cm and 0.79 MV/cm, respectively.The existence of double biases is relevant to the pinched hysteresis loop and antiferroelectric-like characteristics before wakingup. [1]As expected, after 1000 cycles there are only positive internal bias field emerging in Sample B, in a similar situation as Sample T.  Based on the experimental measurements, we propose an explanation to the distinct properties between Sample T and Sample B. The location of heat source determines which side of the dielectric is first subject to crystallization.Moreover, the generation and movement of defects probably occur near the electrode that is close to the heat source.The starting point of the crystallization is important in that it can promote the emergence of similar phases in the rest part of the dielectric.It is supposed that the ZrO2 layer adjacent to the TE is populated with oxygen vacancies, due to the bombardment effect of sputtering.However, the Pt TE itself is chemically inert, therefore these oxygen vacancies have a physical rather than chemical origin.When heated from the top, the generation of new oxygen vacancies is unlikely, but the existing oxygen vacancies tend to diffuse toward the BE side.A vertical distribution of oxygen vacancies facilitates the creation of conductive paths, thus increasing the leakage current.However, a potential benefit lies in that the decrease of oxygen vacancy concentration near the TE, where crystallization first occurs, can suppress the formation of the t-phase. [37]It is well-known that the t-phase is the one among HfO2/ZrO2 polymorphs that can tolerate the most amount of oxygen vacancies. [24,38,39]nsequently, Sample T contains less t-phase, but more m-phase.On the contrary, the TiN BE may absorb oxygen atoms at high temperature, and in Sample B the crystallization near the BE is accompanied by the generation of more oxygen vacancies locally.The formation of t-phase is therefore reasonable, which, together with the high oxygen vacancy concentrations near both electrode interfaces, accounts for the initially pinched hysteresis loop and the existence of waking-up.On the other hand, the leakage current of Sample B is lower as there is less driving force to create conductive paths across the entire dielectric.

III. Comparative Study with other capacitor designs
To further evaluate our designing principle, i.e., high temperature annealing starting from the Pt/ZrO2 side, we carried out several comparative studies.First of all, we annealed the sample at 500 o C using top heating mode, leading to the so-called Sample TL (L for relatively low temperature), which differs from Sample T only in terms of the annealing temperature.The initial P-E loop of Sample TL is pinched as shown in Supplementary Note S2, and it shows the wake-up behavior as the hysteresis gradually opens.This phenomenon is consistent with the previous reports that high annealing temperature can avoid waking-up. [17]Subsequently, we prepared three more groups of samples as demonstrated in   The high 600 o C annealing temperature is supposed to be a key factor for the memristor formation.Hence, we further annealed samples of the same compositions as C1 and C2, using 500 o C top-heating (named Sample C1L and Sample C2L, respectively).Their leakage currents are much improved, but the initial P-E loops are strongly pinched (see  These experimental findings in general indicate that high temperature annealing can eliminate the wake-up process, provided that severe oxygen vacancy generation is avoided and the dielectric is not fully converted to the m-phase.We note that unidirectional heating during the RTA, i.e., heating only with the top lamps, is at the heart of this technique.The unidirectional RTA is not only applicable in superlattice HZO ferroelectrics, but may be helpful in other asymmetric ferroelectric capacitor designs.It is therefore recommended to optimize the RTA process for the crystallization of other HZO-ferroelectrics in the future.

IV. Conclusions
In conclusion, we have designed a special ferroelectric capacitor based on the HfO2/ZrO2 superlattices, which could endure high annealing temperature around 600 o C and is free of waking-up.The bottom and top electrodes are TiN and Pt, respectively.
What is special lies in that the dielectric layer adjacent to the Pt top electrode should be ZrO2, and the rapid thermal annealing is carried out only using top lamps.The significant role of ZrO2 close to the top electrode is two folds.On the one hand, it is not easily transformed to the monoclinic phase totally, even at high temperatures.On the other hand, oxygen vacancy clustering is much less probable in ZrO2 than in HfO2, thus avoiding the dielectric breakdown phenomenon during high temperature annealing.The Pt top electrode is preferred for its inert nature, which tends not to generate more oxygen vacancies at high temperatures.The sample annealed at 600 o C shows a typical 2Pr value of 27.4 µC/cm 2 , and is free of waking-up.In contrast, samples annealed at 500 o C required a wake-up process.And when the Pt/HfO2 contact is designed for the top electrode interface, the device becomes a memristor after 600 o C annealing, which is related to the strong tendency of oxygen vacancy clustering and metal phase segregation inside HfO2.The designing rule of this work as well as the high temperature annealing process for wake-up removal can be useful for the material and device design of hafnia-based ferroelectrics.

Experimental
The TiN/HfO2-ZrO2 superlattice/Pt device is fabricated on an n-Si/SiO2 substrate.The bottom electrode TiN was deposited by magnetron sputtering.Subsequently, the 12nm-

Figure 1 .
Figure 1.(a) A schematic of the capacitor fabrication-RTA-measurement process, illustrating the capacitor structure; (b) Temperature profile of the top heating mode in RTA; (c) Temperature profile of the bottom heating mode in RTA; (d) Cross-section STEM-HAADF (high-angle annular dark-field) image of the TiN/HZO/Pt ferroelectric capacitor (Sample T) after annealing; (e) A reconstructed image obtained by inverse Fourier transform from the red square area of (d).

Figure 2 .
Figure 2. (a) Ferroelectric P-E hysteresis loops obtained from pristine Sample T and Sample B; (b) Ferroelectric hysteresis loops measured after the wake-up process; (c) DC leakage currents of the two samples; (d) The PUND test results.
(a), the mixture of o(111) and t(001) peaks are located around 30.5 o .The relative area ratios of the o-phase, tphase and m-phase at 29 o ~33 o are further illustrated in Figure 3(b)-3(c).The most obvious feature is that the areal intensity ratio, o-phase to t-phase, greatly increases from 1.19 as in Sample B to 6.00 as in Sample T (Table I).Moreover, the percentage of m-phase is enhanced in Sample T compared with Sample B. An additional m(1 ̅ 11) peak at 28.5 o only emerges in Sample T. Hence, the major discrepancy of Sample T and Sample B lies in that the former prefers the m-phase together with the o-phase while the latter contains a substantial amount of t-phase.

Figure 3 .
Figure 3. GIXRD characterization of the annealed ferroelectric capacitor samples.(a) GIXRD scanning results from 25 o to 45 o for Sample T and Sample B; (b) Phasedecomposed patterns of Sample T; (c) Phase-decomposed patterns of Sample B.

Figure 4 .
Figure 4. Distribution of the internal fields revealed by switching density in the FORCs method.(a) Sample T in its pristine state; (b) Sample T after 1000 polarization cycles; (c) Sample B in its pristine state; (d) Sample B after 1000 polarization cycles.

Figure 5 .
The first comparative group (named Sample C1) has a reversed sequence of HfO2/ZrO2 growth, now with TiN/ZrO2 BE interface and Pt/HfO2 TE interface.Sample C2/C3 has HfO2/ZrO2 in contact with both electrodes (Figure 5(c)-5(d)).The chemical stoichiometry is still kept as Hf0.5Zr0.5O2since a corresponding HfO2/ZrO2 layer at the center of the dielectric possesses a reduced thickness of 1 nm for Sample C2/C3.The compositions of these comparative samples are such chosen as to examine whether heating from a Pt/HfO2 interface leads to m-HfO2-dominated phases with potentially low spontaneous polarization.All crystallization annealing steps were performed using the top heating mode at 600 o C in Samples C1-C3.As shown in Figure 5(e), only Sample C3 demonstrates a low leakage current as Sample T, but Samples C1 and C2 suffer from giant leakage currents, demonstrating memristive I-V behaviors.Figure 5(e) shows that the device resistance level can turn from a low resistance state to a high resistance state when a negative voltage is present (RESET), typical of a memristor behavior.The conductive behaviors of Samples C1 and C2 have covered up their possible ferroelectric properties.On the other hand, Sample C3 exhibits a similar ferroelectric hysteresis loop as Sample T (Figure 5(f)), though the remnant polarization values are slightly inferior to Sample T.

Figure 5 .
Figure 5.Comparison of the superlattice structures between (a) Sample T; (b) Sample C1; (c) Sample C2; and (d) Sample C3.(e) DC leakage current test results for all four samples; (f) Ferroelectric hysteresis loops of Sample T and Sample C3.

Figure 6 .
Figure 6.(a) DC leakage currents of Sample C1L and Sample C2L; (b) Ferroelectric hysteresis loops of Sample C1L and Sample C2L in their pristine states; (c) Ferroelectric hysteresis loops of Sample C1L and Sample C2L after 1000 polarization cycles.

Figure 7 .
Figure 7. (a) Schematic structure of Sample C4; (b) Schematic structure of Sample C5; (c) I-V test results of both samples; (d) P-E test results of both samples.

Table S1 .
Materials under investigation, the corresponding calculation settings, and

Table S2 .
Energetics of various sub-oxide decomposition reactions.Here f.u.represents a formula unit.