Low‐Power Logic‐in‐Memory Complementary Inverter Based on p‐WSe2 and n‐WS2

Transition metal dichalcogenides have been considered as candidate materials to construct logic‐in‐memory devices for realizing non‐von‐Neumann architecture. Thus, reducing the power consumption is extremely critical for their applications in big data and artificial intelligence. Here, a low‐power logic‐in‐memory device is demonstrated by constructing complementary inverter with p‐WSe2 and n‐WS2 transistors. By engineering the interface states between WSe2 (WS2) and substrate artificially, non‐volatile memory with resistance ratio of 104 and 103 after 500 s are achieved in individual WSe2 and WS2 transistors, respectively. Furthermore, a complementary inverter with a retention time longer than 500 s is realized by connecting p‐WSe2 and n‐WS2 transistors. More importantly, the static operating source‐drain current Ids of this inverter is around 0.5/0.1 nA at low/high resistance states with source‐drain voltage Vds = 5 V, and the hysteresis window is located around 0 V, both of which can reduce the energy consumption dramatically and leads to the low operation power. This work provides a convenient strategy to build a non‐von‐Neumann device toward post‐Moore information processing technology.

Transition metal dichalcogenides have been considered as candidate materials to construct logic-in-memory devices for realizing non-von-Neumann architecture. Thus, reducing the power consumption is extremely critical for their applications in big data and artificial intelligence. Here, a low-power logic-inmemory device is demonstrated by constructing complementary inverter with p-WSe 2 and n-WS 2 transistors. By engineering the interface states between WSe 2 (WS 2 ) and substrate artificially, non-volatile memory with resistance ratio of 10 4 and 10 3 after 500 s are achieved in individual WSe 2 and WS 2 transistors, respectively. Furthermore, a complementary inverter with a retention time longer than 500 s is realized by connecting p-WSe 2 and n-WS 2 transistors. More importantly, the static operating source-drain current I ds of this inverter is around 0.5/0.1 nA at low/high resistance states with source-drain voltage V ds = 5 V, and the hysteresis window is located around 0 V, both of which can reduce the energy consumption dramatically and leads to the low operation power. This work provides a convenient strategy to build a non-von-Neumann device toward post-Moore information processing technology.

Introduction
Over the past few decades, the data size and computation capability have experienced explosive growth. [1] The evolution of integration density and computation capacity could be described by Moore's law. However, the Moore's law cannot be continuously valid if the transistors are further scaled down to "quantum regime." [2] The fabrication technique limit, tunneling carriers and severe heating issue render that the size transistor, which is attributed to the charge traps at the interface. An inverter is realized by connecting WSe 2 and WS 2 transistor with complementary memory effect. Because WSe 2 and WS 2 are always operating at opposite resistance states, the static current of the inverter is at the order of nanoampere. In addition, the hysteresis window is located at 0 V, reducing the power consumption dramatically. Figure 1a shows the schematic illustration of WSe 2 /WS 2 inverter on Si substrate with a 300 nm SiO 2 serving as the dielectric layer. Silicon wafers were rinsed with isopropanol and deionized water, and subsequently cleaned by oxygen plasma. The oxygen plasma treatment can induce trap states at the interface between WSe 2 (WS 2 ) and SiO 2 , which is critical to realize the hysteresis as reported in our previous work. [15] WSe 2 , WS 2 layers and electrodes were fabricated by dry transfer method (see details in Section 4).

Results and Discussion
We firstly investigate the electric properties of individual WSe 2 and WS 2 transistors. The output curves of WSe 2 and WS 2 are shown in Figure S1, Supporting Information. The symmetrical output curves in liner coordinates reveal the excellent contact between Au and WSe 2 (WS 2 ). Figure 1b,c are the transfer characteristics of individual WSe 2 and WS 2 transistors under different V ds , respectively. I ds continuously decreases (increases) for WSe 2 (WS 2 ) with the increased gate voltage V g , suggesting WSe 2 (WS 2 ) is p-type (n-type) semiconductor. The opposite polarities of WSe 2 and WS 2 meet the basic requirement to build a complementary inverter. Figure 2a,b are the transfer curves of the WSe 2 and WS 2 in logarithmic coordinates with V ds = 3 V. The black and red arrows represent forward and backward V g sweep directions. Both curves have obvious hysteresis caused by interface states between WSe 2 (WS 2 ) and SiO 2 and the mechanism will be discussed below. [15,16] Consequently, a memory can be achieved by using the hysteresis. The hysteresis window of WSe 2 and WS 2 are 0-30 V and −30-0 V, respectively. For V g = 0 V in forward direction, WSe 2 is in high resistance cutoff state, while WS 2 is in low resistance conduction state. On the contrary, resistance states of WSe 2 and WS 2 are reversed in backward direction. It is worth to note that HRS and LRS always appear simultaneously in this inverter regardless of sweep direction, which is the main character of the complementary memory devices.
Furthermore, endurance and retention performance were investigated. Figure 2c,d (upper panel is source-drain current and lower panel is applied gate pulse) are endurance characteristic within 10 cycles by applying V g = ±50 V pulses. The HRS and LRS current remain unchanged within 10 cycles, indicating the reliability of WSe 2 and WS 2 transistors. Figure 2e,f show the retention characteristics of the HRS and LRS for WSe 2 and WS 2 transistors, respectively. WSe 2 transistor exhibits HRS/ LRS ratio of 10 4 after 500 s, and WS 2 transistor also has a HRS/ LRS ratio of 10 3 after 500 s. It can be clearly seen that WSe 2 and WS 2 have opposite resistance states under the same pulse. Therefore, the output current is expected to be small if those two transistors are connected to form an inverter.  We then investigate the mechanism of resistance states evolution. The on (LRS) and off (HRS) states of WSe 2 and WS 2 under ±50 V pulses are schematically shown in Figure 3a.
According to previous reports, [17] the oxygen plasma treatment of SiO 2 substrate would create hydroxyl-group (OH) at the surface that would attract H 2 O and O 2 . Electron trapping and de-trapping within the interface states take place under +50 and −50 V gate pulses respectively, which corresponds to H 2 O/O 2 redox as following equation: [17c] ( ) When a positive V g is applied in Figure 3b, electrons are trapped by interface states. The oxidation reaction takes place and electrons in WSe 2 /WS 2 transfer from H 2 O/O 2 to form OH − . As a results, hole concentration of p-type WSe 2 increases, while electrons concentration of n-type WS 2 decreases as illustrated in top panel in Figure 3a. Therefore, WSe 2 transits to LRS and WS 2 changes to HRS. The reversed reduction process takes place under a negative V g as shown in Figure 3c. The electrons de-trapping process will render WSe 2 to HRS and WS 2 to LRS. To understand how the carrier concentration varies with V g during electrons trapping and de-trapping process, we specifically measured the transfer curve of WSe 2 transistor when V g is changed gradually ( Figure S2, Supporting Information). When the V g decrease gradually from +50 V with a triangle pulse, I ds declines first and then increase ( Figure S2b,c, Supporting Information), which is corresponding to the electrons depletion and holes accumulation process ( Figure S2d, Supporting Information). The memory characteristics are related to the hysteresis opening size of the transfer curve. To investigate the mechanism of hysteresis, WSe 2 and WS 2 transistor are prepared based on different interface states, which show marked difference in hysteresis ( Figure S3, Supporting Information). The charge transfer occurs in interface states during the applying bias ( Figure S3a, Supporting Information), which causes the hysteresis of the transfer curve of WSe 2 and WS 2 transistors ( Figure S3c,e, Supporting Information). In contrast, an inhibition of interfacial charge transfer is observed once the silicon wafer is covered with h-BN layer ( Figure S3b, Supporting Information). Accordingly, the hysteresis of WSe 2 and WS 2 transistors are almost negligible ( Figure S3d,f, Supporting Information). At the same time, the transfer curves of WSe 2 transistor indicate different hysteresis opening sizes by varying the time of oxygen plasma treatment of silicon wafers ( Figure S4, Supporting Information). As the time of oxygen plasma processing the silicon wafer increases, the hysteresis window increases, which demonstrates the correlation between hysteresis and oxygen plasma treatment of silicon wafers.
An inverter was experimentally constructed as shown in Figure 4a. Figure 4b is the corresponding optical image of asfabricated device. After applying ±50 V pulses as input signal (V in ), the output signal (V out ) switches between high-level (≈5 V) and low-level (≈0.6 V) voltage in Figure 4c. The output signal almost remains unchanged after repeating tens of cycles, suggesting the reliability of the logic and memory device. The operating current I ds is presented in Figure S5, Supporting Information. Retention and endurance characteristic are shown in Figure 4d,e. The output voltage changes with V ds and remains constant for 500 s and remaining unchanged for 100 cycles as well, which further evidence the excellent performance of inverter based memory. More importantly, the static operating current I ds is around 0.5/0.1 nA at LRS/HRSs with V ds = 5 V as shown in Figure S6  . In particular, the hysteresis window is located at V in = 0 V, which is another main character to further reduce power consumption of the memory devices. It is worth noting that the high-level output voltage can remain same as V ds but the low-level output is not 0 V which is due to that WSe 2 and WS 2 are bipolar materials. The gain and power consumption of the inverter are shown in Figure S7a,b, Supporting Information, respectively. Since WSe 2 and WS 2 transistors are bipolar, there is a large current at the high and low levels of the inverter output. And high-level output noise margins are 35 and 31.5 V, respectively. A comparison of these parameters with other reported work is shown in Table S1, Supporting Information.

Conclusion
We demonstrated a complementary inverter with logic and memory function by integrating p-WSe 2 and n-WS 2 transistors together to break the von Neumann architecture. The memory function originates from the artificial engineering of the interface states. Because WSe 2 and WS 2 have opposite polarity, there always exist a high-resistance state and low-resistance state regardless of gate voltage. Consequently, the overall current can be reduced dramatically when they form an inverter. The static operating current I ds of the inverter is at the order of nanoampere and the hysteresis window is located at V in = 0 V, both of which can reduce the power consumption. Our work demonstrates a convenient and effective strategy to design energy efficient logic and memory device with non von Neumann architecture. Considering the fact that the atomic thickness of TMDs materials also can increase the integration intensity, this kind of complementary inverter can be promising in the post-Moore information processing technology.

Experimental Section
Device Fabrication: WSe 2 and WS 2 thin flakes (10-40 nm) were obtained by mechanical exfoliation from bulk crystals and then transferred to the plasma cleaned silicon wafer by a dry transfer method. The thermal evaporation Au electrodes were peeled onto a polydimethylsiloxane and then transferred onto WSe 2 and WS 2 as the source drain electrodes. Finally, the device was annealed at 300 °C under Ar 2 atmosphere in a tube furnace with flow rate of 100 sccm and pressure of 1 Torr (Lindberg/ Blue MTF55035KC-1).
Electrical Characterization: The electrical measurements were performed in a probe station (Lakeshore, PS100). Source/measurement unit (Keysight B2902A) was used to apply source-drain voltage and input signal. The nanovoltmeter (keithley 2182A) was used to measure the output signal. All measurements were conducted under vacuum of 10 −4 Torr at room temperature.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.