Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double‐Gated Feedback Field‐Effect Transistors

In this study, the logic‐in‐memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double‐gated feedback field‐effect transistors. The component transistors reconfigure their operation modes into n‐ or p‐channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on‐current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero‐bias condition. This study demonstrates that the ternary logic gates are promising candidates for next‐generation low‐power computing systems.


Logic-in-Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double-Gated Feedback Field-Effect Transistors
Jaemin Son, Yunwoo Shin, Kyoungah Cho, and Sangsig Kim* DOI: 10.1002/aelm.202201134 current in multivalued states is one of the crucial issues affecting excessive power consumption in MVL gates, which remains a challenge.
Logic-in-memory (LIM) computing is another concept that has been considered for overcoming the power consumption and processing delay of current electronic systems. [17,18] The computing and memory units are merged in an LIM scheme, thereby drastically reducing the power consumption and delay of data transportation in the bus lines. Hence, the power consumption and circuit performance can be further improved by combining MVL and LIM computing systems. To operate with MVL and LIM functions simultaneously, an element device should possess both switching and memory characteristics. Given this condition, feedback field-effect transistors (FBFETs) have attracted considerable attention for use as MVL and LIM devices owing to their switchable-memory operation. [19][20][21] FBFETs have demonstrated extremely low subthreshold swings (SSs), high speeds, high on/off current ratios, and stable memory operations based on a positive feedback mechanism. [22,23] These features are advantageous for designing low-power, high-performance MVL and LIM computing systems.
In this study, we propose ternary NAND (TNAND) and ternary NOR (TNOR) logic gates consisting of double-gated (DG) FBFETs, which are capable of performing both MVL and LIM operations in a CMOS logic scheme. The TNAND and TNOR logic gates exhibit three distinct and stable logic states, which are maintained under zero-bias conditions for several tens to hundreds of seconds. Figure 1 shows schematic illustrations of the basic structure, corresponding energy band diagram, and optical images of a DG FBFET. The basic building block of the DG FBFET is a p + -i-n + diode with a double-top-gate structure. On the top of the 7-µm long intrinsic channel region, two 3-µm wide polysilicon gates are arranged side-by-side. The n-type doped polysilicon gate located near the p + drain region is named Gate1, and the p-type doped polysilicon gate located near the n + source region is named Gate2. The intrinsic channel region is electrostatically doped by the work functions of two heavily doped polysilicon gates; the n-doped Gate1 creates n-type electrostatic doping (n*), In this study, the logic-in-memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double-gated feedback field-effect transistors. The component transistors reconfigure their operation modes into n-or p-channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on-current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero-bias condition. This study demonstrates that the ternary logic gates are promising candidates for next-generation low-power computing systems.

Introduction
Multivalued logic (MVL) systems utilizing more than two logical states have been extensively studied to satisfy the exponential increase in storage requirements and data processing. [1][2][3] The MVL system is the simplest way to overcome long signal propagation delay and power density limitations of complementary metal-oxide-semiconductor (CMOS) binary logic systems by reducing the number of devices and interconnect lines. [4,5] Compared to binary logic systems, the use of ternary and quaternary logic systems can substantially reduce the system cost and complexity by 63.1% and 50%, respectively. [6] This indicates that the implementation of beyond-binary logic systems provides significant potential for next-generation computing systems. In recent years, MVL concepts have been widely researched in various devices, including ternary CMOS devices, [7][8][9] 2D materials, [10][11][12] carbon nanotube field-effect transistors, [13,14] and organic semiconductors, [15,16] However, leakage www.advelectronicmat.de and p-doped Gate2 creates p-type electrostatic doping (p*) in the channel region. [24] Accordingly, the DG FBFET forms a p +n*-p*-n + energy band structure with three potential barriers and two potential wells (Figure 1a). This p + -n*-p*-n + energy band structure allows the DG FBFET to operate with a positive feedback mechanism, which is a result of the mutual interaction between charge carriers and potential barriers. In the initial state, the drain-side and source-side potential barrier heights are sufficiently high to block carrier injection. However, when a positive Gate1 voltage (V G1 ) or a negative Gate2 voltage (V G2 ) is applied, a portion of the charge carriers is injected and accumulates in the potential wells in the channel. The accumulation of charge carriers then reduces the potential barrier heights and leads to more charge carriers injecting and accumulating in the potential wells in the channel. This repetition of charge carrier injection and accumulation is regarded as a positive feedback loop that sharply turns on the device in a very short time.
Meanwhile, the DG FBFET can operate in the n-or p-channel modes by controlling the electrostatic doping of the two gates. The circuit symbols of the n-and p-channel modes are depicted in Figure 2a. The two operation modes can be converted simply by adjusting the gate biases. To set the n-channel mode, Gate1 is electrically grounded and Gate2 voltage (V G2 ) is varied. In this mode, V G2 can control the injection of electrons from the source region, which allows the majority carriers to generate the positive feedback loop. Similarly, the p-channel mode can be set by controlling V G1 and grounding Gate2. In the p-channel mode, holes coming from the drain region become the majority carriers that generate the positive feedback loop. Figure 2b shows the representative transfer characteristics of the n-channel mode at a source voltage (V S ) of −1.2 V. As V G2 varies from −2.0 to 2.0 V, the n-channel mode shows a dramatic increase in drain current (I D ), called the latch-up phenomenon. However, as V G2 varies reversely from 2.0 to −2.0 V, the device maintains an onstate owing to the positive feedback loop in the channel region. On the other hand, the device is turned off when the positive feedback loop is eliminated by reducing the supply voltage (V D for the p-channel mode and V S for the n-channel mode). The reduction of the supply voltage regenerates the potential barriers and blocks the injection of charge carriers, and thereby the device cannot maintain the positive feedback loop no longer and consequently it is turned off ( Figure S1, Supporting Information). The p-channel mode at a drain voltage (V D ) of 1.2 V exhibits highly symmetrical operation with the n-channel mode, as shown in Figure 2c. Both the n-and p-channel modes exhibit excellent switching characteristics, including extremely low SSs (<1 mV dec −1 ), low off-current (10 −13 A), and high on/off current ratio (10 7 ). Moreover, the observed hysteresis behavior reveals that the device can operate with a switchable-memory function for ternary LIM computing systems.
For representing our ternary number system, we use a symmetrical balanced ternary logic, which is represented by {"−1," "0," "1"}. The balanced ternary number system has considerable computational advantages in terms of complexity and energy efficiency compared with unbalanced ternary number system {"0," "1," "2"} that requires a separate sign bit to represent negative number. [25,26] Moreover, this system can implement "carryfree" ternary adder and multiplexer, which is highly effective for arithmetic operations. [27] The logic "−1" (logic "1") of the ternary logic system is defined as the V G region where the n-channel mode (the p-channel mode) turns on and p-channel mode (the n-channel mode) turns off. A third intermediate logic level (logic "0") arises from the V G region, where both the n-and p-channel modes are turned on (V G1 = V G2 = 0 V). Herein, the on-currents of the n-and p-channel modes were extracted from the transfer curves at V G1 = V G2 = 0 V (Figures 2b,c). The truth tables of the two-input TNAND and TNOR logic gates that utilize balanced ternary logic are presented in Table 1. The TNAND and TNOR logic gates are respectively defined as min , TNAND and TNOR logic gates are known as universal logic gates that can implement any Boolean logic function. Therefore, we examined the TNAND and TNOR logic gates to investigate the applicability of ternary LIM operations in current logic and arithmetic systems. Figure 3a shows an optical image and circuit diagram of the TNAND logic gate consisting of four DG FBFETs. Similar to the CMOS binary NAND logic gate, two parallel DG FBFETs are set to p-channel mode, and two series DG FBFETs are set to n-channel mode. The drain electrodes of the p-channel modes and source electrodes of the n-channel modes are connected to the power supply voltages V DD and V SS , respectively. The input voltages V IN1 and V IN2 the logics "1," "0," and "−1," respectively. The TNAND logic gate exhibits three stable logic states owing to the identical on-state channel resistance ratio between the n-and p-channel modes. Furthermore, sharp voltage transitions are observed in the TNAND logic gate owing to the positive feedback mechanism of the DG FBFET. An additional memory operation can be realized in our logic gates using the switchable-memory function of the DG FBFET. The DG FBFET has quasi-nonvolatile memory characteristics that retain accumulated charge carriers for several tens to hundreds of seconds. [23] The quasi-nonvolatile memory characteristics of the DG FBFET are superior to those of other charge-based memory transistors, [28,29] and our device does not require any bias to retain stored charge carriers. This is the key characteristic for realizing the LIM operation in logic gates. Figure 3c shows the timing diagram of the TNAND LIM operation. A sequence of input logic {V IN1 , V IN2 } = {"−1," "−1"}, {"−1," "0"}, {"−1," "1"}, {"0," "−1"}, {"0," "0"}, {"0," "1"}, {"1," "−1"}, {"1," "0"}, and {"1," "1"} pulses are performed with a V DD of 1.2 V and a V SS of −2.0 V to verify the ternary logic operation. V IN values of −2.0, 0, and 2.0 V are used for the input logic "−1," "0," and "1" pulses, respectively. During ternary logic operation, the V OUT exhibits three logic levels (logics "−1," "0," and "1") depending on the input logic pulses, which are exactly matched with the TNAND truth table. The voltage spike for the logic "0" pulse results from the voltage division between the resistances of the pull-up and pull-down networks.  Inputs Outputs Adv. Electron. Mater. 2023, 9,2201134 For the logic "0" pulse, the resistance of the pull-up network is lower than that of the pull-down network due to the parallel connection of the component devices, whereas the pull-down network is configured with a series connection. Thus, V OUT becomes ≈0.13 V because of the voltage division. For the hold operation, V OUT is determined by charge carriers stored in the n-and p-channel modes because the supply voltages are not applied. In the TNAND logic gate, the pull-up and pull-down networks exhibit 0.6 and −0.6 V, respectively, when they are in the on-state. Accordingly, the V OUT becomes ≈0 V in the hold operation because the pull-up and pull-down networks both are turned on in the logic "0." After each input logic pulse, hold operations are performed to memorize the output logic states. Although all the biases are set to 0 V during the hold operation, the TNAND logic gate maintains the output logic states owing to the accumulated charge carriers in each device. This indicates that our logic gate not only exhibits zero-static power consumption but also reduces the dynamic power consumption by using shorter logic pulses. Next, TNOR logic gate, the other universal logic gate, was fabricated and its ternary LIM operation was examined. Figure 4a shows an optical image and circuit diagram of the

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TNOR logic gate consisting of four DG FBFETs. In the TNOR logic gate, two series DG FBFETs are set to p-channel modes, and two parallel DG FBFETs are set to n-channel modes. The connection method of the power supply voltages (V DD and V SS ) and input voltages (V IN1 and V IN2 ) in the TNOR logic gate are the same as those in the TNAND logic gate. Figure 4b shows VTCs of the TNOR logic gate at a V DD of 2.0 V and a V SS of −1.2 V. As the values of V IN1 and V IN2 are varied in the range −2.0 to 2.0 V, the TNOR logic gate exhibits distinct and stable output logic states of "−1," "0," and "1". Both TNAND and TNOR logic gates exhibit the difference between V IN and V OUT . The voltage drop of V OUT results in the difference between V IN and V OUT ; the voltage drop of V OUT occurs since the DG FBFETs storage charge carriers in the channel regions with capacitance components. Hence, in order to compensate for the voltage drop, an amplifier is needed in the peripheral circuit. Figure 4c shows the timing diagram of the TNOR LIM operation. During a sequence of the ternary input logic pulses, the output logic levels of the TNOR logic gate exactly match the TNOR truth table. Similar to the TNAND logic gate, the TNOR logic gate also maintains the V OUT levels in each hold operation. Furthermore, ternary logic gates can also be used for binary LIM by simply using two logics "−1" and "1" (Figure S2, Supporting Information). Thus, TNAND and TNOR logic gates are expected to show high applicability in current logic applications owing to their ternary-binary hybrid LIM operations.
To verify the stability of the ternary LIM operation, we analyzed the logic retention characteristics of the ternary logic gates (Figures 5 and 6). The input logic {V IN1 , V IN2 } = {"−1," "−1"}, {"0," "0"}, and {"1," "1"} pulses are used for an estimation of the retention times of the output logics "1," "0," and "−1," respectively. After applying the input logic pulses for 1 ms, all the external biases are set to 0 V for 100 s to confirm the logic retention times. We denote the logic retention time as the time at which the initial V OUT reaches 37%. Figure 5a-c shows the logic retention characteristics of the TNAND logic gate for the output logics "1," "0," and "−1," respectively. The output logic levels gradually degraded toward 0 V as the devices lost accumulated charge carriers. The logic retention times for the output logics "1" and "−1" of the TNAND logic gate are estimated to be 19 and 30 s, respectively. The output logic "0" shows an almost infinite logic retention time because its initial V OUT is 0 V. However, the TNOR logic gate exhibits logic retention times of more than 100 s for all output logics (Figure  6a-c). During the holding time of 100 s, the output logics "1" and "−1" of the TNOR logic gate are degraded by only 27.47% and 9.19%, respectively. The difference between the retention times for the output logics "1" and "−1" of the TNAND logic gate originates from the difference between the charge storage abilities for the p-and n-channel modes. The charge storage ability is directly related with the carrier lifetime being defined as the average time of the minority carrier recombination. For the hold operation of the output logic "1", the p-channel modes storage charge carriers and the n-channel modes are turned off. In contrast, for the hold operation of the output logic "−1", the n-channel modes storage charge carriers and the p-channel modes are turned off. Thus, the logic retention times of the output logics "1" and "−1" depend on the charge storage abilities of the p-and n-channel modes, respectively. The charge storage ability of the n-channel mode is better than that of the p-channel mode because the hole recombination is much slower than the electron recombination. [30] Hence, the TNAND logic gate well maintain the output logic "1" rather than the output logic "−1" during the hold operation. In addition, the Figure 5. Logic retention characteristics of TNAND logic gate for a) logic "1," b) logic "0," and c) logic "−1." www.advelectronicmat.de difference between the retention times for the TNAND and TNOR logic gates results from the difference between the circuit configurations; the serial connection is more advantageous than parallel connection in preventing leakage current. Hence, the TNOR logic gate that minimizes the leakage path of the p-channel modes has a longer logic retention time than the TNAND logic gate.
Nevertheless, ternary logic gates exhibit logic retention times in the range of tens to hundreds of seconds, which is sufficient for ternary LIM operations. Moreover, the logic retention times of the output logics can be extended by applying the supply voltages during the hold operation. The retention time is theoretically infinite when the external biases are applied because the positive feedback loop in the component devices remains unless the external biases are removed.
In Table 2, the DG FBFET-based logic gates are compared with those of the MVL gates reported by other research groups. In terms of operating window that is deeply concerned with the damage of components in the MVL gates, our logic gates are superior to others with a wide operating window being responsible for flow of large current during logic cascading. Moreover, most MVL gates consume relatively high energy during the logic operation due to leakage current in multivalued states. Most previous MVL systems are based on Von Neumann architecture in which processor die dissipates over 50% of energy in caches and register files. Furthermore, the energy cost of the DRAM access is estimated to be 1.3-2.6 nJ, which is hundred times larger than cache access or functional operation (10 pJ). [36] In this study, the DG FBFET-based logic gates are expected to remove the necessity of the energy required to transport data  between computing and memory units owing to the LIM operation and consequently reduce the overall power consumption of the system. Furthermore, switching reliability is another crucial problem for multivalued devices that should be verified for logic and arithmetic operations. For example, tunneling-based multivalued devices, including ternary CMOS, negative differential resistance (NDR) devices, negative transconductance transistors, and quantum-dot-gated transistors, can generate a large leakage current and have temperature limitations because of their operating mechanism. [37] Resistive-based multivalued devices also suffer from device instabilities, such as large cellto-cell variations, low endurance, and low on/off ratio between multivalued resistive states. [38,39] In contrast, FBFETs that operate with a positive feedback mechanism have been verified for their superior operation and environmental stability that can compete with current CMOS technologies. [23,[40][41][42] These promising results indicate that the ternary logic gates have powerful advantages for stable and low-power future electronics. The DG FBFET-based ternary logic gates are desirable for data-intensive applications such as artificial intelligence, Internet of Things, etc. Their MVL and LIM operations can reduce the amount of the data access and system complexity of these applications.

Conclusion
We experimentally demonstrated the ternary LIM operation of the TNAND and TNOR universal gates using DG FBFETs. The DG FBFET exhibited highly symmetrical characteristics between the two operation modes (n-and p-channel modes) with an identical on-current ratio of 1.03. As a result of the positive feedback mechanism, three distinct and stable logic states "−1," "0," and "1" were successfully obtained from the ternary logic gates. Ternary logic gates maintained the output logic states under zero-bias condition for several tens to hundreds of seconds, and these operations are highly appealing for nextgeneration low-power logic applications.

Experimental Section
DG FBFETs were fabricated using a fully CMOS-compatible top-down process on a p-type silicon-on-insulator wafer. 100-nm thick silicon active layers were patterned using photolithography and anisotropic dry etching processes. Subsequently, ≈23-nm thick silicon dioxide gate dielectric layers were grown through thermal oxidation process at 850 °C. Next, two 3-µm wide polysilicon gates were formed side-by-side on top of the channel regions through low-temperature chemical vapor deposition (LPCVD) and photolithography. The separation between the two gates was 1-µm. The source regions and drain-side polysilicon gates were heavily doped with P + ions at a dose of 3×10 15 cm −2 and ion energy of 50 keV. The drain regions and source-side polysilicon gates were heavily doped with BF 2 + ions at a dose of 3×10 15 cm −2 and ion energy of 30 keV. The wafer was then annealed at 1000 °C for 30 min in ambient nitrogen and at 1050 °C for 30 s via rapid thermal annealing to eliminate defects and activate the implanted dopants. After interlayer dielectric formation was executed using LPCVD-based tetraethyl orthosilicate, Ti/TiN/Al/TiN metal stacks were deposited for the drain, source, and gate electrodes by sputtering and photolithography. Finally, forming gas annealing was performed at 450 °C for 30 min. The electrical properties were measured at 297 K using an Agilent HP4155C semiconductor parameter analyzer and Keithley 2636 B source meter.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.