Heterosynaptic Plasticity and Neuromorphic Boolean Logic Enabled by Ferroelectric Polarization Modulated Schottky Diodes

Neuromorphic computing employs a great number of artificial synapses which transfer information between neurons. Conventional two‐ or three‐terminal artificial synapses with homosynaptic plasticity suffer from a positive feedback loop problem. Synapses with heterosynaptic plasticity are thus required to perform learning, processing and modulating simultaneously. Here, complementary metal‐oxide‐semiconductor compatible artificial synapses based on ferroelectric polarization modulated Schottky diodes (FEMOD) on silicon, which enables heterosynaptic plasticity with multi‐functionalities, high endurance, low power consumption, and high speed, are presented. High accuracy is obtained in the supervised learning simulation of artificial neural networks due to the large number of conductance states, good linearity, and small variations of FEMOD synapses. Boolean functions are demonstrated with only one or two FEMOD devices operating at low voltage and low power consumption. The proposed device structure performs multi‐functions of biological synapse and Boolean logic, thus provides high potential for the future large scale and low power neuromorphic computing applications.


Introduction
Neuromorphic computing inspired by the neural network systems of the human brain enables energy efficient and high performance computing to overcome the von Neumann bottleneck for big-data processing. [1][2][3] A neural network is formed by thousands or even millions of neurons which are connected by even a higher number of synapses. The main responsibility of synapses is to transfer information from the pre-synaptic to ferroelectric gate oxide [15][16][17][18] is applied to enable artificial synapse functionality. In detail the gate or the source is connected to the pre-neuron while the drain is used for the terminal of the postneuron. The recent discovery of HfO 2 -based ferroelectrics further boosts the research on FeFETs for neuromorphic applications because of its CMOS compatibility and scalability. [15,16,19,20] Focuses of those abovementioned devices have been mainly put on the homosynaptic plasticity, which is input specific, meaning that the plasticity occurs only at the synapse with a pre-synaptic activation. [21,22] The homosynaptic plasticity has a drawback of positive feedback loop: when a synapse is potentiated, the probability of the synapse to be further potentiated is increased. Similarly, when a synapse is depressed the probability of the synapse of being further depressed is higher. Therefore, synaptic weights tend to be either strengthened to the maximum value or weakened to zero, causing the system to be unstable. [21,22] In contrast, heterosynaptic plasticity which plays an important role in biological neural systems [21,22] can be simultaneously induced at any synapse after episodes of strong postsynaptic activity, [22] thus avoiding the positive feedback problem and stabilize the activity of the post-synaptic neuron. To realize the heterosynaptic plasticity, an additional modulatory interneuron is needed to modulate the synaptic weight between the pre-and post-synaptic neurons, [23][24][25][26][27][28][29][30] as seen in Figure 1a. Transistors with one extra gate forming four-terminal devices can offer heterosynaptic plasticity functions. [28][29][30] Those have been demonstrated using transistors with 2D materials like MoS 2 [28] or WSe 2 , [30] where the bottom gate serves as the modulatory neuron. However, high modulation voltages are needed in those devices due to the thick dielectric layer at the bottom gate causing low modulation efficiency.
As discussed above, FeFET is a very strong candidate for artificial synapses and neurons, [18,20,[31][32][33] and can be used in nonvolatile memories, in-memory computing and reservoir computing. [34] Both excitatory and inhibitory functionalities which are essential for artificial neural networks (ANN) can be realized in FeFET neurons. [35,36] In an FeFET, the device conductance is gradually programmed by gate controlled polarization of the ferroelectric layer. [37] However, the switching of the device from weak channel inversion with low conductance to strong channel inversion with high conductance is very rapid, causing a small number of conductance states and poor linearity in the long-term plasticity, [38] thus resulting in a poor learning accuracy. In this respect, ferroelectric Schottky barrier MOSFETs (FE-SBFET), [39] where the ferroelectric polarization is used to program both the channel conductance and the carrier transport through Schottky barriers at source and drain, can increase the conductance states by more gradual programming of the Figure 1. FEMOD heterosynapse device structure and its working mechanism. a) Illustrations of a biological heterosynapse connected with pre-/postsynaptic neurons and a modulatory neuron. b) The artificial FEMOD heterosynaptic device proposed in this work. Two NiSi 2 /Si Schottky diodes gated with a ferroelectric HZO layer form a four-terminal heterosynaptic device. c) Schematic view illustrating the modulation of the Schottky barrier by partial ferroelectric polarization switching under gate voltage pulses. Increasing number of holes at the NiSi 2 /Si interface with increase of number of voltage pulses, causing a thinner Schottky barrier of NiSi 2 to Silicon at the valence band (E v ), and thus a gradual programming of the diode conductance. d) multi-synaptic functions can be achieved. The inset in (c) shows schematically the pulse bias configuration on an FEMOD synapse.
www.advelectronicmat.de device conductance with modulation of the ferroelectric polarization . In addition, the ambipolar switching of the FE-SBFETs offers reconfigurable excitatory and inhibitory responses by using p-or n-channel. [40] Combining the hetero-synaptic plasticity and the behavior of Schottky diode, we propose and demonstrate, in this work, a very simple device structure as an artificial synapse. The device is based on ferroelectric polarization modulated Schottky diodes (FEMOD) on silicon to mimic the hetero-synaptic plasticity of biological synapses. The working principle of FEMODs is similar as FE-SBFETs, using the gate to control the carrier injection through the Schottky barrier into the channel. Unlike conventional FE-SBFETs, the FEMOD device has two separated gates. The tuning of the conductance of both the gated channel and Schottky barrier enable us to achieve more conductive states for learning. Each synapse can be modulated independently, thereby achieving hetero-synaptic plasticity. The FEMOD device employs Si CMOS compatible Hf 0.5 Zr 0.5 O 2 (HZO) as ferroelectric and TiN as metal gate. The choice of HZO in this work is due to its better thickness/area scaling abilities, low annealing temperature, and high ferroelectricity. [31,41] In addition to these advantages, HZO-based devices can be constructed with desired properties by tuning the chemical concentration and defect engineering. [42] The epitaxial single crystalline NiSi 2 provides uniform Schottky contacts to silicon. The device is fabricated with Si CMOS front-end process, which offers a big advantage for circuit design. The four-terminal layout of FEMOD synapse allows multi hetero-synaptic functions with high speed and low energy consumption. Moreover, Boolean logics, like AND, NAND, XOR, and NOR can be realized with simple FEMOD cells.

Structure and Working Mechanism of the FEMOD Heterosynapse
The proposed FEMOD device to mimic heterosynaptic plasticity as shown schematically in Figure 1b uses Si CMOS based materials and technologies. Two metallic NiSi 2 contacts, named as source and drain form two back-to back electrically connected Schottky diodes on a silicon-on-insulator (SOI) substrate. The use of single crystalline NiSi 2 as Schottky contacts provides a super smooth interface with Si and thus offers a very uniform contact to Si. Then a ferroelectric layer of HZO is deposited on top of the structure. Two separate gates with TiN layers are formed, close to the source and drain Schottky diodes, respectively. The total resistance R of the device includes the source resistance R S , drain resistance R D , and the silicon resistance R Si .
R Si consists of the channel resistances which are modulated by the two gates, and the Si series resistance between the two gates. The source and drain resistance are dominated by the Schottky contact resistance. From the thermionic-field emission theory R S and R D are given by: [43] where q is the electron charge, φ b the Schottky barrier height, N S/D the carrier concentration in the Si channel close to the source or drain, h the Planck constant, ε s the dielectric permittivity of silicon, m * the effective mass of the tunneling carrier. V eD is the effective voltage applied on the drain diode.
The Schottky diode at the drain is forward biased when V DS is negative. Therefore, the programming gate at the source side (Gate 1 in Figure 1b) modulates not only the channel resistance in the region under Gate 1 but also the R S by changing N S . Similarly, the modulating gate (Gate 2 in Figure 1b) at the drain side changes R D and the Si channel resistance under Gate 2 by changing N D , thus providing high modulatory ability. The overlap of the gate to the NiSi 2 is just for a simple process to avoid a large gate/NiSi 2 underlap. Compared to the published four-terminal synapses, [30,44,45] our device benefits from a symmetric source/drain configuration, allowing high flexibility for circuit design.
To explain simply the programming of the FEMOD with voltage pulses we plot the polarization and the corresponding energy band in Figure 1c. The partial polarization switching of the HZO ferroelectric by a negative voltage pulse on the gate induces additional holes at the gate controlled Si channel region. The density of holes increases with the number of pulses due to the increasing domain polarization. As a consequence, the hole accumulation at the NiSi 2 /Si channel interface causes SB thinning at the valence band (E v ) as demonstrated by the band diagrams shown in Figure 1c, resulting in a higher injection rate of holes by tunneling through the thinner SB, as demonstrated in Equation 2. Therefore, an increase of the number of pulses gradually programs the conductance from source to drain. The device can mimic both, the short and longterm plasticity of a biological synapse by applying a voltage pulse on the programming gate as the pre-synaptic spike (V pre in Figure 1d), a voltage pulse on the source as the post-synaptic spike (V post ), a voltage on the modulating gate (Gate 2) as a modulatory spike (V mod ), and a drain voltage (V DS ) for reading. The device functionality includes excitatory/inhibitory post-synaptic current (EPSC/IPSC), paired-pulse facilitation/depression (PPF/PPD), long-term potentiation/depression (LTP/LTD), as well as biological neuron-like spike-timing-dependent plasticity (STDP), as listed in Figure 1d.

Material and Device Direct Current (DC) Characterization
The fabricated FEMOD structure is depicted in the crosssectional transmission electron microscope (TEM) images in Figure 2a for the NiSi 2 /Si Schottky contact and in Figure 2b for the TiN/HZO gate stack on the Si channel. The TEM unravels a single crystal NiSi 2 layer forming an abrupt NiSi 2 /Si interface which is further demonstrated in the high-resolution TEM www.advelectronicmat.de image in Figure S1, Supporting Information, offering superior properties of Schottky contacts with high uniformity and stability. The HZO film deposited by atomic layer deposition (ALD) on the NiSi 2 layer shows also excellent smooth interfaces to the bottom NiSi 2 and the top TiN electrodes. A SiO x interfacial layer (IL) with a thickness of 1.6 nm is formed at the NiSi 2 / HZO interface, which is attributed to oxidation of the NiSi 2 during the annealing of the HZO film to the form ferroelectric because SiO x is easily to be formed during oxidation. [46] The interfacial layer was also confirmed in the energy dispersive X-ray (EDX) mapping as shown in Figure S2, Supporting Information. The ferroelectric polarization-voltage loop with a counterclockwise hysteresis for the 10 nm thick HZO layer is shown in Figure 2c by measuring the TiN/HZO/NiSi 2 metal-ferroelectric-metal (MFM) capacitor. Only a small switching current density is observed as a result of the structural perfection of the TiN/HZO/NiSi 2 interfaces and possibly also due to the interfacial oxide layer. More analysis of the ferroelectric characteristics of the HZO MFM capacitor is given in Figure S1, Supporting Information.
The transfer characteristics given by the drain current I D versus the programming gate voltage V pro are presented in Figure 2d with V pro sweeping from −2 to 2 V and then sweeping back to −2 V, at a modulating voltage of V mod = 0 V and −1 V, respectively. At an applied drain-source voltage of V DS < 0 V for a p-type Si layer, the source diode is reverse biased and the drain Schottky diode is forward biased. Clockwise hysteresis is shown for both V mod curves, which is caused by the ferroelectric polarization. A memory window (MW) of 0.26 V is extracted for V mod = 0 and −1 V at a constant current of 1 nA. A larger MW (MW = 0.6 V) is obtained by sweeping a larger voltage range, V GS1 sweeping from −4.0 to 4.0 V, seen Figure  S3, Supporting Information, similar to conventional FeFETs, [47] which is caused by the increased polarization at higher voltages (Figure S1e, Supporting Information). At V mod = −1 V drain currents are much larger than that at V mod = 0 V. Furthermore, the modulation of V mod on the on-current I ON is shown in Figure 2e, which shares similarity to the I D -V pro characteristics, demonstrating the modulation ability of V mod for the device current. A small V mod can cause a large current change, showing a great advantage for low power application in comparison with reported four-terminal devices with a back gate. [28][29][30] The I D -V DS output characteristics show typical transistor behavior (Figure 2f).

Short-Term Heterosynaptic Plasticity Characterization
In biological nervous system, synaptic plasticity specifically refers to the activity-dependent modification of the strength or efficiency of synaptic transmission at preexisting synapses, [48] which includes short-term plasticity and long-term plasticity. The FEMOD-based artificial synapse is characterized with the configuration displayed in Figure 1a. Voltage pulses V pro www.advelectronicmat.de are applied on the programming gate (Gate 1) as pre-synaptic spikes. The source works as the post-synaptic neuron with currents as the output, Gate 2 is used as a modulatory neuron with a modulating voltage V mod , and the drain voltage V DS is used for reading. EPSC, which is the current of a post-synaptic response to a pre-synaptic stimulus and can measure the synaptic strength [14,49,50] is first characterized by measuring the transient source current for a single voltage pulse applied on the programming gate. Figure 3a displays the EPSC response of a synapse recorded after a starting time of 200 µs, with different pulse amplitudes applied on Gate 1, ranging from −0.8 to −2.0 V and a pulse width t pw = 1 µs at a fixed V mod = −2.0 V. The EPSC was recorded at V DS = −0.1 V.
Since the thermionic emission is less dependent on the gate voltage, the EPSC is mainly contributed by tunneling currents as the Schottky barrier is thinned by the gate electrical field and the polarization induced charges in Si as shown in Figure 1b. The tunneling current through a Schottky barrier φ b at the source is simply expressed as: [43] For EPSC decay the gate voltage pulse has already finished. The carrier concentration N includes the initial doping of the substrate N 0 and the polarization induced charges. N 0 is very small due to the low doping of the SOI substrate, thus: α is a factor to convert the polarization P to the volume charge concentration. The polarization decay with time P(t) in the absence of an electrical field for a ferroelectric layer is given by: [51,52] exp 0 0

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where P 0 is the initial polarization, t 0 is the characteristic time, n is a constant depending on the dimensionality of the domains. Combining Equations (1-4) we obtain: The measured EPSC decay can be fitted perfectly using the above equation as indicated by the dashed red lines in Figure 3a. The EPSC shows a decay time in the range from 10 to 50 µs, increasing with higher pulse amplitude V pro . Compared to FeFETs reported by Yoon et al., [49] the EPSC results in this work show a much longer decay time, which could be due to the different ferroelectric materials and different structures. The EPSC peak value increases with |V pro | (Figure 3b), which can be fitted with EPSC exp because the initial polarization P 0 is proportional to V pro . [53] Figure 3c shows the modulation effect of V mod on the EPSC at a fixed V pro = −2.0 V. A more negative V mod strengthens the EPSC because more holes are introduced by the electrical field and stronger polarization at the drain and thus reducing the contact resistance of the drain. In contrast, a positive V mod depletes holes or even inverts the overlapped Si region to electrons, and induces depolarization and even an opposite polarization to the source side, causing higher contact resistance at the drain and thus lowering the EPSC. Therefore, the modulatory neuron can effectively modulate the synaptic plasticity between the pre-and post-synaptic neurons. The EPSC response is very fast working even with a pulse width (t pw ) of 20 ns with a peak EPSC value of ≈11 nA as seen in Figure 3d,e. Longer EPSC time can be achieved by increasing the pulse duration time to enhance the polarization of the HZO layer. An energy/spike consumption E = 0.45 fJ at t pw = 20 ns is calculated by E = V pro × EPSC × t pw , demonstrating very high energy efficiency of the device (Figure 3e). PPF and PPD are common features for the short-term plasticity of biological synapses. [48,54] PPF/PPD, is defined as, where EPSC 1 and EPSC 2 correspond to the EPSC amplitude generated by the first and the second pre-synaptic spikes. In PPF, the EPSC is further increased by the second pulse which is applied before the EPSC created by the first pulse has completely decayed. Thus PPF strengthens the memory for learning. PPD is just opposite action, reflecting the forgetting. The PPF/PPD measurement is shown in the Supplementary ( Figure S4, Supporting Information). Figure 3f presents the PPF/PPD as a function of the pulse time interval. The PPF/PPD data reflects an exponential decay as indicated by fitting lines using the Ebbinghaus forgetting curve: [55] PPF PPD 0 1 where C 0 is the background, t the pulse interval time, C 1 the initial facilitation/depression magnitude, and τ 0 is the decay time constant. The obtained small τ 0 (2.3 µs for PPF and 4.5 µs for PPD) values indicate a short memory or short retention time which is due to the partial polarization of the HZO layer by low and short voltage pulses. The retention time can be improved by applying a high voltage and long pulses, however with the costs of high energy consumption and low speed. The retention time can be very long when the applied voltage is higher than the coercive voltage (≈3 V) of the ferroelectric material ( Figure  S5, Supporting Information).

Long-Term Heterosynaptic Plasticity Characterization
The synaptic strength of synapses is bidirectionally modifiable by different patterns of activity, namely long-term potentiation (LTP) and long-term depression (LTD). [48] The consequence of LTP/LTD ( Figure S6, Supporting Information) corresponds to learning-forgetting-relearning behavior of biological brains.
Here, the long-term plasticity of the synapse is characterized by measuring the conductance from source to drain under a series of repeated programming pulses applied on Gate 1, with Gate 2 as the modulatory neuron. Figure 4a presents the measured conductance for a synapse programmed by 50 identical negative pulses (V pro = −0.5 V, a pulse width t pw = 1 µs and a pulse interval t pi = 1 µs) at V mod = −2.0 V for potentiation followed by 50 identical positive voltage pulses (V pro = 0.5 V, t pw = t pi = 1 µs) for depression. It shows a maximum/minimum conductance ratio G max /G min = 79. The conductance in the conventional FeFET reported in ref. [38] increases rapidly with a few pulses and then reaches almost saturation when identical pulses is applied, thus resulting in only a few analogue states of 20 and poor linearity. The change of the conductance in such device is caused by the programming of the channel conductance. After a few pulses the channel is switched from weak inversion to strong inversion. In contrast, the conductance of our device is mainly from the Schottky tunneling which can be programmed gradually, thus leading to much more analogue states of 50 and much better linearity. Likewise, the synapse conductance was also measured using 50 non-identical pulses (increasing amplitude, as shown in the inset of Figure 4b). Much better linearity and symmetry for the potentiation/depression with very high G max /G min = 151 are achieved compared with the results in Figure 4a because the polarization is modulated more slowly with non-identical pulses. The fitting parameters for the non-linearity and symmetry is shown in Table S3, Supporting Information. The device shows a high endurance, small cycle-to-cycle (CTC) and device-to-device (DTD) variations ( Figure S5, Supporting Information). V mod can improve the G max /G min ratio, LTP/LTD symmetry and CTC variation as shown in Table S3 and Figure S6c, Supporting Information. The higher number of states (here 50), small CTC variation, high G max /G min = 151 and good linearity are essential for a high training and learning accuracy which will be discussed in the following section.
STDP which is an important learning rule was measured using the configuration shown in Figure S7, Supporting Information. The measured symmetric STDP (at V mod = −2.0 V) is displayed in Figure 4c. Here the STDP functionality was mimicked by plotting the synaptic weight, w, as a function of ∆t (the time difference between the post-and pre-synaptic spikes). The characterization detail and calculation of w are presented in the supplementary materials and Figure S7, Supporting www.advelectronicmat.de Information. The STDP distribution shows a Gaussian function as indicated by the fitting line in Figure 4c. At V mod = 0 V, it is difficult to measure the STDP because the current is too low. At V mod = −1.0 V the STDP ( Figure S8, Supporting Information) shows similar STDP behavior but with smaller weights as compared with Figure 4c. Therefore, the modulatory neuron can also modulate the STDP weight of the synapse between pre-and post-synaptic neurons.

Supervised ANN Pattern Recognition Simulation
The synaptic response of the fabricated FEMOD device on applied pulses provides potential for spiking neural network (SNN) [18] and artificial neural network (ANN) [38,56] applications. We perform supervised learning simulation based on Neu-roSim [56] with a three-layer ANN (see Figure 4d) using training/ testing of 60k/10k images. The Modified National Institute of Standards and Technology (MNIST) database of handwritten digits were used for pattern recognition. As an example, a handwritten "0" is used, shown in Figure 4d. Figure 4e presents the simulated recognition accuracy based on the measured LTP/LTD results. Thanks to the large number of state (50 states), higher G max /G min ratio, and small CTC variations, a high learning accuracy of 91.3% is achieved at V mod = −1 V. The accuracy increases with an increasing negative V mod , and then saturates at V mod < −1.0 V. Using the non-identical pulses can further improve the accuracy (see Figure S9, Supporting Information) because of the higher G max /G min ratio, better linearity and symmetry, as well as smaller variations when a V mod < −1.0 V and non-identical pulses are applied. More simulation results can be found in Supplementary materials. The high speed and low power consumption of the FEMOD in this work are essential for mobile (i.e., the next generation 6G networks), smart devices, and internet-of things (IoT) applications. The supervised learning as demonstrated in present simulations could be used to reduce the path loss or to use for improved allocation of the bandwidth. [57]  c) The synaptic weight, w as a function of ∆ , showing a biological symmetric STDP. Green curve: data was fitted with a Gaussian function (an offset of 25%). d) Schematic diagram of the three-layer perceptron with 400 input neurons, 100 hidden layer neurons, and 10 output neurons based ANN simulation. An input pattern of handwritten "0" is used as the input. e) Recognition accuracy of simulation with different V mod . A high learning accuracy of 91.3% is achieved at V mod = −1.0 V with non-identical pulses. www.advelectronicmat.de

Neuromorphic Boolean Functions with FEMODs
Boolean logics are essential for neuromorphic computing. [23,41,42,[55][56][57][58][59][60] In human brains the decision making of "yes" or "no" is also similar to the binary "1" and "0" logic. In this section we present Boolean functions using FEMOD devices. Different from the synapse configuration discussed above, we use both gates as pre-synaptic neuron inputs in parallel as displayed in Figure 5a. Because of the modulation function of Gate 2, Boolean logic AND gate function is achieved with a single FEMOD device, as shown in Figure 5c by using the EPSC current I out as the output. The AND logic function measured at V DS = -1.0 V is demonstrated in Figure 5d. As aforementioned V mod can increase the EPSC, only when both inputs, V A and V B , have a high level (here −1.0 V) the output EPSC can reach a large value ("1" state), thus achieving the AND function as demonstrated by the truth table in Figure 5d.
We estimate the power consumption P for AND operation as follows: www.advelectronicmat.de · DS out = P V I (10) Corresponding to each AND operation we obtain: 10 0,0,0 0 ,1,0 1,0,0 ≈ ≈ = P P P n W (11) As an average each operation of AND consumes (430+30)/4 = 115 nW which is about 2 times higher of the CMOS AND logic with 6 transistors (67.6 nW). [61] The power consumption can be further lowered by scaling of the device to reduce V DS . We need only one FEMOD device for AND logic, much less than the CMOS AND (6 transistors), thus reducing the footprint area and providing potential for high density integration.
By connecting one resistor on the drain of an FEMOD device as indicated in Figure 5b,e we can realize a NAND gate. Figure 5f shows the measured NAND function using one FEMOD device and 1 resistor (1D1R) and the corresponding truth table with a pull-up resistor R = 200 kΩ at V DS = −1 V.
The optimization of the pull-up resistor is presented in the Figure S10, Supporting Information, by measuring a NAND inverter function where both inputs V A and V B are in parallel with the same input signal. The output voltage for {110} operation in Figure 5f shows a decay time of 64 µs due to the nonvolatile memory effects of FEMOD devices.
More logic functions can be achieved using two FEMOD devices and one resistor (2D1R), as illustrated in Figure 6a, where 2 FEMOD devices are parallel connected to a pull-up resistor (here 100 kΩ). The output currents with two FEMODs are presented in Figure S11, Supporting Information, showing the sum and OR logic functions, indicating that the device can be easily designed and integrated to crossbar arrays which are required for neuromorphic computing. By configuration of the four-inputs as indicated in Figure 6c,e,g, NAND, NOR, and XOR logic functions can be achieved as demonstrated by the measurement results shown in Figure 6d,f,h using the voltage inputs in Figure 6b. Since the NAND gate and NOR gate are universal gates, there are many possible circuits that could become higher integrated using FEMODs, as an example, Figure 6. Boolean functions with 2 FEMOD devices and 1 resistor (2D1R). a) Logic cells with 2D1R. b) Input voltage pulses for measurements with a pulse width of 100 µs. c) The NAND unit and its input configuration. d) The measured NAND. e) the XOR unit and its inputs, where V IN3 is the f) The measured XOR, where the dashed line represents the up-level of "0" state. g) A NOR unit and its input configuration. h) The measured NOR. The gray and yellow colors indicate the binary state "0" and "1," respectively. www.advelectronicmat.de a half adder requires five basic FEMOD cells. However, for conventional CMOS technology, the half adder is composed of 14 transistors. [61] One of the challenges for the logic gates shown here is the integration with a resistor, which causes high energy consumption, lower speed and larger integration area in comparison with standard CMOS logic gates. Integration of FEMODs on both p-type and n-type Si to achieve "complementary FEMOD" logic gates could be the solution. Together with further optimization of the FEMOD, this technology could potentially become more energy efficient than state of the art CMOS technology.

Conclusion
Low power, large bandwidth, and small footprint area are essential for applications like mobile and smart devices, IoT, and autonomous drones. In such aspects, we presented in this paper a simple artificial synapse structure based on FEMOD which utilizes gated NiSi 2 /Si Schottky diodes with an HZO ferroelectric layer. The ferroelectric polarization switching modulates the Schottky barrier and is thus programming the conductance between the two-metal contacts by a series of low voltage pulses. The hetero-synaptic plasticity is demonstrated with both short-and long-term plasticity (including symmetric STDP characteristics) characterization. The device is operated at low voltages with a very fast response (20 ns), showing a low energy/spike consumption (<1 fJ spike −1 ), very small circle-tocircle variations (≈1%), and high endurance. High learning accuracy (>91%) is achieved from the simulation based on the LTP/LTD results. Boolean functions, like AND, OR, NAND, XOR, NOR are realized with only 1 or 2 devices, which normally need more devices for the corresponding logic units by CMOS and other technologies. The complete Si CMOS technology with front-end process offers high device scalability and high integration density, for example, with arrays. The benchmarking with other devices in terms of figures of merit ( Table 1) demonstrates very suitable performances including high speed, low power consumption, good linearity for high accuracy training, with the tradeoff of a short retention time. Furthermore, future optimization of a shorter gate length down to the nanometer scale could result in even less power consumption and higher speeds.

Experimental Section
Device Fabrication: Slightly p-type doped (10 16 boron cm −3 ) SOI substrates with a 55 nm thick top Si layer and a 145 nm thick buried oxide (BOX) layer were used. Device area was defined by mesa etching. Then 10 nm thick single crystalline NiSi 2 layers were formed at source and drain regions with a distance of 10 µm by self-aligned silicidation process with a sacrificial gate: rapid thermal annealing (RTA) of a 3 nm Ni at 800 °C in forming gas (10% H 2 in N 2 ) atmosphere followed by a selective etching process to remove the unreacted Ni. [64,65] After etching the sacrificial gate and cleaning, a 10 nm thick HZO ferroelectric layer grown by atomic layer deposition and a 40 nm thick TiN layer by sputtering were deposited to form the gate stack. Tetrakis (ethylmethylamino) hafnium (TEMAHf) and tetrakis (ethylmethylamino) zirconium (TEMAZr) were employed as precursors for Hf and Zr. An RTA at 500 °C for 30 s in Ar atmosphere was performed to crystallize the HZO into the ferroelectric phase. Next, the gate stack was patterned by photolithography and reactive ion etching. The device fabrication was finished by an oxide layer passivation, contact window opening, and metallization with Al.
Electrical Characterization: All the measurements were performed in air environment. The polarization of the HZO ferroelectric layer was characterized with TiN/HZO/NiSi 2 MFM capacitors using a TF Analyzer 2000 of aixACCT System and a precision Agilent E4980A LCR Meter. The device characteristics, synaptic functions, and logic gates were evaluated using a Keithley 4200-SCS semiconductor analyzer system with 4225-PMU pulse measurement units, a Tektronix DPO70604C digital phosphor oscilloscope, and a Tektronix AWG7122C arbitrary waveform generator. An example of the STDP measurement setup is shown in Figure S5, Supporting Information.
Material and Structure Characterization: The STEM, EDX, and TEM samples were prepared with FEI Helios 600 NanoLab. The TEM images were acquired in an FEI Tecnai G2F20 operated at 200 keV. The STEM Table 1. Benchmarking of this work with other reported devices in terms of figures of merit.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.