Structural Engineering of H0.5Z0.5O2‐Based Ferroelectric Tunneling Junction for Fast‐Speed and Low‐Power Artificial Synapses

Advanced synaptic devices capable of neuromorphic data processing are widely studied as the building block in the next‐generation computing architecture for artificial intelligence applications. Due to its fast speed, low power, and excellent complementary metal‐oxide‐semiconductor (CMOS) compatibility, Zr‐doped HfO2 (HZO)‐based ferroelectric tunnel junction (FTJ) are promising candidates as a new type of non‐volatile memory for neuromorphic device applications. Here, an experimental approach is reported to enhance the tunneling efficiency and the electrical performance by engineering the dielectric stack of the FTJ device. By sandwiching the HZO ferroelectric layer with ZrO2 and Al2O3 layers, the FTJ tunneling current is greatly increased with lowered barrier, larger remnant polarization (Pr), and tunneling electrical resistance ratio as well as suppressed leakage current have been achieved. The optimized FTJ devices are further implemented emulating synaptic functions with demonstrated short/long‐term synaptic plasticity and spike‐timing‐dependent plasticity behaviors. Such engineering in HZO‐based FTJ devices can be promising and instructive for the realization of future ultra‐low‐power and CMOS‐compatible neuromorphic devices and systems.


Introduction
The rapid development of information technology has urged great demands for advanced logic and memory devices toward low-power and high-speed data processing and storage. At present, traditional computing systems based on von Neumann architecture have challenges in power consumption, scalability to large networks, and execution speed. [1][2][3] Since the human www.advelectronicmat.de better capability in scaling down and CMOS process compatibility. [23][24][25] These HfO 2 -based ferroelectric films can maintain considerable P r even with a film thickness less than 10 nm. [26,27] Compared to other doping elements like Al, Y, Gd, La, and so forth, Zr has similar atom radii as Hf, and robust ferroelectricity can be achieved by Zr doping. [28] It has been reported that the Hf 0.5 Zr 0.5 O 2 (HZO) film should be thinner than 5 nm to achieve an adequate on-state current in FTJ. [29,30] However, with such thin HZO functional layer, the leakage current will notably increase, which will inevitably degrade the fatigue characteristics of the device [31] and sometimes even the TER value. [32][33][34][35][36] This will severely influence the feasibility of FTJ in synaptic device applications. For instance, Yoon et al. prepared FTJ devices with HZO thicknesses of 4 and 5 nm, and the TER values were less than 10. [37] Sulzbach et al. used a 4 nm HZO film to fabricate FTJ device, and the device performance was significantly attenuated after only 300 operational pulses. [38] Similarly, ≈40% degradation in residual polarization after 1000 operational pulses was observed in the work by Lyu et al. [39] Here, in this work, we report an HZO-based FTJ synaptic device with the ferroelectric HZO film sandwiched between a ZrO 2 seed layer and Al 2 O 3 capping layer for performance enhancement. Such device structure optimizes the tunneling barrier of the FTJ in a similar way as the tunneling layer in a conventional charge trapping memory device. [40,41] P r is improved from 7.97 to 18.02 µC cm −2 , and ≈30 TER with enhanced retention and fatigue properties are achieved even with a 10 nm HZO film. Typical synaptic behaviors including excitatory postsynaptic current (EPSC), long-term potentiation/ depression (LTP/LTD), paired pulse facilitation (PPF), and spiketiming-dependent plasticity (STDP) have been well obtained. The nanosecond-level response time and fJ-level power consumption make the engineered FTJ devices promising for future synaptic device and human brain-like artificial intelligence system applications.

Results and Discussion
We have designed and fabricated devices using HZO/Al 2 O 3 (10/3 nm) stack without (Device-1) and with (Device-2) ZrO 2 as the seed layer (the thickness of ZrO 2 seed layer is 2 nm if not specified). Besides, a reference device (refer as Reference) with only HZO sandwiched between the metal electrodes is also fabricated for comparative study. Highly doped p-type silicon was used as the substrate, and the dielectric stack was grown by ALD followed by Ti/Au top electrode formation (detailed device fabrication is illustrated in Figure S1, Supporting Information). The structures of the fabricated devices are schematically demonstrated in Figure 1a-c. Figure 1d shows the cross-sectional transmission electron microscope (TEM) image of Device-2, and the corresponding energy dispersive X-Ray spectroscopy (EDX) is illustrated in Figure 1e. The Al 2 O 3 , HZO, and ZrO 2 layers are clearly observed with sharp interfaces. It is noted that a thin layer of SiO 2 (≈1 nm) exists at the ZrO 2 /Si interface. This is due to the oxidation of silicon substrate prior to the ALD deposition at relatively high temperature (300 °C). From the X-ray photoelectron spectroscopy (XPS) result shown in Figure 1f, the stoichiometric ratio of Hf:Zr:O is calculated to be ≈0.91:0.97:2, which is close to the ideal value (XPS characterization of Zr 3d is shown in Figure S2, Supporting Information).
As mentioned above, TER ratio is a critical characteristic of FTJ devices that can be affected by film thickness, growth method, type of bottom or top electrode, annealing time, annealing temperature, and so on. In our work, Device-1 utilizes an HZO/Al 2 O 3 stack structure in which the inserted 3-nm

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Al 2 O 3 acts as a tunneling layer, when the FTJ synapse device working in the low resistance state (R on ). Due to the large mismatch of dielectric constant between HZO and Al 2 O 3 , when an external electric field is applied, carriers are injected through the thin Al 2 O 3 layer and trapped at the HZO/Al 2 O 3 interface, as shown in Figure S4 (Supporting Information). The mismatch between spontaneous polarization charge and the compensating charge at the HZO/Al 2 O 3 interface results in a large interfacial polarization, which further leads to a significant improvement in remnant polarization (P r ). [42][43][44] As a result, for the R on state of Device-1, the band tilt is greater than that of the Reference ( Figure S4, Supporting Information), resulting in a reduction in the barrier width and thus a larger on-current. On the other hand, when FTJ is in the high resistance state (R off ), the inserted Al 2 O 3 layer increases the total thickness of the dielectric layer, which makes the electron tunneling more difficult, leading to a smaller off-current. It should be noted that a thinner Al 2 O 3 cannot provide sufficient tunability on the band offset, while a much thicker Al 2 O 3 will hinder the electron tunneling. Ryu et al. have reported that the TER value of FTJ devices could be effectively increased when the thickness of Al 2 O 3 is ≈3 nm.
Compared with Device-1, a ZrO 2 seed layer is introduced to Device-2, which is employed to tune the ferroelectricity of HZO film. [45] First, a seed layer could promote the lateral growth of high density film instead of island like growth during atomic layer deposition (ALD). Second, the introduction of ZrO 2 seed layer before ALD deposition of HZO could decrease the defective interface states originated from the native oxide on silicon substrate. In addition, in the initial cycles of ALD process for HZO film growth on the surface of bare silicon, the existence of native oxide layer with tensile strain effect will increase the grain size of HZO. The smaller lattice mismatch between ZrO 2 and HZO films suppresses the tensile strain effect decreasing the grain size of HZO in Device-2 than that of Device-1. Such smaller grain size can effectively prohibit the transition of HZO film from tetragonal phase (t-phase), which is mainly related to the formation of the ferroelectric orthogonal phase (o-phase), to monoclinic phase (m-phase), thus improving the ferroelectricity with higher remnant polarization. [46][47][48][49][50] Figure 2a shows the polarization hysteresis of Reference, Device-1, and Device-2 with different thicknesses of ZrO 2 (referred as 1-4 nm), respectively. The dependence of P r and coercive electric field (E c ) extracted from Figure 2a on the thickness of ZrO 2 is shown in Figure 2b. The stars in Figure 2b represent the data values of the Reference device. As compared to the Reference device, clear enhancement in both P r and E c has been observed from Device-1 and Device-2. This is due to the insertion of Al 2 O 3 which introduces additional interfacial polarization and dielectric thickness. It is also noted that the ferroelectricity of Device-2 is dependent on the thickness of the ZrO 2 seed layer. As the thickness of ZrO 2 increases, both P r and E c increase, reaching peak values when ZrO 2 is 2 nm, and then decrease with thicker ZrO 2 . For P r , the much thinner ZrO 2 film is discontinuous and its function as the nucleation layer for the HZO deposition is degraded. With much thicker ZrO 2 film, the characteristics of the ferroelectric HZO in the device is greatly dampened due to the larger contribution of the non-ferroelectric ZrO 2 . [49,[51][52][53] As   Figure 2. a) Polarization hysteresis loops of Reference, Device-1, and Device-2 with ZrO 2 layer thickness of 1, 2, 3, and 4 nm. b) Dependence of P r and E c on the ZrO 2 seed layer thickness for Device-2. c) Fatigue test for P r with 10 4 operation cycles. d) Retention test for P r with a duration of 10 4 seconds at 85 °C. Pulse amplitude is ±5 V and pulse width is 200 ns for both fatigue and retention tests.

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for E c , the inserted ZrO 2 layer with proper thickness can withstand part of the applied voltage enabling a larger E c . But the non-ferroelectricity of ZrO 2 will become dominant if the ZrO 2 is much thicker, and the E c thus decreases. From the above results, compared to the Reference device, the insertion of 3 nm Al 2 O 3 in Device-1increases P r from 7.54 to 8.47 µC cm −2 and E c from 1.26 to 1.37 MV cm −1 . Further device engineering with another 2 nm ZrO 2 seed layer in Device-2 boosts the P r and E c of Device-2 to 18.02 µC cm −2 and 1.84 MV cm −1 , respectively.
Fatigue and retention tests are then carried out on the three devices. The pulse voltage is maintained at ±5 V. As shown in Figure 2c, the Reference device exhibits electrical breakdown before 10 4 pulses, while the P r values of Device-1 and Device-2 are not attenuated and remain relatively stable after 10 4 testing cycles. Such improved fatigue property is attributed to the inserted Al 2 O 3 layer, which can prevent charge drift inhibiting accidental polarization reverse switching. Figure 2d shows the retention characteristics obtained at 85 °C (the retention characteristics at room temperature are shown in Figure S4, Supporting Information). During a duration of 10 4 s, the P r values of the three devices are well maintained with negligible degradation under the test conditions of both room temperature and 85 °C. Such good reliability in ferroelectricity is ascribed to the good film quality by using ALD growth with good interface quality between the dielectric layers.
We have further explored the ferroelectricity improvement of HZO based stack by characterizing the storage performance of Device-1 and Device-2. As mentioned above, the polarization direction in the ferroelectric layer can be changed by applying an external electric field. Due to the asymmetry structure of the device, two resistance states (R on and R off ) with different tunneling barrier widths and barrier heights will be formed. The tunneling current is exponentially dependent on the barrier width and barrier height, and therefore, the change of the potential barrier can effectively modulate the magnitude of the tunneling current. The storage performance of FTJ devices strongly depends on the ferroelectric properties of the ferroelectric layer, especially the P r value, which determines the degree of band bending. As shown in Figure 3a, we applied a series of pulses with an amplitude of ±5 V and width of 200 ns to the two devices, the measured TER ratio of Device-1 is ≈10 and is ≈30 for Device-2, which is higher than the values in most previously reported works. [54,55] Within the 10 6 test cycles, the loss of TER of Device-1 is larger than Device-2. This can be explained by analyzing the band diagram shown in Figure S4 (Supporting Information). For the Reference device, when a negative pulse is applied to the top electrode, the polarization of HZO (P) is directed from the silicon substrate to Ti/Au. The majority carrier of the p-type Si substrate accumulated at the interface, resulting in a lower barrier height (R on ). Similarly, the energy band bends to the opposite direction after applying a positive pulse, the semiconductor surface becomes depleted, resulting in an additional Schottky barrier, and thus significantly increased the device resistance (R off ). For Device-1, the inserted Al 2 O 3 layer with larger band gap functions as the tunneling layer. In the R on state, carriers only need to tunnel through the Al 2 O 3 barrier, which is much thinner than that of the Reference device. In the R off state, carriers need to cross both the Al 2 O 3 layer and part of the HZO layer during the tunneling process, and only limited carriers can appear at the opposite electrode, resulting in a small off-current. Compared to Device-1, P r value of Device-2 is much larger. For the R on state, due to the enhancement of P, the band bending of Al 2 O 3 is greater, so that the width of the tunneling barrier is further reduced, thereby obtaining a larger tunneling current. For the R off state, a larger P r leads to an increase in the tunnel barrier height, and the insertion of ZrO 2 brings an additional tunnel barrier width, so the tunneling current is smaller than that of Device-1. It is worth mentioning that, the p-type Si substrate also contributes to the large TER value. In the R on state, the surface of p-type Si substrate is accumulated due to the attraction of screening charge, while in the R off state the p-type Si substrate becomes depleted. Carriers need to pass through the depletion region to complete tunneling, and R off is further increased for the devices.
According to the above analysis, the insertion of ZrO 2 reduces R on and increases R off , both of which resulted in a larger TER ratio for Device-2 than that of Device-1. Figure 3b shows the resistance hysteresis curves of the two devices. The width of the applied pulse (t pulse ) is 500 ns with maximum voltage of ±6 V (inset of Figure 3b). Both devices can maintain the R on and R off states. The switching between the two states occurs near the E c measured above, but there is still a difference. This suggests that F-N tunneling and direct tunneling coexist in the device and F-N tunneling dominates. The resistance value is similar to that in Figure 3a. For Device-1, R on and R off are ≈1.5 × 10 6 and 2.2 × 10 7 Ω, respectively. For Device-2, R on and R off are ≈1.2 × 10 6 and 5.3 × 10 7 Ω, respectively. Device-2 has better performance in both R on and R off states, consistent with the results of the energy band analysis. Next, we studied the dependence of conductance ratio on pulse amplitude (V pulse ) and t pulse . As shown in Figure 3c, with increased V pulse amplitude, the conductance ratios of the two devices maintain ≈1 and then increase gradually. This is because small V pulse cannot effectively alter the polarization direction in the ferroelectric stack, and the two resistance states cannot be distinguished. When V pulse increases, P r of the ferroelectric stack becomes larger, making the band bending greater in the R on and R off states, and the two states are gradually separated so that the conductance ratio gradually increases. The maximum conductance ratio of Device-2 (≈290) is larger than that of Device-1 (≈90), which is consistent with the previous experimental results. Figure 3d shows the impact of t pulse on the conductance ratio. A series of voltage pulses with different widths are applied. From Figure 3d, it is also observed that the conductance ratio increases with longer t pulse , which suggests the change in the direction of ferroelectric polarization. When much smaller t pulse , HZO cannot be fully polarized, and the conductance ratio is relatively small. Compared with some previously reported FTJ storage devices, [1,14] our devices with an optimized structure exhibits a shorter response time (50 ns), which provides solid basis for the application of highspeed and high-sensitivity synaptic devices.
Based on the above experimental results, we have further characterized the synaptic behaviors of Device-2. Figure 4a,b shows schematic diagrams of the device structure and its corresponding synapse illustration. In the nervous system, neurotransmitters are the medium of communication between synapses. The neurotransmitters released by the presynaptic www.advelectronicmat.de neuron are received by the postsynaptic neuron and generate an electrical excitation, and the excited electrical signal is EPSC. We first explored the effect of signal duration (pulse width, t pulse ) on EPSC, which is shown in Figure 4c. With a fixed V pulse of −5 V, when t pulse varies from 50 to 600 ns, EPSC increases from 41.75 to 566.9 nA. The synaptic weight G = EPSC/V read can be used to measure the conduction capacity of synapses, and the inset of Figure 4c shows the linear dependence of ΔG on the pulse width. Figure 4d shows the impact of signal strength (pulse amplitude, V pulse ) on EPSC. With a fixed t pulse of 200 ns, when V pulse increases from 2 to 6 V, EPSC linearly increases from 19.7 to 269 nA. The energy consumption of the synapse can be calculated by W = V pulse ×I pulse ×t pulse . When t pulse is 50 ns and V pulse is −5 V, the power consumption is 10.44 fJ/spike with an effective device area of 6400 µm 2 . This suggests that the FTJsynapse device will produce different responses when transmitting different signals. It can realize the basic function of a synapse with low power consumption.
In real nervous system, the working environment of synapses is more complicated with more than one single signal. Therefore, the response of synaptic devices to multiple signals is also very critical to realize practical neuromorphic applications. When two consecutive pulses are applied to the synapse, it will produce two current responses. The latter

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can be affected by the previous stimulus and strengthened on the basis of the previous current signal, which is known as the PPF response ( Figure S7, Supporting Information). If the synapse is dually stimulated at the pre-synaptic and postsynaptic neurons, and the two stimuli are not applied at the exactly same time, the response current of the synapse will be affected by the two stimuli and is related to the time interval between them. STDP is used to describe this phenomenon. As shown in the inset of Figure 4e (red and purple lines represent the pre-synaptic and post-synaptic spikes, respectively), t pulse is 100 ns, and Δt = t post -t pre , ΔV = V post −V pre . The conductance of the device varies with Δt. This is because when Δt changes, the combined signal will change. Each Δt corresponds to a different peak voltage and duration of high voltage, so that the polarization state of the ferroelectric stack is also different.
This leads to a change in conductance value. The relationship between ΔG (ΔG = (G post −G initial )/G initial ) and Δt is shown in Figure 4e, demonstrating the test data and fitting curve. As the absolute value of Δt increases, the influence between the two stimuli becomes weaker, thus ΔG decreases, and it is similar with the response of biological synapse. Figure 4f is the long-term potentiation and depression performance of Device-2. Here, we adopted the testing scheme used by Chou et al., [9,13] applying a series of signals with constant t pulse (100 ns) and increasing absolute V pulse (V pulse = −3-−6 V, pulse step is −0.2 V). In the process of potentiation and depression, linearly varying conductance values are obtained, and 16 different states (4 bits) have been obtained from both processes, showing great potential in complicated neuromorphic computing applications. www.advelectronicmat.de

Conclusion
In summary, the ferroelectricity of HZO thin film and the performance of the HZO-based FTJ device have been greatly improved through structural engineering, using ZrO 2 seed layer and Al 2 O 3 capping layer with proper thickness. A maximum P r of 18.02 µC cm −2 and TER value of ≈30 have been achieved, which greatly enhances the memory performance of the FTJ device with good fatigue and retention characteristics at both room temperature and elevated temperature. Furthermore, synaptic functions have been well obtained including EPSC, PPF, LTP/LTD, and STDP. Experimental results show that the optimized FTJ device is capable of mimicking a biological synapse, and can produce a response with stimulus duration as short as 50 ns. The power consumption is as low as 10.44 fJ per spike. Such fast-speed and low-power performance of the HZO-based FTJ synaptic device can be attractive in the detection and capture of weak transient signal, as well as highdensity large-scale integration toward human brain-like artificial intelligence implementation.

Experimental Section
Highly doped p-type silicon with resistivity of 0.001-0.005 Ω cm was used as substrate and bottom electrode. Before the deposition of the dielectric stack, standard cleaning and hydrofluoric acid treatment were performed on the substrate to remove the native oxide layer on the surface of the silicon wafer, and the wafer was immediately loaded into the ALD chamber (Picosun R-200, Finland). The deposition of the dielectric stack was completed sequentially in situ, using TEMAHf, TEMAZr, TMA, and H 2 O as the Hf, Zr, Al, and O precursors, respectively. The chamber base vacuum and temperature were maintained at ≈1 KPa and 300 °C, respectively. The measured growth rate of HfO 2 , ZrO 2 , and Al 2 O 3 were 1.1, 1.1, and 0.9 Å per cycle, respectively. During the growth of HZO, the circulation of different precursors was controlled to make sure that the ratio of Hf and Zr was ≈1:1. In order to induce the phase transition of the dielectric stack to obtain ferroelectricity, TiN was used as a capping metal layer as the strain source during the rapid thermal processing (RTP). Thirty nanometer TiN was grown by physical vapor deposition (PVD), and RTP was carried out in a nitrogen atmosphere at 550 °C for 30 s. TiN was then removed via wet etching in NH 4 OH and H 2 O 2 for 5 min. Finally, the top electrode array (80 × 80 µm) was patterned by ultraviolet lithography and Ti (20 nm)/Au (100 nm) metal electrode was deposited by PVD. Scheme of the FTJ synapse device and the corresponding process flow of the device are shown in Figure S1 (Supporting Information).
The ferroelectricity test of the device was carried out by PremierII Ferroelectric Tester from RADIANT Technology. Typical test frequency was 1 KHz. When performing memory and synaptic tests, WGFMU and SPGU modules of 1500A from Agilent Technology were used to generate voltage pulses, and the read voltage was kept at 0.5 V. During high temperature test, heat source was provided by KER3101-COSSim system.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.