Reconfigurable Field‐Effect Transistor Technology via Heterogeneous Integration of SiGe with Crystalline Al Contacts

Reconfigurable field‐effect transistors, capable of being dynamically programmed during run‐time, overcome the static nature of conventional complementary metal‐oxide semiconductors by reducing the transistor count and the circuit path delay. Thereby, SiGe and Ge are predicted to boost drive currents, switching speed and to reduce power consumption. Nevertheless, Ge‐based reconfigurable field‐effect transistor prototypes have so far fallen short in reaching both the promised performance due to interface instability to their contacts and gate oxides, as well as in reaching the current–voltage symmetry necessary for circuit applicability. Here, a top‐down fabricated SiGe‐based reconfigurable transistor technology is reported that is comprised of a vertical Si‐Si0.67Ge0.33 heterostructure enabling the envisioned high and symmetric on‐currents of both n‐ and p‐type operation. Monolithic integration with single‐elementary crystalline Al contacts alleviates process variability compared to conventional Ni‐silicide/Ni‐germanide contacts and introduces an ultra‐thin Si interlayer providing stability and equal injection efficiency of holes and electrons. The implementation of a three top‐gate transistor in combination with a hysteresis‐free Si/SiO2/HfO2 gate stack enhances polarity control and leakage current suppression to limit static power dissipation. Importantly, the obtained Al‐Si‐SiGe multi‐heterojunction and advanced reconfigurable transistor design is the first Ge‐based technology showing the envisioned stability and performance enhancements.


Introduction
The transition from conventional integrated circuits with fixed physical layout and functionality to logic systems capable of run-time reconfiguration is one of the main lines of research targeting an increase in computational complexity at relaxed hardware and power consumption constraints. [1][2][3] Such a technological advance further poses high potential enabling new types of circuit functionality [4] while simultaneously reducing the transistor count, power consumption, and circuit propagation delay. [5,6] In this regard, reconfigurable field-effect transistors (RFETs), have the feature of unifying unipolar n-and p-type transistor characteristics into a single electrically programmable device, thus reducing fabrication complexity regarding transistor geometry and composition explicitly excluding doping, are considered as a key enabler of future adaptable nanoelectronics. [7,8,4] The concept of reconfiguration is supported by a broad family of emerging Schottky barrier field-effect transistors (SBFETs) that exploit the filtered injection Reconfigurable field-effect transistors, capable of being dynamically programmed during run-time, overcome the static nature of conventional complementary metal-oxide semiconductors by reducing the transistor count and the circuit path delay. Thereby, SiGe and Ge are predicted to boost drive currents, switching speed and to reduce power consumption. Nevertheless, Ge-based reconfigurable field-effect transistor prototypes have so far fallen short in reaching both the promised performance due to interface instability to their contacts and gate oxides, as well as in reaching the current-voltage symmetry necessary for circuit applicability. Here, a top-down fabricated SiGe-based reconfigurable transistor technology is reported that is comprised of a vertical Si-Si 0.67 Ge 0.33 heterostructure enabling the envisioned high and symmetric on-currents of both n-and p-type operation. Monolithic integration with single-elementary crystalline Al contacts alleviates process variability compared to conventional Ni-silicide/Ni-germanide contacts and introduces an ultra-thin Si interlayer providing stability and equal injection efficiency of holes and electrons. The implementation of a three top-gate transistor in combination with a hysteresis-free Si/SiO 2 /HfO 2 gate stack enhances polarity control and leakage current suppression to limit static power dissipation. Importantly, the obtained Al-Si-SiGe multi-heterojunction and advanced reconfigurable transistor design is the first Ge-based technology showing the envisioned stability and performance enhancements.
of charge carrier type across their Schottky junctions. [8][9][10][11][12] The concept has the potential to be extended to operate with steep subthreshold slopes by including band-to-band tunneling transitions, [13][14][15][16] positive feedback effects, and impact ionization. [17] Importantly, RFETs enable in general a "fine-grain" reconfiguration approach of circuits, which fundamentally differs from the "coarse-grain" approach as conventionally realized, for example, in field programmable gate arrays. In the latter, signals are routed to predefined logic and memory blocks, often resulting in high overall latency in data transfer and extensive chip area consumption. [18] In contrast, RFETs enable reconfiguration utilizing multiple-independently-gated regions that modulate the charge carrier type traversing across the transistors' active region, effectively filtering out the undesired charge carrier type and thus enabling programmable unipolar n-or p-type operation in a single device. A tangible circuit example is the realization of a reconfigurable logic gate that can provide dynamic run-time switching between NAND and NOR operation with only four or even three RFETs. [19] Other important logic gates, that can be envisioned using a lower number of transistors than in conventional CMOS technology, are highly compact XOR / XNOR gates realized with four RFETs, [10] capable of enabling majority (MAJ) logic and combinational circuits that are highly efficient in the computation of arithmetic operations. Further advantages of RFET-based logic gates and circuits over their CMOS counterparts include wired-AND capabilities [20] and suppression of parasitic charge-sharing effects in dynamic logic gates. [21] In this respect, prominent applications of such RFETs are currently being explored in the area of hardware security and in highly integrated combinational and sequential logic. [22] Although the inherent switching delay of a single Si RFET is higher than that of an Si MOSFET, it has been predicted by mixed-mode TCAD simulations that circuit operability is even possible in the GHz range. [23] While most RFETs are still based on Si, the utilization of Ge and SiGe as channel materials are expected to boost the performance metrics of these devices, thanks to the reduced band gap and higher carrier concentration, which translates into higher oncurrents and faster switching capabilities. In this respect, recent mixed-mode device TCAD calculations revealed the high potential of Ge and SiGe versus Si RFETs in terms of ring oscillator frequency, which is an important figure of merit for logic circuits. [23] Exploiting these features, the first realizations of Ge nanowire RFETs with reduced threshold voltages [24] and Ge on insulator-based RFETs have already been demonstrated. [25] However, the translation of the highly promising simulation results into fabricated devices has proven to be challenging due to the well-known instability of Ge interfaces to most insulators and metals. Indeed, highly relevant metrics required for circuit operability have not been shown yet, including sufficient symmetry of n-and p-type on-currents, lack of hysteresis, and reliability. These have been the result of the well-known difficulty to engineer an interface to the high-κ gate insulator with a low density of trap states. [26] Having high and symmetric on-currents is an essential prerequisite for logic applications, however, most metal-Ge junctions are affected by strong Fermilevel pinning close to the valence band, limiting the capability of injecting electrons into the channel. [27,28] So far, Ge-based RFETs suffer from high static power dissipation related to the source to drain leakage given the significantly lower band-gap compared to Si.
In this work, we address all these issues by the choice of composition and geometry of the semiconductor channel material as well as dedicated junction and oxide interface engineering solutions, for the first time yielding the leveraged RFET characteristics by intermixing Ge as predicted by simulations. Thereto, we have introduced a vertical Si-Si 0.67 Ge 0.33 -Si epitaxial channel stack selected the ideal stoichiometric composition of Si 0.67 Ge 0.33 and applied a reliable lateral Al-Si-Si 0.67 Ge 0.33 contact scheme that enables symmetric barrier heights, finally leading to the envisioned highly symmetric on-currents in n-and p-type operation. Remarkably, this behavior is enabled without any additional processes, such as strain engineering [29] or postgrowth treatments [30] allowing for a streamlined technology at different RFET dimensions. The unique formation of a thin Si-rich interlayer between single-crystalline Al contacts and the Si 0.67 Ge 0.33 channel delivers a junction with equal injection capabilities for both electrons and holes. Importantly, the application of these measures in our RFET architecture delivers high and symmetric on-currents, while also maintaining low current leakage between the source and drain. To further increase reproducibility and to eliminate hysteresis we have designed a sacrificial Si cap that is fully reacted into a SiO 2 interface layer with low-interface trap densities and the integration of a high-κ HfO 2 gate-insulator. This resulted in a stable device operation and ensures suitability for logic gates and circuits.

Results and Discussion
In this work, we report on the fabrication, structural analysis, and an in-depth investigation of the electronic transport in SiGe-based RFETs with enhanced and highly symmetric on-currents for both, n-and p-type operation modes. This is enabled by band-gap engineering, employing a vertical Si-Si 0.67 Ge 0.33 -Si stack into a monolithic metal-semiconductor heterostructure with high-quality single-elementary Al contacts. Based on a systematic analysis of Si x Ge 1−x with varying stoichiometric compositions carried out in Ref. [31], the ideal Ge content for delivering the envisioned equal injection capabilities for both electrons and holes was estimated to be 33% in this work. Importantly, using the proposed Si to Ge ratio, the relevant advantages of Ge (i.e., higher on-currents and higher switching speeds) are still accessible. Increasing the Ge content in the Si x Ge 1−x alloy would lead to a more dominant p-type behavior, due to the Fermi-level pinning close to the valence band, thus resulting in asymmetric on-currents of the n-and p-mode operation. [31] For device fabrication, a new type of ultra-low temperature molecular beam epitaxy (MBE) of silicon-germanium [32] enabled to grow a (100) surface oriented Si 0.67 Ge 0.33 layer with a thickness of d SiGe = 8 nm with high crystalline quality on top of the device layer of a silicon on insulator (SOI) substrate with a device layer of d Si = 20 nm. To cap the Si 0.67 Ge 0.33 layer, a Si layer with a thickness of d cap = 3 nm was grown atop. Subsequent to the mesa patterning of the nanosheets, thermal dry oxidation was applied to grow a SiO 2 interface layer, serving as a high-quality dielectric. Additionally, SiGe RFETs with an additional 7.5 nm thick atomic layer deposition (ALD) grown HfO 2 www.advelectronicmat.de as gate dielectric were fabricated and analyzed. Remarkably, using HfO 2 enhances the performance of the on-and off-currents. Extracted current-voltage (I/V) metrics are set in contrast to SiGe RFETs with SiO 2 as the gate dielectric in Table 1.
For device integration, nanosheets with a width of W NS = 400 nm and a length of L NS = 10 µm were pattered from the Si-Si 0.67 Ge 0.33 -Si stack (see Experimental Section) and contacted by Al source/drain leads. A subsequent monolithic contact formation via a thermally induced exchange reaction between the Si-Si 0.67 Ge 0.33 -Si nanosheets and Al contact pads was carried out by rapid thermal annealing (RTA) at T = 774 K to define the channel length of the transistors between L SiGe = 1.5 and 2 µm. The obtained Al contacts show no intermetallic phases and therefore no phase sequence formation or competition takes place as otherwise observed in most conventional contacts to Si/Ge such as, for example, Ni, Pt, Co, or Cu, forming silicides or germanides. [33][34][35] Instead, mono-elementary Al contacts to Si/Ge are obtained, thus enabling reliable and abrupt metal-semiconductor junctions important for SBFET device fabrication. [31] A high-resolution scanning transmission electron microscopy (HRSTEM) image of the epitaxially grown vertical stack embedded in an Al-Si 0.67 Ge 0.33 -Al heterostructure is shown in Figure S1 (Supporting Information). Making use of the unique electronic structure of this monolithic metalsemiconductor-metal heterostructure, resembling two highquality Schottky junctions accessing the active region, we apply three-top-gated regions to finalize the RFET fabrication. Thereto, by placing program gates (PGs) directly atop the two abrupt metal-semiconductor junctions, effective polarity control of the charge carriers into the channel as well as efficient suppressing of the off-current can be achieved. In correlation with the operation of conventional MOSFETs, the charge carrier concentration in the channel can be effectively modulated by the control gate (CG) placed in the middle of the channel. Importantly, the design involving three-top gate regions ensures the decoupling of the effects of selective current injection (i.e., polarity control) with the PGs and effective control of the charge carrier concentration with the CG. Figure 1a shows a colored scanning electron microscopy (SEM) image of the complete top-down fabricated SiGe RFET device. To better understand the fabricated Al-Si-Si 0.67 Ge 0.33 -Si-Al heterostructure, we have conducted additional detailed HRSTEM ( Figure 1b). Thereof, Table 1. Comparison of the key performance parameters of the proposed SiGe RFETs with SiO 2 and HfO 2 gate dielectric with Al-Si RFETs. The green highlighted cells indicate the best performance for each parameter. For comparison, the ten best-performing devices of each of the chips were considered to evaluate the mean values and standard deviation.  www.advelectronicmat.de a double interface between the Al contacts obtained from the Al-SiGe exchange reaction and the vertical Si-Si 0.67 Ge 0.33 -Si nanosheet was found. As shown in the orange box, an axial Al-Si-Si 0.67 Ge 0.33 multi-heterojunction is formed. This is in agreement with previous investigations of the Al diffusion in Si 1−x Ge x nanosheets, which have been systematically conducted with different Ge concentrations. [31] The sharply defined Si-rich segment sandwiched between the intruded Al contact and the unreacted Si 0.67 Ge 0.33 channel is evidently piled up during the thermally induced heterostructure formation and was found to be ≈5 nm in length. [31] With respect to the crystal structure, the unreacted Si-Si 0.67 Ge 0.33 -Si channel shows a diamond structure, oriented in a (110)-zone axis with a 001 out-of-plane orientation. The intruded Al contacts were identified as a face-centered cubic structure. Further, the interface between Al and Si follows a {111} facet of Si for the Si pile-up region and curves toward a {110} facet close to the Si 0.67 Ge 0.33 layer. This channel itself is terminated by two {111} facets bordering the Si interlayer. [31] We have to note that the metal-semiconductor exchange dynamics leading to the formation of the Al-Si-SiGe multi-heterojunction is not entirely clarified. However, the remarkably differing diffusion coefficients of Si and Ge in Al might play an important role as the Ge diffusion is significantly faster, which might promote the formation of the Si pile-up region. More details of the Al-Si-SiGe multi-heterojunction formation can be found in the supporting information. Further, we have investigated the gate stack by a cross-sectional HRSTEM seen in Figure 1c. The composition analysis of the stack revealed a conformal Π-shaped gate-oxide with a thickness of d ox = 6 nm. Further, it is evident that the thermal oxidation used for gate dielectric fabrication completely consumed the original Si capping layer on top of the Si 0.67 Ge 0.33 layer hindering the oxidation of the contained Ge and explaining the lack of hysteresis in the I/V characteristics. The overall quality of the gate stack is supported by the HRSTEM image in Figure S2 (Supporting Information) and the energy-dispersive X-ray spectroscopy (EDX) elemental maps in Figure S3 (Supporting Information). Next, we focus on the electrical properties of the proposed SiGe RFETs for both electron-and hole-conduction capabilities. Thereto, Figure 2a shows the subthreshold transfer characteristic for V DS = 2 V revealing unipolar n-type (red) and p-type (blue) operation from the same device by setting V PG = 5 and −5 V, respectively. The insets depict schematic illustrations of the band bending for both operation modes enabling the proposed RFET functionality. For n-type operation (cf. right inset) the barrier below the PGs is lowered to inject electrons from source to drain. In analogy, in p-operation mode (cf. left inset), the barrier below the PGs is shifted to enable the injection of holes from the drain to the source. For both modes, the respective dashed lines indicate the band bending configuration of the off-state. Importantly, high and symmetric on-currents were observed for both operation modes. The current densities in the on-state at V DS = 2 V are 114.7 kA cm −2 (41.3 µA µm −1 ) in n-type operation and 238.2 kA cm −2 (85.7 µA µm −1 ) for p-type operation, respectively. To set these values into perspective with the state of the art, Ge RFETs with Ni 2 Ge-Ge junctions reveal a factor of 88 and 15 smaller currents (normalized to the width) for n-and p-type operation respectively. [24] Even Ge RFETs with monolithic and single-crystalline Al-Ge junctions, showing enhanced p-type conduction due to Fermi level pinning to the valance band, are a factor of 2065 and 1.6 smaller for n-and p-type operation respectively. [36] Importantly, the obtained transfer characteristics reveal a low off-current of only 10 pA indicating an efficient suppression of source-drain leakage. This can be attributed to the three-gated region design of the proposed RFET featuring explicit tunability of the incorporated energy landscape. In this respect, despite having a significant Ge content, the I On /I Off ratios of the proposed SiGe RFETs is on par with state-of-the-art Si RFETs and is three to four orders of magnitude higher compared to Ge REFTs. [24,25] Moreover, inverse subthreshold slopes of S n = 435 mV dec −1 and S p = 245 mV dec −1 and threshold voltages of V th n = 0.79 V and V th p = −0.36 V have been obtained with the SiO 2 gate dielectric for the n-and p-type operation, respectively. Due to the excellent quality of the SiO 2 gate dielectric interface, only a minimal shift of the threshold voltage and hysteresis sweeping V CG was found. To set the given key performance parameters into perspective, Si RFETs based on the SOI substrate with 20 nm device layer and Al contacts have been fabricated and analyzed. As seen in Table 1, despite a slightly smaller on-current symmetry, the current densities, subthreshold slopes, and threshold voltages could be significantly improved with the proposed SiGe RFET. In this respect, by integrating a HfO 2 gate dielectric, an additional improvement of the subthreshold slopes and threshold voltages was achieved. The electrical characteristics of the SiGe RFETs including the HfO 2 are shown in Figure S5 (Supporting Information). To further investigate the polarity control in the proposed SiGe RFETs and to derive the optimal operating parameters and the stability range, Figure 2b provides a conduction map showing the drain current I D in a logarithmic scale for varying both V CG and V PG . In this respect, modulating the injection barriers via V PG , the RFET can be efficiently switched between electron (V PG = 5 V) and hole conduction (V PG = −5 V), resulting in two distinct operation on-states, marked with dashed white lines, as well as two distinct off states. Importantly, this representation confirms the operational stability of our SiGe-based RFETs as applied voltages can change in a circuit. Moreover, it illustrates the successfully implemented symmetric tunability of the barriers for both electron and hole injection. Such a representation is of particular importance considering circuits, due to the requirement of equal voltage levels of the gates as well as supply voltage. Importantly, investigating the temperature dependence of the transfer characteristics of the proposed SiGe RFETs revealed a stable device operation of both the n-and p-program for temperatures up to T = 400 K (see Figure S6, Supporting Information). Comparing the symmetry of the oncurrents of the n-and p-mode of our devices with state-of-theart Ge-based RFETs, which show symmetries between 10 and 100, [24,25] the proposed Al-Si-SiGe multi-heterojunction platform presented in this paper is a clear advancement. However, further improvements to the symmetry could be achieved using either a finer stoichiometric balance of the semiconductor channel, a gate-dielectric enhancing the n-mode such as ZrO 2 or strain engineering. [37] To complement the electrical characterization of the proposed SiGe RFET, Figure 2c and d show the output characteristic of www.advelectronicmat.de the n-and p-type mode operation respectively. For the n-type operation, we have modulated the drain current I D for positive V DS and positive V PG , while for the p-type operation, we have plotted the I D for negative V DS and negative V PG . In both operation modes, a nonlinear increase of the V CG -dependent current is observed for low V DS , which is a typical behavior of SBFETs, attributed to the bias-dependent change of barrier thickness and related tunneling transmissibility. [37,38] This effect has been attributed to the change in the shape of the tunneling barrier caused by the V PG to V DS potential difference actively affecting the tunneling probability. When V DS is rising, the width of this barrier is decreasing resulting in an exponential increase of the current due to an enhanced tunneling transmission.
As the barrier height for holes is lower compared to electrons, they can already tunnel with a high probability for comparatively low V DS resulting in an overall linear I/V characteristic of the p-mode of the RFET. The more negative V CG is, the more transmissible the barrier will be.
Although this work, for demonstration purposes, focuses on fairly large channel lengths, the proposed SiGe RFET concept should be physically scalable as recent device TCAD simulations of multi-gated Si and Ge transistors have shown. Remarkably, RFET operability down to a channel length of ≈50 nm with gate lengths and gate-spacings down to 10 nm was proven. [23] In this respect, the overlap between the PGs and the source/drain regions is critical, as a small overlap is necessary to achieve a low off-state and ensure small parasitic capacitances. [39,23,40] Therefore, we expect significantly enhanced key performance parameters of our SiGe RFET utilizing shorter channel lengths and thinner effective gate oxide thicknesses. For a convenient comparison of the key parameters of the proposed SiGe RFET with SiO 2 and HfO 2 gate dielectric, Table 1 provides the mean

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values of the ten best SiGe RFETs compared with Al-Si-based RFETs. In the case of the gate stack including the HfO 2 , again thermal oxidation (see Experimental Section) was used to partially oxidize the Si capping layer, which is supported by the EDX map and corresponding HRSTEM shown in Figure S4 (Supporting Information). We want to note that the EDX and HRTEM images are however not able to accurately resolve the boundary between SiO 2 and the remaining Si capping layer.
To further probe the usable operation regimes of the proposed SiGe RFETs, Figure 3 shows color maps of I D in dependence of V DS and V CG for both n-and p-type operation in the temperature regime between T = 295 and 400 K. The region of the n-and p-type on-states is indicated by the area below the white dashed lines. The high degree of symmetry with respect to the applied bias is a clear indication of highly similar injection capabilities of electrons and holes from both the source and drain contacts, thus highlighting the quality of the obtained Al-Si-Si 0.67 Ge 0.33 multi-heterojunction. Importantly, no significant charging or trapping effects could be noticed during the measurements, which manifests a high reproducibility of the obtained transport maps. The rise of the off-current with increasing temperature is ascribed to the thermally excited charge carriers surpassing the blocking barrier, according to thermionic emission. The subthreshold region can be further described by thermal field emission and a higher rate of injection of charge carriers through thermal-assisted tunneling. In contrast, the on-current is not significantly influenced at elevated temperatures as expected to occur by a highly transparent i.e. quasi-ohmic metal-semiconductor junction. [41,42,31] Importantly, an ambipolar operation is still well suppressed for both operation modes even up to T = 400 K. This is further supported by varying V PG with respect to V CG sweeps for temperatures between T = 295 K and T = 400 K (see Figure S8, Supporting Information). In agreement with thermionic emission theory, the I/V curves in the subthreshold region are flattened with increased temperature, which can also be observed in the temperature-dependent transfer characteristic seen in Figure S6 (Supporting Information). Interestingly, a slight but reproducible current decrease was found for both operation modes for increasing temperatures. Thus, it is evident that highly transparent junctions for both electrons and holes are obtained, [35,31] indicating that scattering is the main contribution to the resistance at elevated temperatures in the on-state. This observation is a further indication of tunneling through a thin barrier, which is determining the transport, rather than thermionic emission. [31] Such highly transparent junctions are only seldomly observed in Schottky contacts with intrinsic or lowly doped semiconductors, for example, in carbon nanotubes with high work-function Pd contacts [43,44] or for the efficient use of thin Si 3 N 4 interface layers to Si with Fermi-level depinning properties. [45,46] Importantly, the fact that the proposed SiGebased RFET shows stable unipolar n-and p-type operation up to temperatures of T = 400 K implies that static n-and p-type FETs as conventionally used in a CMOS circuit can be replaced, principally enabling deliberate logic functions in a complementary design. [47] Importantly, extending complementary designs, www.advelectronicmat.de the proposed RFET technology supports the realization of wired logic connections such as wired-AND gates, where the logic output is defined by the current flow through the channel of the device. Thereto, the CG is split into several independent gates to turn the RFET off except when all inputs are on. [48,20,49] A realization of a three-input wired-AND can be seen in Figure  S7 (Supporting Information). Compared to an RFET device without a Si 0.67 Ge 0.33 layer, an approximately one order of magnitude higher drive-current could be realized, which is particularly interesting for series interconnections and the above-mentioned wired-AND topology.
Finally, we focus on the gate-and bias-voltage-dependent activation energy of the proposed Al-Si-Si 0.67 Ge 0.33 junction of the presented SiGe-based RFET. In the chosen approach, the activation energy of the entire I D has been extracted via Richardson plots as explained below. Note that the exact Schottky barrier heights of the contacts can only be approximated in specific bias conditions, but the different operation regimes can nevertheless be identified and compared to each other. For a more quantitatively accurate model for the extraction of Schottky barrier heights in Schottky FETs refer to the recent work of A. Pacheco et al. [50] Figure 4 shows the respective activation energy maps obtained from temperature-dependent I/V maps of the n-and p-operation mode extracted from temperature-dependent I/V measurements recorded between T = 295 and 400 K.
The evaluation is based on the theoretical assumptions for the experimental activation energy extraction described in the work "Metal-Semiconductor Contacts" by E.H. Rhoderick and R.H. Williams. [51] Here it needs to be considered that the I/V(-T) approach, which relies on thermionic emission theory, is applied. In general, this theory is valid for barrier heights larger than k B T (25.7 meV at T = 300 K) and small bias voltages to avoid barrier lowering, and thus significant tunneling currents. Nevertheless, the contribution of tunneling to the total current plays an important role in the scope of this work. Hence, experimental investigations do not allow for differentiation between thermionic and tunneling contributions to the total current. Moreover, this experimental approximation neglects the potential between the metal and semiconductor and thus leads to a simplified equation. According to E.H. Rhoderick and R.H. Williams, the current through the Schottky barrier can be simplified when the applied bias voltage exceeds 3k B T/q (76 mV at T = 300 K). Equation (1) gives the simplified equation based on thermionic emission theory for the evaluation of the total effective activation energy. Note that previously published works promote this model for determining the total effective activation energy. [52,53] where J TE is the measured current density through the device, A * is the effective Richardson constant, T is the corresponding temperature and qφ eSBH is the total effective activation energy. Thus, the total effective activation energy can be extracted by measuring the I/V-characteristic at different temperatures and applying the natural logarithm to extract the barrier height of the previous equation (see Figure S9a, Supporting Information). Finally, Equation (2) shows the obtained expression.
Thus, by plotting ln 2 J T TE (y-axis) as a function of 1000/T (xaxis), a so-called Richardson plot is obtained. Using the linear equation and setting the factors of the above equation correspondingly to y = kx + d, the individual parameters can be extracted. Analyzing the slope k, the corresponding qφ eSBH can be determined for a specific bias voltage V DS as depicted in Equation (3). An example of the Richardson plot is shown in the supporting information ( Figure S9b, Supporting Information).
where k is the evaluated slope of the Richardson plot. Finally, qφ eSBH can be plotted over V DS for the evaluation of the total effective activation energy. Therefore, values for each V DS and V CG do exist, which are then used for the data representation in Figure 4. An exemplary plot explaining the procedure is shown in the supporting information ( Figure S9c, Supporting Information). Remarkably, such activation maps allow deducing more reliable and resilient interpretations of the charge carrier transport mechanisms of RFETs compared to the values obtained at single operation points. [54] The activation energy map as a function of V DS and V CG for n-type operation mode is shown in Figure 4a, depicting two explicit regions with www.advelectronicmat.de different activation energies E a separated by a narrow regime at ≈250 meV. First, the region from V CG = 1 to 5 V is considered, which indicates highly transparent contacts for electron injection (i.e., with E a ≈ 0 eV or even negative values), which can be attributed to efficient electron injection. As no strong V CG -dependent gradient is observable, the injection capabilities remain stable in this regime. Sweeping V CG from 1 to −5 V, positive activation energy E a values are obtained, indicating an explicit barrier to inject holes, which proves the capability of the proposed SiGe RFET to efficiently block the undesired charge carrier type. Moreover, a dedicated high barrier is measured between a V CG from 0 V to −2 V, with a peak at V DS = 0 V. This can be attributed to reduced band bending initiated by the source/drain as well as CG potential. Figure 4b shows the equivalent map of the p-type operation mode, indicating a similar behavior. However, due to the incorporation of Ge, the Fermi-level might be slightly offset closer to the valence band, supporting a more efficient injection of holes, [28] observed at V CG < 1 V. Remarkably, the three-top-gate RFET architecture still features a sufficient blocking of source-drain junction leakage (here: electrons) limiting static power dissipation in the positive V CG regime. Again, due to reduced band bending initiated by the source/drain potential, a higher barrier is evident around V DS = 0 V. A more detailed discussion of the underlying transport mechanisms of three top-gated RFETs can be found in the Supporting Information.

Conclusion
In conclusion, we have shown the fabrication, structural investigation and in-depth transport analysis of RFETs based on a vertical Si-Si 0.67 Ge 0.33 channel monolithically integrated with single-elementary crystalline Al contacts formed from a thermally induced Al-SiGe exchange reaction. The chosen Si 0.67 Ge 0.33 stoichiometry and the dedicated Al junctions with thin Si interlayers provide an ideal material system to reach symmetric IV operability in RFETs. To further enhance the device's subthreshold behavior three independent-gate regions were applied. Despite the significant Ge content, efficient suppression of source-drain leakage has been achieved. To set the performance of the proposed SiGe RFET into perspective, a detailed comparison with Si RFETs based on the same SOI substrate and equal Al contact technology was conducted. Despite a slightly smaller on-current symmetry, the current densities, subthreshold slopes and threshold voltages could be significantly improved with the presented Si 0.67 Ge 0.33 RFET. To counteract the commonly known trapping-related instability of Ge-based channels, integration of a HfO 2 gate dielectric with a SiO 2 interlayer provided a stable and hysteresis-free operation even at elevated temperatures. Additionally, this gate stack improved subthreshold slopes and threshold voltages. The combined features and systematically engineered material and interface properties of the reported Al-Si-Si 0.67 Ge 0.33 multi-heterojunction-based SiGe RFETs are an ideal prototyping platform to enable the design of high-performance adaptive circuits, targeting an increase of logic functions per chip for future energyefficient systems as well as for applications reaching beyond the CMOS capabilities, for example for integrated hardware security circuits.

Experimental Section
Epitaxial Growth of Si 0.67 Ge 0.33 on SOI: For the growth of the Si 0.67 Ge 0.33 on SOI, recent growth strategies were adapted for the successful formation of Ge-rich but pseudomorphic 2D films with low surface roughness deposited on bulk Si substrates. [32,55] The layers were grown in a Riber SIVA-45 MBE system on SOI in (100) orientation. The BOX and device layer thickness for the SOI was 100 nm / 20 nm, respectively. After a standard substrate cleaning process, the substrates were dipped in hydrofluoric acid (HF 1%) to remove the native oxide before their introduction into the MBE chamber. The substrates were degassed at 973 K for 20 min. The SOI substrate was covered by a 10 nm Si buffer layer (T G ramped from 723 to 823 K), an 8 nm thick Si 0.67 Ge 0.33 layer, and a 3 nm thick Si capping layer, both deposited at T G = 623 K.
Device Fabrication: The Si 0.67 Ge 0.33 on SOI was patterned using laser lithography and SF 6 -O 2 -based reactive ion etching. As gate dielectric, either a 6 nm thick SiO 2 obtained through thermal dry oxidation at T = 1174 K for 3 min or a combination of thermal oxidation at T = 1174 K for 1 min to partially oxidize the Si capping layer obtaining a 2.5 nm thin SiO 2 interface dielectric and a 7.5 nm thick ALD grown HfO 2 layer was used. The ALD process was carried out using TEMAHf and H 2 O as precursors, with N 2 as the carrier gas, while keeping the reactor at a temperature of T = 524 K. Al pads contacting the obtained nanosheets were fabricated by laser lithography, 125 nm Al sputter deposition, preceded by a 20 s BHF dip (7:1) to remove the SiO 2 at the Al-Si 0.67 Ge 0.33 contact area and lift-off techniques. An SF 6 -Ar-based reactive ion etching process was used to remove the HfO 2 at the contact area. For source/ drain formation, an Al-SiGe exchange reaction was induced by RTA at a temperature of T = 774 K in forming gas atmosphere. Π-shaped Ti/Au top gates were fabricated atop the proposed heterostructures, using a combination of electron beam lithography, Ti/Au evaporation (10 nm Ti, 100 nm Au), and lift-off techniques.
TEM Measurements: TEM lamella preparation was performed using a Tescan Lyra FIB/SEM. The TEM images were acquired using a Thermo Fisher Scientific Titan Themis 200 G3 outfitted with a SuperX detector used for the EDX maps.
Electrical Measurements: The electrical measurements as well as the temperature-dependent measurements were performed using a LakeShore PS-100 cryogenic probe station and a Keysight B1500A semiconductor analyzer. Considering the symmetric operation of the device, V D was set, and consequently V S = −V D . Hence, throughout the manuscript, V DS was used to declare the applied bias voltage.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.