Biosignal Amplifiers Based on Low‐Noise Organic Transistors with Printed Electrodes

The monitoring of microvolt‐level biosignals such as electroencephalograms requires the application of low‐noise signal amplifier circuits, which, for single‐use cases, must be fabricated for disposability using low‐cost manufacturing techniques. One promising solution for the production of low‐cost amplifier circuits for digital biosensing is the emerging technology of low‐noise printed circuits. Here, a low‐noise‐electrode printing process for organic transistors that can carry out precision measurement of brain activity using a low‐noise organic amplifier is proposed. In the transistor fabrication process, Ag electrodes are processed via flat stamp parallel printing, and fine‐process optimization to minimize the charge‐trapping effect enables a three‐order reduction in transistor noise. The low‐noise transistors are used to produce an organic pseudo‐complementary metal‐oxide‐semiconductor amplifier with a small noise level of 2.2 µVp‐p at 10 Hz, which enables precision brain wave monitoring in a close correlation with signals obtained using a commercialized measurement system.


Introduction
Wearable biosensing equipment is a highly anticipated nextgeneration medical device technology for obtaining advanced personal healthcare and self-medication. A critical requirement for a wearable device is that it does not interfere with daily human activity, which means that it must be mechanically flexible and lightweight. Furthermore, to avoid motioninduced artificial noise and obtain higher-quality biosignals, the sensor device must remain in close contact with the surface of the human body. To meet these requirements, a number of www.advelectronicmat. de In this paper, we demonstrate a low-noise printing process that minimizes transistor noise by optimizing the OTFT electrode stacking process. The device employs a bottom-contact, top-gate transistor structure in which source-drain silver electrodes are printed using the flat stamp parallel printing (FSPP) method, a type of reverse offset printing method that enables both the patterning of fine source-drain electrodes and a large-area biopotential input electrode. In this study, we focused on the junction between organic semiconductors and source-drain electrodes, and conducted a fundamental study using glass substrates. In the design process, process improvements such as thinning the contact electrodes and insulator film and optimizing the chemical treatment process for the contact electrodes were tested to evaluate their respective impacts on transistor noise. This process optimization resulted in improved mobility, reduced contact resistance, and reduced subthreshold slope and enabled the fabrication of a low-noise, 2.3 × 10 -11 Hz −1 OTFT with improved transistor characteristics. Using the low-noise OTFTs, a pseudocomplementary metal-oxide-semiconductor (CMOS) amplifier with an ultra-low output noise of 2.2 µV p-p at 10 Hz was fabricated.
The EEG signal is a microvolt-level biopotential signal and can only be successfully measured using a low-noise amplifier circuit; accordingly, the printed-electrode low-noise organic amplifier was tested to determine whether it was capable of EEG measurement. EEG signal analysis clarified that the amplified signal obtained by the low-noise amplifier was closely correlated with the signal obtained using a commercial EEG measurement system and that its characteristic alpha wave under the closed-eye condition could be measured accurately, confirming that the EEG signal was amplified correctly.

Fabrication of Printed Electrodes
We fabricated the OTFT electrodes using the FSPP method, a type of reverse offset printing. The FSPP fabrication process involves five steps ( Figure 1A): i) coating ink containing metal nanoparticles (NPs) onto a flat silicone blanket through a slit nozzle, ii) pressing the blanket to a flat glass printing plate for adhesion, iii) peeling the printing plate from the blanket, iv) pressing the blanket to a target substrate, and v) peeling the substrate from the blanket. The desired blanket pattern is obtained through processes (i)-(iii), and transcription of the pattern is achieved by performing processes (iv) and (v). The printing process is performed at room temperature (typ. 25 °C). Following the printing process, the NP ink pattern is sintered in an oven at 100-120°C until it becomes electrically conductive (< 25 µΩcm). In this study, although the electrodes are printed on glass substrates, as the entire FSPP process is performed at below 150 °C, it can be used to print patterns onto plastic films such as the polyimide films as demonstrated in Figure 1B.
Three features differentiate FSPP from other methods. First, FSPP can make both fine and large patterns, such as electrode arrays and pad electrodes, simultaneously, as shown in Figure 1C. This feature provides an advantage relative to other printing methods such as ink-jet printing by reducing the time needed to produce a pattern of a given size. Second, FSPP enables very fine patterning into thin, flat structures with minimal spatial and linear fluctuation even at short line widths. Figure 1D,E shows, respectively, an optical microscopic image of electrodes printed via FSPP (line/space = 15 µm/5 µm) and a cross-sectional profile of the electrodes obtained using atomic force microscopy. The edge-line fluctuation of the electrode is less than 0.1 µm, enabling the minimum line width and space of 2.5 µm and 2 µm, respectively.

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Ink coating into the flat blanket in step (v) enables high reproducibility of the electrode thickness, sample-to-sample variation of which is ≈5% in a standard deviation. It is difficult to obtain a fine pattern such as that shown in Figure 1D using an ink-jet process, in which the volume decreases in ink ejection needed to make a fine pattern causing edge-line fluctuation, while ink ejection at short intervals consumes additional time and increases the electrode thickness. [15] By contrast, FSPPprinted electrodes have minimal linear and spatial fluctuation, making the device fabrication process reproducible. In addition, FSPP-printed electrodes are sufficiently thin and flat, which do not affect the upper layer of a multilayered structure. Finally, FSPP enables a very high overlay accuracy of ±2 µm in a multistacking process. An alignment of the pattern is conducted by superimposing the designed marks of both the substrate and the blanket prior to the pressing in step (iv). In standard offset printing, camera movement for focusing both alignment marks causes accidental misalignment. By contrast, a very short distance between the substrate and the blanket, owing to the use of a flat blanket in place of the standard roll blanket, enables fine alignment. The proposed process uses this feature to enable the printing of 200-dpi flexible electrophoretic displays. [16]

Process Improvement for Low-Noise Organic Thin-Film Transistors
Although there have been many studies to date on the fabrication of OTFTs using printed electrodes, there is no report addressing the issue of noise. Some reports have suggested that the noise produced in an OTFT without printed electrodes is related to the presence of carrier traps in the semiconducting layer or to contact resistance. [12,17,18] As the interface properties are important regardless of the fabrication process, it is necessary to focus on the cross-sectional structure of the electrodes and the metal-organic interface properties to optimize the device fabrication process. In this study, we assessed the following three approaches for reducing noise in OTFTs: suppression of morphological fluctuation in the semiconducting layer using thin-film source-drain (SD) electrodes, decreasing the carrier-trap effect using a thin insulator layer, and improving the metal-organic interface properties by optimizing the process of chemical modification. Figure 2A shows a cross-sectional diagram of a fabricated OTFT. We coated a primer layer onto a glass substrate to enable electrode adhesion. The SD electrodes were fabricated by FSPP and then immersed into a 2-propanol solution of www.advelectronicmat.de pentafluorobenzenethiol (PFBT) for 30 min at room temperature (typ. 25 °C). A 30-nm semiconducting layer of dinaphtho[2,3-b:2″,3″-f ]thieno[3,2-b]thiophene (DNTT) was then deposited via physical vapor deposition, followed by deposition of parylene to obtain a 100-nm insulating layer. Finally, a 50 nm gold electrode was deposited to fabricate a gate electrode.
The transfer characteristics of the fabricated OTFTs at a −5 V drain bias were measured ( Figure 2B); the intrinsic mobility, contact resistance, subthreshold slope, and hysteresis characteristics are listed in Table S1, Supporting Information. The intrinsic mobility and contact resistance were analyzed using the transfer line method. [19] Figure 2B shows the characteristics of an OTFT with a 100 nm SD electrode (device A). Decreasing the thickness of the SD electrodes to 50 nm resulted in an increase in drain current (B in Figure 2B). Figure 2C,D show cross-sectional images taken by scanning transmission electron microscopy of devices A and B, respectively. In both devices, part of the SD electrode edge is buried in the primer layer, making the semiconducting layer smoother. The thinning of the SD electrodes in device B further enhanced the smoothness of the semiconducting layer, nearly halving the contact resistance and enhancing the field-effect mobility (µ L5 ) of the short channel device (Table S1, Supporting Information). [20] In device C, the thickness of the insulator is reduced from 100 to 40 nm, resulting in a doubling of the mobile carrier quantity and a decrease in the ratio of trap to overall carriers. This, in turn, decreased contact resistance and hysteresis and improved the mobility by ≈70%.
Device D was fabricated at altered PFBT process temperatures, resulting in a further 30% decrease in contact resistance at a PFBT solution temperature of 40 °C. To verify the effect of this improved PFBT process, we analyzed the surface of the electrodes before and after processing using X-ray photoelectron spectroscopy ( Figure S1, Supporting Information). It was found that, following the PFBT process, the abundance ratios of ink additive and silicone residue on the Ag electrode decreased while the Ag and PFBT signals increased. These effects were enhanced as the PFBT process temperature was increased. These results suggest that increasing the temperature during the PFBT process results in an ideal metal-organic interface without unexpected residue, resulting in turn in an additional decrease in the contact resistance. Figure 2E shows the noise measurement results for each fabricated OTFT (the measurement setup is shown in Figure S2, Supporting Information). It is apparent that the noise decreases significantly as the process improves. For the preoptimized device (A), the noise power density of noise at 10 Hz normalized by drain current is 1.4 × 10 −8 Hz −1 , while for the optimized device (D) it is 2.3 × 10 −11 Hz −1 , a three-ordersof-magnitude improvement. The noise levels produced by the fabricated OTFTs are low compared to those achieved in past studies. [14,18,21] As mentioned above, the reductions in carrier traps and contact resistance likely reduce the transistor noise. Our process improvements result in smoothing of the semiconducting layer to reduce the amount of disorder in the semiconductor, which in turn reduces the number of carrier traps. As a result, the intrinsic mobility improves. The effect of the carrier traps is also suppressed by decreasing the thickness of the insulator. In addition, the fabrication of an ideal metal-organic interface reduces the contact resistance. The effects of these three types of process improvement are also observable in the actual parameters such as intrinsic mobility, contact resistance, subthreshold slope, and hysteresis.
While previous studies investigated the noise effects of the crystallinity of the organic layer, [12,13] insulator surface properties, [22] and electrode materials, [23] this study focused on the overall process, including the printing of the electrodes. We found that the structure of the printed electrodes and the additive and residue derived from printing process significantly affected both the transistor characteristics and the noise properties, indicating that it is necessary to optimize the conditions specific to the printed electrode to realize the reduction of transistor noise.

Low-Noise Printed Pseudo-CMOS Amplifier
The low-noise OTFTs were applied to an analog circuit to detect ultra-low amplitude signals. A photograph and circuit diagram of the fabricated pseudo-CMOS amplifier with printed-electrode OTFTs are shown in Figure 3A,B, respectively. The pseudo-CMOS circuit has the advantages of comprising only p-type OTFTs, with no n-type OTFTs, and having a high amplification gain capability and a low-noise potential owing to its low circuit current. [24] Pseudo-CMOS amplifiers have previously been used for the amplification of biosignals, [7] which is also suitable for obtaining our target signals. In the experiments, the printed pseudo-CMOS circuit was operated by a 5 V power supply. We obtained a trip point of 4.70 V and a static gain of 49 from the input-output characteristics ( Figure S3A, Supporting Information). The hysteresis of the trip point was less than those of printed-electrode inverter circuits used in previous studies. [25] The circuit was operated as an amplifier using a feedback resistance of 20 MΩ and an input capacitance of 47 nF ( Figure 3B). Figure 3C shows the output transient response obtained from inputting a 1 mV signal at 10 Hz, which found that the output signal is an inverted phase of the input signal amplified by a factor of 18. The output signal was measured for 10 s to obtain an amplitude spectral density via fast Fourier transform (FFT), as shown in Figure 3D. We defined the ratio of the peak to the base noise amplitudes at a given frequency as the signal-to-noise ratio (SNR). We note that a pseudo-CMOS amplifier comprises two stages, in which the transistor noise is also amplified by itself. Thus, it is insufficient to discuss the noise level, and the analysis of SNR, which is the noise normalized by the gain, is necessary in the fundamental investigation of pseudo-CMOS amplifier characteristics. More discussion of the frequency response of the gain and SNR is given in the Supplementary Information (Note S1 and Figures S3B, S3C, Supporting Information).
We then investigated the amplification potential of the printed amplifier. Figure 4 plots the output SNR (vertical axis) against the input signal amplitude (horizontal axis) for four devices (amplifiers A-D) with different transistor noises, which were fabricated under the same conditions as devices A-D discussed in the transistor noise section (see Figure 2). All experimental values used to produce the results in Figure 4 are listed in Table S2, Supporting Information. In theory, a circuit will www.advelectronicmat.de only function as an effective amplifier if its SNR is greater than one; therefore, we obtained the amplification limit from the x-value of the point at which the SNR of the linear fit was equal to one. The amplification limit of amplifier A, which had the highest-noise transistor, was 7.3 µV p-p , while that of amplifier D, which had the lowest-noise transistor, was 2.2 µV p-p , indicating that a noise-optimized amplifier can detect and amplify very small signals of at least 2.2 µV p-p . We further investigated the amplification characteristics by inputting an actual small signal (10 µV) to the printed amplifiers (Table S2, Supporting Information), and found that, although the output signals of amplifiers A and B were completely buried in noise, amplifiers C and D successfully detected and amplified the 10-µV input signal.

Demonstration of EEG Measurement
To demonstrate the usefulness of a printed amplifier capable of detecting an ultra-small signal of a few µV, we carried out several EEG measurements. Figure 5A shows a photograph of the device used for EEG measurement, in which the source, drain, and gate electrodes and the bioelectrode used to detect brain signal were all printed by FSPP. Figure 5B shows a schematic of the EEG measurement setup. To validate the measurements,   Figure 3). Input signals with amplitudes varying from 1 mV p-p to 10 µV p-p are applied to the amplifiers. Broken lines show linear approximation.

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we compared the signals detected by the printed amplifier to those obtained using a commercially-available EEG measurement system (AD instruments: PowerLab 26/4 with DualBi-oAmp FE232). The measurements were obtained from human subjects using a plate electrode attached to one earlobe and a bioelectrode attached to the forehead as the circuit ground and signal source, respectively. The details of the setup and the measurement system used to measure direct signals from the bioelectrode and the output signals from the printed amplifier are shown in Figure S4, Supporting Information. Figure 5C shows the results of a series of 2-s EEG measurements taken with the eyes closed. A periodic signal of ≈10 Hz contained in the direct signal (blue line) was amplified by the printed amplifier by a factor of ≈20 as seen in an output signal (red line), indicating that the printed amplifier is applicable to a real biosignal. We obtained a correlation coefficient of 0.7 between the direct and amplified signals, indicating that the magnitudes of the amplified signals nearly perfectly reflected those of the original signals. EEG signals obtained with the eyes opened and blinking ( Figure 5D) revealed a lack of the periodic signal detected in the closed-eyes experiments in Figure 5C. Typically, the brain signal at 9-12 Hz, or so-called alpha wave, is induced by closing the eyes and disappears when the eyes are opened, confirming that the printed amplifier detected a real brain signal. The large signals during blinking corresponded to electro-oculogram (EOG) signals induced by eye movement that were detectable because of the proximity of the bioelectrodes to the eyes. We also measured continuous brain signals over periods of ≈1 min and compared the amplitudes of the spectrograms of the direct ( Figure 5E) and amplified signals ( Figure 5F); the results also revealed EOG signals, alpha waves, and signal disappearance during blinking, eye closure, and eye opening, respectively. The spectrograms were in close agreement over the entire measurement period. Overall, the results above indicate that we achieved precise measurement of an ultra-small brain signal of ≈10 µV p-p using our lownoise printed amplifier.

Conclusion
We investigated the effects on the noise properties of printedelectrode OTFTs. Use of the FSPP process enabled us to reduce the thickness of the SD electrodes to 50 nm. A detailed www.advelectronicmat.de cross-sectional electron microscopy investigation revealed enhanced smoothness in the semiconducting layer, which led to the reduction of carrier traps in the semiconducting layer. The reduced thickness of the insulator further suppressed the effect of the carrier traps. By optimizing the PFBT process used on the printed SD electrodes, the amount of ink additive and silicone residue could be reduced. Using these process adjustments, we successfully reduced the noise of the printed OTFT to 2.3 × 10 −11 Hz −1 and used printed OTFTs to fabricate a low-noise pseudo-CMOS amplifier with the ability to detect and amplify a 10-µV p-p signal at 10 Hz. The low-noise printed amplifier clearly amplified alpha waves, a standard EEG signal induced by closing the eyes. This is the first comparison between the noise properties of a single transistor and a pseudo-CMOS amplifier and the first demonstration of EEG measurement using an integrated amplifier based on printed electrodes.
In this study, the FSPP printing process has replaced the formation of the source-drain electrode in the transistor circuits. Only the device used for EEG measurement has the printed electrode realized by FSPP printing including top-gate electrodes. This is a preliminary step toward realizing all stacking layers of circuits by printing methods. In fact, there are still issues that must be optimized to realize transistor circuits with FSPP printing, including the fabrication of top-gate electrodes. Specifically, the filling method for vertical via holes to connect multiple transistors and process optimization to ensure the circuit yield. However, our findings clearly indicate the low-cost printing technique with fine-process optimization enables the fabrication of low-noise amplifiers as well as transistors, which is a necessary step for realizing cost-effective ultra-small biosignal monitoring.

Experimental Section
Design of OTFTs and Pseudo-CMOS Amplifiers: A primer layer (thickness: ≈100 nm) was formed by spin-coating a Primer A solution (Bando Chemical Industries) onto a glass substrate and annealing it at 120°C for 30 min in ambient air. Patterning of the source and drain electrodes was performed via an FSPP process using 15 wt.% Ag ink (FlowMetal SR7021: Bando Chemical Industries) followed by sintering at 120 °C for 30 min in ambient air. The thicknesses of the electrodes (100 or 50 nm, depending on the sample, N = 39) were checked using a stylus-type profilemeter (Dektak 8: Bruker) and coherent scanning interferometry (VS1330: Hitachi High-Technologies). The microscopic surface roughness of the sintered electrodes is 3-4 nm measured by atomic force microscopy (Dimension Icon: Bruker). The PFBT process was performed by immersing the electrodes into a 10-mM 2-propanol (IPA) solution of pentafluorobenzenethiol (PFBT, Tokyo Chemical Industry) for 30 min. The electrodes were rinsed with IPA following the PFBT process. A 30 nm semiconducting layer of DNTT was deposited via physical vapor deposition at a rate of 0.3 Å s −1 in a vacuum condition (<5 × 10 −3 Pa). A parylene gate dielectric layer (diX-SR, KISCO) was fabricated by a vapor deposition system (Specialty Coating Systems: Labcoater), and its thickness was identified by measuring the capacitance using an LCR meter (Agilent E4980A). A 50-nm-thick Au gate electrode was fabricated by physical vapor deposition at a rate of 3 Å s −1 in a vacuum condition (<10 −3 Pa). For EEG measurements, a 170-nm-thick Ag gate electrode was fabricated in place of the Au electrode via FSPP, with the electrode sintering performed at 100 °C for 30 min in ambient air.
Cross-Sectional Imaging via Scanning Transmission Electron Microscopy (STEM): Cross-sectional images of the OTFT devices with 50-and 100-nm-thick SD electrodes were obtained via a focused ion beam process and using STEM equipment (Hitachi High-Technologies S-5500).

X-Ray Photoelectron Spectroscopy of the Surfaces of the Printed Ag
Electrodes: Three types of measurement samples were prepared: FSPPprinted Ag electrodes that were as-sintered (w/o PFBT), immersed in an IPA solution of PFBT in a 5 °C refrigerator for 30 min (w/PFBT 5 °C), and immersed in an IPA solution of PFBT that was heated to 40 °C using a hot plate (w/PFBT 40 °C). X-ray photoelectron spectroscopy measurement was performed using a PHI Quantera II with a monochromatic X-ray source (Al Kα).
Measurement of OTFT Properties and Noise: The OTFTs used for the measurements had a common channel width (W) of 500 µm and channel lengths (L) of 200, 100, 50, 20, 10, 5, and 3 µm, respectively, and were fabricated in the same processing lot. The transfer and output characteristics were measured using a semiconductor device analyzer (Keysight Technologies B1500A). The experimental circuit for transistor noise measurement (L = 5 µm) is shown in Figure S2, Supporting Information. The transistor noise current SiN was obtained by dividing the voltage noise across the resistor by R 2 . Voltage noise was measured using a homemade data logging system with a 24-bit analogto-digital converter (ADC). The sampling frequency used to obtain noise measurements was 250 Hz, and the gate and drain biases were −2.45 V and −0.5 V, respectively. The noise current signal and dc current were measured for 10 s, followed by a fast Fourier transform (FFT) and smoothing using a Savitzky-Golay filter to obtain the noise spectra.
Measurement of Pseudo-CMOS Properties and SNR: In the OTFTs comprising the pseudo-CMOS amplifier, all electrodes had 5-µm-gap channel lengths, and a designed Tr1-Tr4 channel width ratio of 1:3:3:3. Input-output characteristics ( Figure S3A, Supporting Information) were measured using a semiconductor device analyzer (Keysight Technologies B1500A). A power source (Keysight Technologies B2962A) was used to generate input signals for SNR measurement. The printed amplifier was driven by a 2.45 V power supply. The output signal from the printed amplifier was measured for 10 s using a homemade data logging system with a 24-bit ADC, followed by FFT calculation to transform the signal into the power spectrum. The background noise floor of the printed amplifier was obtained by smoothing the spectrum using a Savitzky-Golay filter with the input terminal shorted to 0 V ( Figure S3C, Supporting Information). The SNR was calculated from the peak magnitude of each amplitude spectrum divided by the background noise value in the smoothed spectrum at the input-signal frequency.
Demonstration of EEG Measurement: All experiments on human measurements comply with the Osaka University Research Ethics Committee guidelines. The experimental setup used to demonstrate EEG measurement is shown in Figure S4. The measurements were obtained from three healthy volunteers (30-38 years of age; 2 male), among which the clearest result was discussed above. The plate and printed electrodes were attached to the earlobe and forehead, respectively, using conductive paste (Ten 20: Weaver). The conductive paste is an adhesive gel-like paste that electrically connects the forehead and the printed bioelectrode on the glass substrate. Additionally, a rubber hair band was used to tightly attach the conductive paste on the forehead. The pseudo-CMOS printed-electrode amplifier was driven by an alkaline coin battery (LR44 1.5 V). In the amplifier circuit shown in Figure 3B, a 20 MΩ chip resistor and a 47-nF chip capacitor-indicated by R and C, respectivelyare used as circuit discrete. The direct EEG and printed amplifier signals were measured using a PowerLab 26/4 through a DualBioAmp FE232 (AD Instruments), which together constitute a commercially available measurement system. As the DC voltage of the amplified signals exceeded the input voltage limit of the measurement system, the amplified signal was measured through a voltage follower and a highpass filter (cut-off frequency: 0.68 Hz). The sensitivity of DualBioAmp was 16-bit at the ±20 mV input range; as the input range of PowerLab is ±2 V, the DualBioAmp operated as a 100× amplifier.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.