Cryogenic Storage Memory with High‐Speed, Low‐Power, and Long‐Retention Performance

Cryogenic‐computing draws attention due to its variety of applications such as cloud‐computing, aerospace electronics, and quantum computing. Low temperature (e.g., 77 K) enables higher switching speed, improved reliability, and suppressed noise. Although cryogenic dynamic random‐access memory is studied, the cryogenic NAND flash is not explored intensively. Herein, a cryogenic storage memory based on the charge‐trap mechanism is reported. By removing the tunneling oxide from the conventional silicon/oxide/nitride/oxide/silicon (SONOS)‐type flash memory (therefore becoming silicon/oxide/nitride/silicon (SONS)), high‐speed and low‐power operation is aimed to be achieved while relieved from poor retention issue thanks to the cryogenic environment. The FinFET‐structured SONS memory device is demonstrated experimentally with gate length of 20–30 nm, which can achieve the retention issue (>10 years) with low voltage (≈6.5 V) and high speed (≈5 µs) operation at 77 K. To have a holistic system‐level evaluation, benchmark simulation of an interface between a host microprocessor and solid‐state‐drive is conducted, considering the refrigerator cooling cost and the heat loss via cables across two temperatures (300 and 77 K). The results show that the SONS‐type cryogenic storage system shows over 81% improvement in both latency and power, compared to the SONOS counterpart located at cryogenics.


Device Characteristics of SONS CELL at RT
The detailed fabrication process flow of SONS device is explained in the Experimental Section.
This section demonstrates the electrical characteristics of the SONS cell at RT. The typical transfer (I D -V G ) and output characteristics (I D -V D ) of the SONS FinFET are plotted in Figure 3.
V G was swept from −1 to 1 V and −5 to 5 V in the I D -V G curves at V D = 0.5 V, where the former does not show noticeable memory window (MW) and the latter shows the MW of ≈0.91 V. In the Cryogenic-computing draws attention due to its variety of applications such as cloud-computing, aerospace electronics, and quantum computing. Low temperature (e.g., 77 K) enables higher switching speed, improved reliability, and suppressed noise. Although cryogenic dynamic random-access memory is studied, the cryogenic NAND flash is not explored intensively. Herein, a cryogenic storage memory based on the charge-trap mechanism is reported. By removing the tunneling oxide from the conventional silicon/oxide/nitride/ oxide/silicon (SONOS)-type flash memory (therefore becoming silicon/oxide/ nitride/silicon (SONS)), high-speed and low-power operation is aimed to be achieved while relieved from poor retention issue thanks to the cryogenic environment. The FinFET-structured SONS memory device is demonstrated experimentally with gate length of 20-30 nm, which can achieve the retention issue (>10 years) with low voltage (≈6.5 V) and high speed (≈5 µs) operation at 77 K. To have a holistic system-level evaluation, benchmark simulation of an interface between a host microprocessor and solid-state-drive is conducted, considering the refrigerator cooling cost and the heat loss via cables across two temperatures (300 and 77 K). The results show that the SONStype cryogenic storage system shows over 81% improvement in both latency and power, compared to the SONOS counterpart located at cryogenics.

Introduction
At cryogenic temperature, many advantages are achieved for integrated circuits such as the higher switching speed, improved reliability, suppressed noise levels as shown in I D -V D curve at the V G of 1 V, the output resistance of the SONS FinFET (r o ) was extracted for the later simulation. The impact of gate length (L G ) and channel width (W fin ) on the threshold voltage (V T ) and subthreshold slope (SS) are shown in the Supporting Information. V T and on, off current (I ON , I OFF ) are displayed with respect to the write voltages (V write ) in Figure 4a,b and pulse width (t pulse ) in Figure 4c,d. The V write was ranged from 4.5 to 6.5 V and the t pulse was varied from 200 to 5 µs.
Here, the I ON and I OFF were extracted at V G = (high V T +low V T )/2. Two wake-up pulses of ±6.5 V, 500 µs were applied prior   www.advelectronicmat.de to pretesting for stable operations due to increased trap densities. At V write = 6.5 V with t pulse of 1 µs, a ratio of I ON to I OFF (I ON /I OFF ) is larger than 20. At t pulse of 5 µs, the MW and the I ON /I OFF were ≈0.4 V and 200, respectively. Note that both the V write of 4.5-6.5 V and the t pulse of a few µs in the SONS structure are much smaller compared to the V write of >10 V and t pulse of a few hundred µs in the SONOS structure. [9] This improved feature is attributed to the absence of tunneling oxide in the proposed SONS structure.

Device Characteristics of SONS Cell at 77 K
The I D -V G and I D -V D curves at 77 K are displayed in Figure 5.
Like an RT case, the V G sweep of ±5 V makes the MW of 0.75 V, whereas that of ±1 V results in negligible MW. The two pulses were applied in 77 K prior to exploring the effect of V write , t pulse on V T , and I ON /I OFF in Figure 6. As shown in Figure 6, the MW at 77 K is comparable to that at the RT, but the I ON /I OFF is

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≈10to 100-fold larger at 77 K than at RT due to the steep SS. This feature allows a larger sensing window and is attractive for further device down-sizing. Figure 7a,b compares cycling endurance characteristics between RT and 77 K for V write = ±6.5 V with t pulse = 1 µs. In Figure 7a, the crossover that the low V T exceeds the initial high V T for 77 K occurs approximately at 10 5 cycles whereas it happens at 10 4 cycles for RT. Therefore, the number of endurance cycles is approximately ten times increased in the cryogenic environment. Reduction of stress-induced leakage current (SILC) at lower temperature contributes to improving the performance of cycling endurance. [10] In Figure 7b, the I ON /I OFF is roughly ten times enhanced at 77 K compared with at RT due to the steep SS.
Figure 7c-f compares the retention characteristics between RT and 77 K at V write = ±6.5 V with t pulse of 1 µs and 5 µs respectively for the MWs of V T and I ON /I OFF . The estimated retention time exceeding 10 years is extrapolated by use of the following equation: current = α − β×ln(time + γ) with proper constants of α, β, and γ. The MWs of V T and I ON /I OFF at RT completely closes at ≈1 year of retention with t pulse = 1 µs and less than 10 years with t pulse = 5 µs respectively. On the other hand, the MWs of 77 K at both t pulse = 1 and 5 µs can be sustained for longer than 10 years of retention time. Therefore, the cryogenic SONS cell can take advantage of not only the reduced power consumption with low V write and t pulse compared to the conventional SONOS cell, but also the highly improved reliability issues and increased I ON /I OFF .

Simulations toward Large-Scale System
Beyond the device-level experiments of the SONS cell at cryogenic temperatures, system-level simulations are conducted. The simulated model is illustrated in Figure 8a. The SONS-based cryogenic storage system is compared to the conventional SONOSbased one at 77 and 300 K. [9] For the latter (SONOS at 300 K), the microprocessor (memory controller) at 77 K is connected to the SONOS-based storage system at 300 K via cables. For system-level comparison, additional contributors influencing on power consumption are considered. For example, when the flash memory is placed in the cryogenic refrigerator (77 K), the refrigerator's cooling power needs to be additionally counted. The total power including a cooling power is approximately set to 10× of chip power in this paper (i.e., P total = 10 × P chip ), by averaging the commercial refrigerator cooling efficiency. [11] On the other side, when the SONS-based solid-state-drive (SSD) at 300 K is connected to the microprocessor at 77 K, heat loss via the cables needs to be considered. A NAND flash memory system for an SSD is composed of multiple banks and each bank is comprised of a memory cell array and necessary peripheral circuits for programming/sensing. For the device-level parameters, the measured data of the SONS cell and those of SONOS cell reported in ref. [9] were used (Figure 8b).
For the peripheral circuits modeling, models of a 22 nm Q8: fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor (FDSOI MOSFET) at 300 and 77 K (Figure 9) were used. [2] By updating the technology library with the cryogenic model, DESTINY, [12] a variant of NVSim [13] (the memory system-level www.advelectronicmat.de simulation framework) was used to estimate energy and power consumption for an interface between a host processor and an SSD. To determine the number of cables and their physical parameters such as thermal conductivity and diameter, the Intel the open NAND flash interface (ONFI) 5.0 interface protocol and commercial coaxial cable data (Lake Shore Cryotronics) were referred in this simulation. Finally, employing Fourier's law, the heat loss at the cable was calculated and added to the overall system power consumption (Figure 10).
The estimated performance of latency and energy for the NAND flash memory array is compared in Figure 11.
At 77 K, SONS-based flash memory is superior to conventional SONOS-based flash memory in terms of latency and energy for all operations of program (PGM), erase (ERS), and read. This is attributed to high I ON (due to larger gate capacitance) and low voltage of PGM, ERS, and pass operation. Compared to the cryogenic SONOS memory, the SONS memory shows performance improvement more than 80%. Quantitatively, speed enhancement is 81%, 98%, and 94% for read, ERS, and PGM, respectively. Note that excluding the peripheral circuitry, 80%, 79%, and 79% of the energy saving was estimated in the memory array level for each operation. W And Figure 8. Configuration of cryogenic system and system-level simulation data. a) Cell parameters (left) and system configuration for estimation of energy and latency (right). b) Organization of NAND-flash array with block-level schematic. Figure 9. I D -V G curve of 22 nm FDSOI MOSFET at 300 K (red) and 70 K (blue) for peripheral circuit modeling. [2] energy saving is 81%, 88%, and 87% for read, ERS, and PGM, respectively. Without the heat loss via the cable being considered, energy consumption of the SONS memory is slightly larger than that of the SONOS memory owing to the cooling power even though it is still advantageous in terms of latency. But, if such heat loss is counted, the above inferiority is eliminated. Because the heat is essentially dissipated through the cable even at an IDLE state, power efficiency of the system for overall operation will be improved. Power consumption according to a ratio of active operation time to IDLE time is compared in Figure 12.
Consequently, the SONS device is very attractive for cryogenic NAND flash memory cell, hence it will become increasingly important for high-performance computing at 77 K in the future data centers.

Conclusion
A SONS-based device was proposed for cryogenic storage memory. Even though the efficiency for PGM and ERS was notably improved by eliminating the tunneling oxide from   www.advelectronicmat.de a conventional SONOS flash memory, the poor retention was problematic at RT. On the contrary, such inferior retention characteristic was significantly improved at 77 K due to reduced thermal energy. Additionally, endurance performance was also boosted because the SILC effect becomes weakened at cryogenic environments. In terms of energy and latency, the system-level simulation showed that the SONS memory was more than five times superior to the SONOS memory when storage memory is placed at the cryogenic temperature. Even though considering refrigerator's cooling power, the cryogenic-SONS memory shows smaller power consumption compared to the RT storage configuration (SONOS), when considering heat loss at the cable connecting two temperature regions. Therefore, the proposed SONS structure is promising as a storage memory system for cryogenic computing.

Experimental Section
Fabrication of SONS Device: A p-type (100) silicon-on-insulator wafer (purchased from SOITEC) was used as a starting wafer. The top silicon film was thinned down to 40 nm thickness by oxidation process using furnace. Then, the fin structures were defined using optical lithography having 193 nm wavelength from KrF and the fin structures were reduced to 25 nm by photoresist (PR) ashing process. After that, 3.5 nm of Si 3 N 4 , 2 nm of tetraethyl orthosilicate, and 100 nm of n + poly-Si were sequentially deposited by low-pressure chemical vapor deposition, making S/O/N/S stack. The chemicalmechanical polishing was performed for planarization of the protruded poly-Si gate. Gate region was then patterned again using the PR ashing process, followed by oxide sidewall spacer formation. Then, the ion implantation process was conducted to form source/ drain (S/D) junctions with As, which was activated by rapid thermal annealing at 1000 °C for 5 s. Finally, forming gas annealing process was applied.
Estimation Process of Energy Consumption: In calculating arraylevel simulation results, the memory device operation dynamic energy consumption is calculated using the principle of CV 2 . In this formula, C is the gate capacitance of the memory device (SONS/ SONOS [9] ) and V is the read (pass)/erase (ERS)/programming (PGM) voltage gathered in the measurement results and reference papers. Gate capacitance C was estimated by measuring physical size of the fabricated devices (gate area, effective oxide thickness (EOT), etc.). According to the measurement results, even though the gate area was smaller in SONS (0.45x of that in SONOS), due to the smaller EOT the overall capacitance of SONS was estimated to be 1.3 times larger than SONOS. However, as the pass/PGM/ERS voltage is 2.50 (pass)/2.46 (ERS, PGM) times smaller in SONS, the overall energy consumption was estimated to be 4.81/ 4.65 times smaller compared to the SONOS.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.