Synaptic Transistor Based on In‐Ga‐Zn‐O Channel and Trap Layers with Highly Linear Conductance Modulation for Neuromorphic Computing

Brain‐inspired neuromorphic computing has drawn significant attraction as a promising technology beyond von Neumann architecture by using the parallel structure of synapses and neurons. Various artificial synapse configurations and materials have been proposed to emulate synaptic behaviors for human brain functions such as memorizing, learning, and visual processing. Especially, the memory type indium‐gallium‐zinc‐oxide (IGZO) synaptic transistor adopting a charge trapping layer (CTL) has the advantages of high stability and a low leakage current of the IGZO channel. However, the CTL material should be carefully selected and optimized to overcome the low de‐trapping efficiency, resulting from difficulty in inducing holes in the IGZO channel. In this paper, IGZO is adopted as a CTL and found out that making it degenerated is crucial to improving de‐trapping efficiency. The degenerate CTL, where electrons remain as free electrons, induces Fowler‐Nordheim tunneling by increasing the electric field across the tunneling layer. As a result, the synaptic transistor represents a high linearity of potentiation (αp: −0.03) and depression (αd: −0.47) with 64 conductance levels, which enables the spiking neural network simulation to achieve high accuracy of 98.08%. These experimental results indicate that the synapse transistor can be one of the promising candidates for neuromorphic applications.


Introduction
In recent years, the amount of data to be processed has grown exponentially with the rapid development of AI and IoT technologies. [1][2][3] Traditional computing based on von Neumann architecture suffers from computational inefficiency because of www.advelectronicmat.de band gap of the n-type IGZO channel, hole carriers are hardly induced and have extremely low mobility. [29] Therefore, the de-trapping process should depend solely on the electron detrapping in the charge trapping layer (CTL) without the assistance of hole carriers. To increase the de-trapping efficiency, light-assisted de-trapping [30][31][32] or changing the CTL material to oxide semiconductors [33,34] have been proposed. It has been reported that when IGZO is used as a CTL in memory, the efficiency of charge de-trapping improves with increasing CTL's conductivity. [35] Accordingly, the use of IGZO as a CTL can enhance the de-trapping process, simplifying device fabrication by using the same channel and CTL material. However, more detailed material properties and mechanisms of IGZO CTL for implementing synaptic behaviors have yet to be reported.
In this paper, we demonstrated synaptic transistors with bottom-gate structure using IGZO channel and IGZO CTL. By analyzing the energy band diagram of various CTLs, we found that the degenerate layer significantly improves the de-trapping efficiency due to the increased number of free electrons and their Fowler-Nordheim (FN) tunneling toward the channel layer. In addition, synaptic behaviors such as excitatory postsynaptic current (EPSC), inhibitory postsynaptic current (IPSC), long-term depression (LTP), and long-term potentiation (LTD) were successfully emulated under various voltage pulse conditions. Especially, the synaptic transistor shows high endurance and linearity in LTP/LTD using an incremental voltage scheme. Furthermore, a spiking neural network (SNN), which is a more biologically plausible network than an artificial neural network (ANN), [36] was simulated to validate the performance of our synaptic transistor in the neuromorphic system.

Results and Discussion
In the nervous system of the human brain, neurons are connected to each other via synapses that convey electrical signals from presynaptic neurons to postsynaptic neurons. The signal strength between neurons, called synaptic weight, is modulated by a neuromodulator, as shown in Figure 1a. [37] We fabricated bottom-gate IGZO synaptic transistors, where the drain and source can be connected to the presynaptic neuron and the postsynaptic neuron, respectively (Figure 1b,c). The channel transmits signals between neurons, where channel conductance can be controlled by modulating the amount of charge inside IGZO CTL sandwiched between the Al 2 O 3 blocking layer and the Al 2 O 3 tunneling layer. Using a gate terminal functioning as the neuromodulator, it is possible to control the synaptic weight independently regardless of the input spike of the neuron. In order to mimic synaptic behaviors, a sufficiently high electron trapping/de-trapping efficiency of the CTL is required to induce an appropriate conductance gain of the synaptic transistor. However, as previously reported high-k material CTL-based IGZO charge trap memory, it was difficult to de-trap electrons already trapped in deep states of the forbidden gap. [27] Therefore, it is important to make electrons de-trapped near the conduction band (E c ) to improve the de-trapping efficiency. IGZO has many donor states related to oxygen vacancy that can act as trap sites near E c . Furthermore, the fermi level (E f ) location in the IGZO also plays a key role as it determines the active trap/de-trap levels. These properties can be modulated by the oxygen partial pressure (P O2 ) during deposition. Accordingly, we fabricated IGZO synaptic transistors with different P O2 www.advelectronicmat.de (0% to 2%) of CTL to investigate the effect of oxygen vacancy concentration and E f of the CTL on trapping/de-trapping efficiency. First, the transfer curves of the synaptic transistors were compared under the gate double-sweep from −20 to 20 V. All devices exhibit clear clockwise hysteresis with a large on/off ratio of over 10 7 and a low leakage current ( Figure 1d). As P O2 of the CTL decreases from 2% to 0%, the hysteresis window increases from 2.7 V to 11.5 V, which might be attributed to an enhancement of electron trapping/de-trapping capability. To verify whether the observed hysteresis is an unstable operation occurring at the channel interface rather than in the CTL, a reference transistor without the CTL was fabricated using the same process conditions. Under the same double-sweep condition, the transistor showed almost no hysteresis, implying that charge trapping/de-trapping occurs in the CTL ( Figure S1, Supporting Information).
To further analyze the electron trapping/de-trapping behaviors of synaptic transistors with various P O2 , program and erase operations were performed using positive and negative gate voltage pulses, respectively. Figure 2a-c shows the transfer curves of the synaptic transistors at the pristine, programmed, and erased state according to the P O2 of the CTL. The programmed state was measured after applying a program pulse (20 V, 100 ms) in the pristine state. Then the erased state was measured after applying an erase pulse (−20 V, 10 ms) in the programmed state. When the program pulse is applied to the gate, the electrons accumulated in the channel are trapped in the CTL. Therefore, the threshold voltage (V TH ) increases in the programmed state. On the contrary, V TH will decrease if the trapped electrons in the CTL are successfully de-trapped to the channel under the erase pulse. With P O2 of 0%, the program and erase operations were successfully implemented, where the threshold voltages shift (ΔV TH ) by program and erase was 1.2 V and -2.1 V, respectively. Furthermore, repetitive program and erase operations were measured using the gate voltage pulses, exhibiting negligible degradation for 1000 cycles ( Figure S2, Supporting Information). However, as P O2 increased, ΔV TH by program decreased to 0.7 V and 0.4 V at P O2 of 1% and 2%, respectively, and ΔV TH by erase was not observed owing to suppressed electron de-trapping process. Pulse conditions can also affect trapping/de-trapping, so we additionally performed the same measurement with different pulse widths, as shown in Figure 2d,e. For the program operation, ΔV TH increased for all P O2 cases with the elevation of pulse width from 100 µs to 1s, representing the highest ΔV TH at P O2 of 0%. For the erase operation, |ΔV TH | increased with the elevation of pulse width only at P O2 of 0%. Contrary to the program, ΔV TH was not exhibited for the erase at P O2 of 1% and 2%, although the pulse width was increased to 1 s. This implies that the erase is much more sensitive to P O2 than the program.
To investigate the effect of P O2 on the electron trapping/detrapping capability of the CTL, the oxygen vacancy concentration and E f were quantitively analyzed by using several analysis methods. X-ray photoelectron spectroscopy (XPS) depth profiling was implemented on various P O2 of CTL to quantify the amount of oxygen vacancy that correlates with the donor density in the CTL, as shown in Figure 3a-c. The O 1s peaks are deconvoluted into three separate Gaussian-Lorentzian distributions (MO, Vo, -OH). The MO (530.3 eV) is associated with O 2− ions in the IGZO metal-oxygen bonding. The Vo (531 eV) is related to O 2− ions in oxygen-deficient regions that represent oxygen vacancies. The -OH (532 eV) is generally attributed to the chemisorbed hydroxide. [38,39] As P O2 increases, there is a significant change in the oxygen-binding www.advelectronicmat.de states in IGZO, where oxygen vacancy concentration decreases from 30.6% to 21.5%. This result could be attributed to an increase in stable MO bonds and a decline in oxygendeficient states during deposition. [40,41] The position of E f in the CTL changes depending on the oxygen vacancy concentration, which can alter the level of the site where the electron is trapped/de-trapped. [42] To clarify E f of the CTL with respect to P O2 , ultraviolet-visible (UV-vis) spectroscopy and ultraviolet photoelectron spectroscopy (UPS) measurements were conducted for the band alignment of the CTL. Figure 3d shows a Tauc plot of the CTL utilizing the measurement result by UV-vis spectroscopy at various P O2 of CTL. The intersection of the line, which extrapolated the (αhv) 2 against eV, represents the band gap energy (E g ) of the CTL, where the values were calculated to be 3.27, 3.34, and 3.35 eV for P O2 of 0, 1, and 2%, respectively. The introduced oxygen during deposition induces a decline in donor defects related to oxygen vacancies, which contributes to an increase in E g . [43] The UPS spectra result represents the band offset of the CTL according to P O2 , where the intercept of the background extrapolation line is the difference between E f and the valence band (E v ) (Figure 3e). The values of E f -E v were determined to be 3.3, 3.23, and 3.2 eV for the P O2 of 0, 1, and 2%, respectively. In addition, the work function (Φ) of the CTL was extracted using the high energy cut-off of the UPS spectra, where the values of Φ were calculated to 3.73 eV, 3.74 eV, and 3.74 eV for P O2 of 0%, 1%, and 2%, respectively ( Figure S3, Supporting Information). Considering the values of E g , E f -E v , and Φ, the band alignment of the CTL was obtained according to different P O2 (Figure 3f). At P O2 of 0%, the CTL is degenerate, where E f is located at 0.03 eV above E c . Excess carriers are present in the degenerate CTL due to the high oxygen vacancy concentration, and the carriers can be transported as free electrons via the overlap of In 5s orbitals on the E c . [44] In contrast, the CTL is non-degenerate at P O2 of 1% and 2%, where E f is located at 0.11 eV and 0.15 eV below E c for P O2 of 1% and 2%, respectively. As P O2 increases, the carrier concentration decreases so that CTL becomes non-degenerate with E f below E c and unoccupied trap sites. In addition, IGZO exhibits metallic behavior in degenerate state and operates as a semiconductor in non-degenerate state. [45] To verify this, we characterized transistors using the IGZO CTL as a channel with different P O2 ( Figure S4, Supporting Information). While metallic behavior was exhibited in the transfer curve at P O2 of 0%, conventional transfer characteristic was observed at P O2 of 1% and 2%. This result supports that CTL is degenerate at P O2 of 0% in the electrical measurement as well as the band alignment result based on UV-vis and UPS data. The fact that ΔV TH caused by de-trapping occurred only at P O2 of 0% in the previous pulse measurement indicates that the de-trapping efficiency increases significantly when the CTL is degenerate.
The programming and erasing behaviors can be explained in depth by using the energy band diagram of the synaptic transistor with two gate bias conditions, as shown in Figure 4. Since IGZO can be divided into degenerate and non-degenerate with respect to P O2 , trapping and de-trapping mechanisms in CTL should be explained separately based on P O2 . In the case of P O2 0%, E v and E c of the IGZO channel bend downward, leading to electron accumulation in the channel region for program operation (Figure 4a). As the CTL exhibits metallic behavior, the voltage drop across this layer is negligible, while there is a significant voltage drop across the tunneling layer. Therefore, the degenerate CTL can make the FN tunneling of accumulated electrons possible. As the trap sites of degenerate CTL below E c are already occupied, trapped electrons from the www.advelectronicmat.de channel can exist as free electrons above E c in the CTL. For erase operation, the channel is depleted by negative gate bias, and free electrons in the CTL are de-trapped to the channel by FN tunneling (Figure 4b). It is worth noting that the electrons can be easily trapped/de-trapped in the form of free electrons using a floating gate-like CTL. In the case of P O2 1/2%, the accumulated electrons are injected into E c via direct tunneling, and then the electrons are trapped in the trap sites under E c for program operation (Figure 4c). Band bending of the nondegenerate CTL reduces the electric field of the tunneling layer compared to the degenerate one, resulting in direct tunneling rather than FN tunneling. Regarding the de-trapping process, it is difficult to erase because electrons are trapped in the trap sites below E c , requiring additional energy to de-trap unlike the free electrons in the degenerate CTL (Figure 4d). Furthermore, direct tunneling causes less electron tunneling than FN tunneling under the same thickness of the tunneling layer. [46] Consequently, the electron de-trapping is significantly suppressed in non-degenerate CTL.
All measurements of synaptic behaviors were performed on a synaptic transistor with P O2 of 0%, indicating the best electron trapping/de-trapping capability in the CTL. As shown in Figure 5, EPSC and IPSC measurements of the synaptic transistor were implemented to emulate synaptic behaviors. Figure 5a,d shows EPSC and IPSC responses under negative (−20 V, 100µs) and positive (20 V, 5 ms) gate voltage pulses, respectively. In the EPSC response, the de-trapped electrons from the CTL are tunneled to the channel, and the gate field screening of the CTL is weakened by a decrease in the CTL charge, inducing an abrupt current increase from 175 to 295 nA. After the voltage pulse is removed, the current decays because there are no more electrons supplied from the CTL, and the current is slowly saturated to the level of CTL charge changeinducing current. In the IPSC response, there is a sudden drop in current from 171 to 96 nA because the gate field screening of the CTL is enhanced due to the trapped electrons in the CTL. The current decays slowly due to the leakage of some trapped electrons from the channel. Figure 5b,c shows the EPSC responses with increasing pulse voltage and width. As the pulse voltage increases from −16 to −20 V, ΔEPSC, the current difference before and after the pulse is applied, steadily increases from 37 to 122 nA. Likewise, as the pulse width increases from 100 µs to 1 ms, ΔEPSC increases from 21 to 119 nA. Figure 5e,f represents the IPSC responses with increasing pulse voltage As a next step, we measured LTP/LTD characteristics, which are essential properties in neuromorphic computing because the linearity and conductance level of LTP/LTD affect the classification accuracy of neural networks. [47] Channel conductance was modulated by using a series of gate voltage pules, where all conductance values were read at V GS of 0 V and V DS of 1 V. Figure 6a shows the LTP/LTD measurements using Scheme 1 composed of 32 potentiation pulses (−20 V/100 µs) and 32 depression pulses (20 V/2 ms) with the pulse interval of 50 ms. Additionally, LTP/LTD results with various pulse conditions are shown in Figure S5 (Supporting Information). The conductance change according to the pulse number is evaluated by the following equations: [48] ( ) where G p is the conductance of potentiation, and G d is the conductance of depression. P max is the maximum number of pulses. A is a parameter modulating nonlinear behavior. B fits the functions into the range of G min and G max . The fitting was performed using the equations and the predefined table ( Figure S6, Supporting Information) based on experimental results, where the nonlinearity factor α p and α d are −0.24 and −5.29, respectively. The device adopting Scheme 1 exhibits good linearity in LTP, whereas the linearity in LTD is poor due to excessive depression in the initial stage leading to high α d of −5.29. Incremental voltage method is used to address the abrupt conductance change in LTP/LTD. [49][50][51][52] We adopted Scheme 2 where the incremental voltage method is introduced only in depression to suppress the abrupt conductance decline in the initial step of LTD (Figure 6b). In Scheme 2, the voltage of depression pulse increases from 6 to 19.6 V at 0.8 V steps in the initial stage. When the pulse voltage reaches 19.6 V, the voltage of the next following pulses is fixed at 20 V to prevent excessive depression. By using the method of low voltage starting with 6 V and limiting the voltage to 20 V, disproportionate depression in the early and late stages is prevented, leading to improved LTD linearity (α d : −0.47). Furthermore, our synaptic transistor shows a high G max /G min ratio (>100) and a stable LTP/LTD conductance change for 500 cycles (Figure 6c). Retention characteristics of 32 conductance states were measured during 1000 s ( Figure S7a, Supporting Information). The conductance value of each state should not disturb the adjacent states for preventing impractical read condition updates. Considering the variation of all conductance states, adjacent state variation was tolerable during 60 s ( Figure S7b, Supporting Information).
To evaluate the performance of the synaptic transistor in the neuromorphic system, an SNN simulation was performed www.advelectronicmat.de using MATLAB software. In contrast to an ANN, which uses floating-point vectors as inputs and outputs, the SNN transmits input data as a series of spikes within a certain period. Figure 7a represents the spike propagation when the digit 9 image is used as an input. The image size is 28 × 28, and spikes are generated by using right-justified rate coding. [53] The number of spikes generated is proportional to the grayscale of the input image, and each spike is propagated in the right order according to the time step. We utilized three fully connected layers with 784 input neurons, 256 1st hidden neurons, 256 2nd hidden neurons, and 10 output neurons. As a neuron model, an integrate and fire model was adopted, which generates a spike to the next neuron when the accumulated voltage in the membrane capacitor exceeds a certain threshold voltage. [54] The intensity of voltage spikes generated in the presynaptic neuron is modulated by the synapses and then summed up in the membrane capacitor of the postsynaptic neuron. Each postsynaptic neuron has synapse units consisting of excitatory and inhibitory parts to implement positive and negative weights, respectively (Figure 7b). [55] To obtain synaptic weights to be transferred to synapses, ANN training was conducted in a Python environment using supervised learning with backpropagation and training parameters as follows: learning rate of 0.001, batch size of 50, and training epochs of 200. The ANN structure is the same as the SNN structure (784-256-256-10). The accuracy of the trained ANN network is 98.15% for the test sets ( Figure S8, Supporting Information). The trained ANN weights in the software were normalized and transferred to synapses in the SNN simulation. In the transfer process, the distribution of weight values changes due to the limited representable values of the synapse weight, which corresponds to 64 values of LTP and LTD ( Figure S9, Supporting Information). The SNN simulation was performed using a Modified National Institute of Standards and Technology (MNIST) dataset with the transferred weights. Figure S10 (Supporting Information) represents the membrane voltage variation of each output neuron according to the time step in the SNN when the digit 9 is used as an input. The classification accuracy of 98.08% could be achieved for 10 000 MNIST test images using the synapse transistor with Scheme 2, which was only 0.07% degradation compared to ANN accuracy (Figure 7c). In the initial time step, spike information is not sufficient to classify the digits of images, resulting in low classification accuracy. As the time step increases, the spike generation of the output neurons becomes sufficient to correctly classify the digits, where the output neuron with the most frequent spike generation represents the classification answer. Unlike the online learning method performing inference

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and training simultaneously, this SNN simulation uses the offline learning method that is less affected by linearity than the online learning method because it utilizes already trained weight values in the software. [56,57] Rather, it is important how densely the synapse conductance values between G min and G max can be expressed to achieve high accuracy in the SNN. Since our synaptic transistor has sufficient conductance level and linearity, the weights that can be expressed are evenly distributed between G min and G max , which ensures high accuracy. In other words, there is almost no information loss when converting the weights from ANN to SNN due to the sufficient representation of the synapse conductance. Next, we injected random variation noise with the gaussian distribution into all synapse weights to investigate the impact of weight variation in the SNN, where the mean value is 0 and σ w is the ratio of the standard deviation to the maximum weight value. Simulations were performed 20 times for each σ w , and the classification accuracy according to σ w was plotted using a box plot (Figure 7d). Despite the accuracy decline with an increase in σ w , the accuracy is above 94% until σ w increases to 10%, which is close to accuracy without variation. The simulation results show that the SNN is tolerant of weight variations to some extent, indicating that the synaptic transistor can operate well in a noisy environment. Our synaptic transistor shows superior synaptic characteristics compared with other recently reported IGZO-based synaptic devices (Table S1, Supporting Information). Based on the results, we expect the IGZO synaptic transistor to have the potential as an artificial synapse for high-performance neuromorphic computing.

Conclusion
In summary, we fabricated IGZO-based synaptic transistors using an Al 2 O 3 /IGZO/Al 2 O 3 gate dielectric stack to emulate synaptic behaviors. The program and erase characteristics according to P O2 of CTL were investigated by comparing the transfer curve measurement with the program/erase pulse. It was found that making CTL degenerate is a key point for improving trapping/de-trapping efficiency. Furthermore, the operation mechanism of the synaptic transistor with the band diagram in relation to P O2 was discussed. Synaptic behaviors such as EPSC, IPSC, LTP, and LTD were successfully implemented in the synaptic transistor with P O2 of 0%. High linearity and G max /G min ratio of LTP/LTD were achieved using an incremental pulse scheme. The SNN simulation with the synaptic transistor exhibited a high classification accuracy of 98.08% because of sufficient conductance level and linearity despite conversion from ANN to SNN. In addition, the SNN was tolerant of weight variation up to σ w of 10%, maintaining accuracy above 94%. The results indicate that the synaptic transistor using the IGZO as the channel and CTL, which has the benefit of low process temperature and less material usage, can be a promising candidate for neuromorphic applications.

Experimental Section
Device Fabrication of IGZO Synaptic Transistor: A heavily p-doped Si (≈0.005 Ω cm) substrate was cleaned and wet etched to remove the www.advelectronicmat.de native oxide. The 58-nm Al 2 O 3 blocking layer was deposited by atomic layer deposition (ALD) at 150 °C using a Trimethylaluminum (TMA) precursor with H 2 O oxidant. Then a 40-nm IGZO CTL was deposited by radio frequency (RF) sputtering at room temperature (RT). The target composition of In:Ga:Zn was 1:1:1 and the P O2 in the Ar/O 2 gas mixture during sputtering deposition was varied to 0%, 1%, and 2%. Subsequently, the CTL was patterned by photolithography and wet etching. The 7-nm Al 2 O 3 tunneling layer was deposited by ALD at 150 °C. A 40-nm IGZO channel layer was deposited by RF sputtering at RT with lower RF power than CTL. The channel layer was patterned by photolithography and wet etching. The 70-nm Source/drain electrodes were deposited by e-beam evaporation and formed by a lift-off process. The channel width and length of the device were 15 and 3 µm, respectively. Finally, all fabricated devices were annealed at 200 °C for 0.75 h in an air atmosphere to optimize the device characteristics.
Characterization: All electrical measurements were conducted in a dark box at RT. The transfer curves and synaptic behaviors of the devices were measured using a semiconductor parameter analyzer (Keithley, 4200 SCS & 4225 PMU). The top-view image of the device was measured using a scanning electron microscope (SEM; TESCAN, VEGA GMS). X-ray photoelectron spectroscopy (XPS; PHI, VersaProbe-III) measurements were conducted using Al kα (1486.6 eV) source. For depth profiling, sputtering was carried out using an argon ion gun with an acceleration of 3 kV. Deconvolution of XPS peaks was performed using the MultiPak software (PHI). Absorption spectra were measured with an ultraviolet-visible (UV-vis; Hitachi, U-2900) spectrometer in the range from 300 to 1100 nm. Ultraviolet photoelectron spectroscopy (UPS; Kratos, Axis Supra) was performed using He I (21.22 eV) source.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.