A Memristive Cell with Long Retention Time in 65 nm CMOS Technology

The memristor, which Leon Chua discovered in 1971 and Hewlett Packard fabricated for the first time in 2008, is still facing many design and fabrication challenges. Luckily, memristor emulators using mature Complementary Metal Oxide Semiconductor (CMOS) processes are good substitutes for memristors in several applications. The common setback for these emulators is their inability to retain their internal states for long periods of time. This article presents a memristive cell that not only has the memristor's characteristics but also can retain its resistance for up to 10 years. To bring forward such a cell, a charge trap in a 1 mm2 chip is designed and fabricated using a standard 65 nm CMOS process. By characterizing the proposed trap prototype, its unexpected yet interesting behavior is revealed, such as charge tunneling that occurrs at voltages between 350 mV and 650 mV despite the process sensitivity. Next, based on the measurement results and using the VerilogAMS programming language, the charge trap to be combined with other circuits that constitute the proposed memristive cell is modeled. This model, which is partly based on previously reported models, matches the measured characteristics of the fabricated charge trap and can be easily integrated into circuit simulations.


Introduction
The need for a programmable resistor has increased ever since dynamic analog-circuit solutions became considered to solve the complex problems with which traditional circuit or software solutions are floundering. [1,2] Programmable resistors are devices that have a variable resistance that varies with the voltages applied on the devices' terminals. The common characteristics capacity, the last two factors define the time required to fully charge or discharge any capacitor attached to an FGT; e) the junction breakdown voltage, where every p-n junction has a certain voltage tolerance beyond which the cell is damaged; f) the maximum number of permitted write-operations through the dielectric including every charging and discharging process; g) the effective voltage range, which determines the safe voltage limits for charge tunneling without breaking the p-n junction; and finally h) the transistor gate-tobulk and gate-to-terminal resistances.
Characterizing a CT, which deploys FGTs in particular, is very critical to produce a simulation model that matches the actual behavior of a real trap. Researchers have always struggled to simulate any FGT-based design before proceeding to chip fabrication, a process that is very costly in cutting-edge technologies. Some researchers used mathematical equations to estimate the gate leakage current in sub 70 nm MOSFETs. [13][14][15] Even with the use of advanced simulation models provided by recent computer-aided systems, it is still difficult to simulate an FGT-based design.
Multiple works relate to the characterization of FGTs. [16][17][18][19][20][21][22][23][24][25] Some research led to the fabrication of custom FGTs, [16][17][18][19][20][21] while others validated the developed theoretical models using computer aided design (CAD) tools. [25,26] On the other hand, some researchers characterized FGTs in standard 0.5 and 0.8 µm CMOS processes. [22,23] Meanwhile, other research started with a verified CAD model which was then utilized to fabricate an FGT in a standard 180 nm CMOS process. [10,27] The reported effective voltage range for charge tunneling in MOSFETs with 20 and 7 nm dielectric is between 1.2 and 5 V for transistors fabricated with 0.25 and 0.18 µm CMOS processes. [26] The thinner the dielectric layer is, the trickier it becomes reliably and controllably tunnel charges through it, because of the high sensitivity of the tunneling mechanism to the applied voltage. As a result, many recent applications that deploy FGTs are still not resorting to sub 70 nm transistors with sub 5 nm dielectric thicknesses. [28,29] In this work, a standard 65 nm CMOS process with 2 nm dielectric-thick MOSFETs is utilized to characterize our proposed CT cell, focusing on its main features like effective voltage range and retention time. After proper characterization, the fabricated CT cell was modeled in VerilogAMS and integrated with a memristor emulator adapted from ref. [30] to match the CT's working conditions. This integration resulted in a memristive cell capable of retaining data for longer periods while maintaining a pinched I-V hysteresis curve.
The rest of the paper is structured as follows: Section 2 clarifies our methodology, Section 3 reports the obtained results, Section 4 discusses our results and findings, and finally, Section 5 summarizes the derived conclusions.

Implementing a Charge Trap in 65 nm Process
The purpose of this section is to analyze the behavior of a CT cell fabricated in a 65 nm process. Two different cell topologies are proposed to study and analyze the properties of this CT: a) An individual transistor cell (ITC) composed of six transistors is used to characterize the effective voltage range and the tunneled-current magnitude and b) a capacitive cell (CC), made of one ITC attached to a capacitor and other circuit components, is used to analyze the retention time and both charging and discharging currents.

Individual Transistor Cells
Based on transistor characteristics in the targeted technology, the circuits of Figure 1a,b were designed to stress 1 V type transistors (M1 and M3) implemented in various widths. On the other hand, the pull-up transistors (M2 and M4) are of the 2.5 V type and have a higher voltage tolerance (<3.3 V) than that of the 1 V MOSFETs (<1.2 V). Each of these two 2.5 V transistors is used to control and stress the corresponding 1 V transistor when the shared pulse-train bus is applied. It is worth noting that, according to the technology documentation, the 2.5 V transistors used are supposed to function normally and do not suffer from time-dependent dielectric breakdown (TDDB) issues under the stressful voltage conditioning for the 1 V transistors, where pulse amplitudes do not exceed 3.3 V. Figure 1a presents the schematic of the basic cell in which nmos M1 is the device under test having a minimum channel length of 60 nm and three distinct width values: 2, 4, and 8 µm.
Since transistor M1's body is grounded and tunneling will likely occur on channel edges, the 14-finger layout of M1 with a large width-to-length (W/L) ratio maximizes the contact area between the transistor's source or drain terminals and its gate. Devices T1 and T2 are transmission gates made of two 2.5 V MOSFETs placed as protections between the thin-dielectric sensitive transistor gates and the bonding pads.
An external variable resistor is attached to node E during every measurement of the voltage V E (t). The current tunneled through M1 (i M1 (t)) can be calculated by dividing the aforementioned voltage (V E (t)) by its corresponding resistance on node E according to the relation: When a pulse train is applied on node A1 with EN1 voltage held low, transistor M2 will pass the applied train to node C, hence stressing M1 and forcing charges to tunnel from its source-gate and drain-gate thin dielectrics to node D1. Some theoretical models are often used in MOSFET circuit simulators when dealing with cutting-edge technologies like the Berkeley predictive technology models (BPTMs). The curves plotted in Figure 2 correspond to a 65 nm BPTM and are adapted from ref. [13]. The plots correspond to 1.3 and 1.7 nm dielectric thicknesses, which are close to MOSFETs' dielectric thicknesses in our targeted technology. Based on Figure 2, when V gate = 1 V, the leakage current is considered high until V source reaches 0.5 V which represents a turning point after which the current decreases on a logarithmic scale to reach values in the order of 10 −21 A at V source = 800 mV. This implies that the voltage difference between the sourceordrain nodes with the gate should be lower than 400 mV for the leakage to remain in the steep slope regime. That is for a transistor with characteristics similar to those plotted in Figure 2, the region of operation where charges could be trapped on a www.advelectronicmat.de floating gate transistor over a long period of time is that when V gate − V source(drain) < 1 V − 600 mV = 400 mV.
It is expected that the gate leakage current decreases as the dielectric thickness increases. For example under BPTM, the 1.3 nm dielectric-thick MOSFET has a tunneling current much greater than a 1.7 nm MOSFET. Hence, it is safe to assume a smaller leakage current for a 65 nm process (or other sub 70 nm processes) in which the dielectric is slightly thicker (>1.8 nm for 65 nm MOSFETs).
To investigate the variation in tunneled current for 1 V transistors with respect to channel width, the cell presented in Figure 1a was laid out and fabricated with multiple widths: 2, 4, and 8 µm. Furthermore, to analyze the differences in behavior between nmos and pmos transistors, the same cell configurations were repeated for a cell comprising a p-type transistor M3, as shown in Figure 1b.

Capacitive Cells
The circuit shown in Figure 1c is designed for characterizing the cell's retention time. This circuit reflects the effect of capacitor sizing on charging and discharging delays. When a pulse train is applied and transistor M8 is conducting by applying 0 V on node EN7, transistor M7 will be forced to tunnel charges according to the pulses' amplitude and duration.
In Figure 1c, capacitor C1 can have one of four different values: 10, 50, 80, and 200 fF. Each of these values corresponds to different charging and discharging times. However, the change in C1's capacitance is not supposed to affect the aforementioned FGT voltage limit (400 mV), which defines the maximum charge that can be trapped on the node.
Transistors M5 and M6 are 2.5 V nmos transistors matched in layout implementation based on the common centroid method. [31] The design decision of using 2.5 V transistors was taken for safety at a time when we had no specific knowledge of the tunneling characteristics of the 1 V transistors in the target technology. Devices A 1 and A 2 are two ammeters placed off-chip to measure the currents traversing M6 and M5, respectively. The voltage source V a supplies a DC voltage of 1 V whereas V g is a variable DC voltage source. When the voltage across capacitor C1 increases, the current measured by A 1 increases with V a = 1 V. Sweeping V g can translate the hidden voltage across C 1 The circuit of Figure 1d is similar to that of Figure 1c, but it also includes two matched copies of a voltage controlled  Gate leakage current versus the source voltage for various dielectric thicknesses in a 65 nm BPTM process when V gate = 1V (Reproduced with permission. [13] Copyright 2022, IEEE). www.advelectronicmat.de oscillator (VCO) whose internal structure is shown in Figure 1e. The voltage applied on the VCO control voltage terminal in Figure 1e tunes the VCO's output frequency. Hence, any two voltages are indirectly comparable by comparing the output frequencies of two matched copies of the VCO to which the two input voltages are connected. For example, in Figure 1d, the voltages C2 V and V g are assumed to be equal when the frequencies on nodes P 67 and P 68 are equal.
Adding the two VCOs to our experimental setup provides additional evidence of the voltage trapped on node C2 V in Figure 1d. This type of indirect measurement is mandatory for observing trapped charges on a floating node. In addition, converting voltages to frequencies provides signals rather insensitive to parasitics on the readout paths.

Emulator Circuit
In order to implement our proposed charge trap memristive cell (CTMC), we adapted the memristor emulator from ref. [30] for use into a 65 nm CMOS process. A detailed justification for choosing this emulator from the list of available emulators can be found in ref. [32]. In the SX subcircuit of Figure 3, transistors S 1 to S 4 form a simple differential amplifier with S 0 controlling the branches' currents, i 1 and i 2 , according to V bias . The voltage across C SX controls the conductance of S 5 which, in turn, affects S 5 's drain current, i 5 . The resulting circuit behaves as a memristor with a response directly dependent on the relations between A1 V , i 5 , and SX V C . The voltage SX V C can be defined as the memristor state whereas the current, i sx , is the memristor current.

CTMC Architecture
The circuit of Figure 3 shows CTMC's general architecture in which we integrate the aforementioned memristor emulator and the previously discussed CT cell. We used VerilogAMS to simulate the depicted CT model, and integrate it with other circuit components.
In the resulting memristive cell, SX V C is copied to FGT V C which has a longer retention time (up to 10 years) as compared to SX (around 1 µs). The voltage across the capacitor in SX, SX V C , controls the current traversing transistor M 3 . This current is mirrored to the control circuitry through R 1 . On the other side of the circuit and similar to SX V C , FGT V C is mirrored to the control circuitry which, in turn, controls the flow of the charging/discharging pulse trains (PTs) through V CTRL .
In this topology, the use of current mirrors is required in order to avoid non-gate leakage currents to (and from) the

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floating branch in CT. In addition, transistors M 3 and M 6 are designed to have very low gate-leakage currents (in the order of 10 −20 A). As the ultimate goal of our memristive cell is to match i FGT with i sx , transistors M 1 , M 2 , M 4 , and M 5 must have the same aspect ratio (W/L), and so must M 3 and M 6 . It follows that the resistors used should have the same resistance value.
The CTMC also includes two sub-circuits that ought to work together in harmony with one controlling the other. The first sub-circuit, called logic circuitry, controls the pulse train flow, PT, into CT through two comparators and a combination of ten logic gates. Each comparator has a hysteresis window to allow some error tolerance between the two voltages, SX V C and FGT V C . These comparators pass their signals to the 10-gate logic circuit which generates five control signals, four of which control the PT signal.
As for the pulse generator, this sub-circuit generates the PT signal based on the four control signals it receives, Ctrl {1 − 4} . The signal PT can have one of three shapes: a) positive sharp pulses when the branch connecting Pulse Train 1 is active; b) negative sharp pulses when the branch connecting Pulse Train 2 is active; and c) 0 V DC when all branches are disabled. The capacitors C 1 and C 2 help in generating pulses with controllable pulse widths and amplitudes, whereas the two-resistors branch adds positive or negative DC offset voltages to PT. The pulse generator sub-circuit is important for our memristive cell since it represents a simple solution to generate PT with the fine and positive (or negative) pulses required to charge CT. In Figure 3, In short, the functionality of our proposed memristive circuit changes according to the control signals, that is, EN FGT , Ctrl 1, Ctrl 2, Ctrl 3, and Ctrl 4, when either comparator detects a change in R1 V or R2 V . The CTMC can have one out of three modes: i) Off mode: All branches of the pulse generator circuit are shut down and the PT signal is at 0 V dc. In addition, EN FGT is held high to 1 V. This happens when R where Hysteresis Voltage Range 2 ε ≤ . ii) Charging mode: Only the Pulse Train 1 branch is activated (that is Ctrl 1 = 1 V, Ctrl 2 = 0 V, Ctrl 3 = 1 V, and Ctrl 4 = 0 V) and EN FGT is held low to 0 V. As a result, the PT signal takes the shape of positive pulses with some positive dc offset voltage iii) Discharging mode: Only the Pulse Train 2 branch is activated (that is Ctrl 1 = 0 V, Ctrl 2 = 1 V, Ctrl 3 = 0 V, and Ctrl 4 = 1 V) and EN FGT is held low to 0 V. As a result, the PT signal takes the shape of negative pulses with some negative dc offset

CT Characterization
In this section, the measurement results of the fabricated test chip whose micro-graph is shown in Figure 1f are reported in detail. These results were collected using: a) a Keithley 2450 SMU source meter, b) an Agilent 33220A waveform generator, c) a Tektronix MDO4104-6 oscilloscope, d) a Keithley 4200 SCS parameter analyzer, e) a Keysight N9010A spectrum analyzer, and f) the MATLAB software running on a Lenovo notebook (Intel i7 fourth generation chipset and 8 gigabytes of RAM).
All the reported results in this section were gathered using MATLAB by direct communication with the equipment using the general purpose interface bus protocol. The Keithley 2450 was the bottleneck in collecting data with around 80 ms per read command. This forced collecting the results in batches followed by estimating the correct timing in MATLAB.

Individual Transistor Cells
Transistor Response: In order to properly characterize the voltage tolerance of the capacitive cell (CC) presented in Figure 1c, the threshold voltage of the 2.5 V MOSFETs, like M5 and M6, should be measured. Therefore, the gate voltage of M5 was swept while applying a 1 V on V a , and the measured versus simulated drain currents are plotted in Figure 4. The curves in Figure 4 show a threshold voltage of 350 mV for the fabricated devices versus a 550 mV threshold voltage for the same devices under a computer simulation. Since transistors M5 and M6 are matched in layout, the two transistors are assumed to have the same threshold voltage which is considered to be the minimum voltage that can cause a change in the reading of ammeter A 1 , should C1 V change as a result of the current tunneled through M7.
In addition, our chip was fabricated in a process where the maximum voltages that the used 1 and 2.5 V transistors can withstand are 1.2 and 3.3 V, respectively. [33] For this chip, the purpose is to induce tunneling currents through the gates of the 1 V transistors, not the 2.5 V ones. Nominal supply voltages for both transistor models are 1 and 2.5 V, respectively. Our initial assumption while designing the test chip was that tunneling for 1 V devices would start at a voltage higher than 1 V, somewhere in the range of (1-2 V). Thus, to stress a 1 V MOSFET, it was expected that another transistor that can hold steadily the anticipated voltage range like the 2.5 V MOSFETs was needed. Computer simulations of the cells presented in Figure 1a,b demonstrated their ability to reflect the DC components of every input signal. However, existing models do not accurately reflect the charge tunneling phenomenon.

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In light of a lack of openly reported information on the tunneling voltage for devices with sub 5 nm gate dielectric, the circuits in Figure 1a,b were designed to flexibly stress only M1 or M3. Moreover, ESD protection cells were also removed for more flexibility.
Tunneling Voltage for 1V Model MOSFET: Figure 5 shows the measured tunneled currents in the ITCs (see Figure 1) when applying a 1 MHz pulse train. The averaged leakage current of the ITC in Figure 1a under no stress is plotted in Figure 5a for W = 8 µm and VDD = 0.8 V. This response indicates the sensitivity of the devices under test and shows that the measured current is a low-magnitude sinusoidal signal as long as the pulses' amplitudes are below 400 mV. Therefore, this low amplitude signal appears as a background interference component that adds to any signal that we attempt measuring with our experimental setup. The collected to measure data was interpolated as a sine wave with a period of 73 µs, an amplitude of 2.2 mV, a vertical offset of 2.2 mV, and a horizontal shift of 1.7 µs.
On the other hand, gradually increasing the pulse train amplitude on node A1 in Figure 1a from 400 to 500 mV increases the current on node E up to 6.5 nA, as shown in Figure 5b, Trial 1. This experiment was repeated under the same setup, and similar results were obtained (see Figure 5b, Trial 2). As long as we respected the 500 mV limit, we were able to reproduce these results even with similar cells in different copies of our chip.
Substrate Break-Down Voltage: The on-chip pulse train bus is shared among all cells with an enable terminal specific to each cell. To measure the breakdown voltage of the devices under test, a pulse train of variable magnitude was applied to a circuit randomly selected from those in Figure 1. While enabling the target cell by holding its corresponding EN voltage low and disabling other cells by holding their respective EN voltages high, some probes were connected to different chip pads with variable distances to the transistor under stress in order to detect any changes in the drawn currents. Applying any substrate voltage in the range between 0.8 and 2.5 V did not have any effect on the chip when either the applied pulse train amplitude was below 800 mV, or each of the gate currents detected by the measuring probes was below 50 nA. When the gate current of any MOSFET exceeded the 50 nA limit, changes in other onchip currents were detected, with values varying according to pulse train amplitudes. Chips that were subjected to this test could be easily distinguished from others under the microscope by substrate burnouts or silicon bubbles.
Dielectric BreakDown Voltage: We experimented with the cell of Figure 1a with the following configuration for M1: W = 2 µm and L = 60 nm. The plot of Trial 1 in Figure 5c shows the results of our first experimental trial in which we applied a maximum pulse train amplitude of 1.2 V and a VDD voltage of 500 mV to which the bulks of p-type MOSFETs are connected. In this test, the pulse period was 1 µs and the pulse width was 200 ns. We collected the current observed on terminal E of Figure 1a by attaching an external 1 MΩ resistor to this node and dividing the measured voltage by its corresponding resistance. The observed current started to increase at a pulse amplitude of www.advelectronicmat.de 450 mV and reached its maximum (8 nA) when the amplitude became 1.2 V. This behavior was symmetrical when sweeping the pulse amplitude downwards from 1.2 to 0 V.
In another experimental trial performed on the same circuit of Figure 1a, when we raised VDD to 800 mV, a higher tunneling current was observed with a maximum of 15 nA at pulses' amplitude of 1.2 V. Yet, before the tunneled current reached 15 nA, when the pulse amplitude exceeded 650 mV, the device started to have a resistive response equivalent to a 40 MΩ resistor (see the curve of Trial 2 in Figure 5c).
All our setups followed standard conditioning for MOSFETs compatible with the process used, with a substrate voltage (VDD) close to 1 V and a maximum pulse amplitude less than or equal to 1.2 V. Nonetheless, repeating the last experimental trial, under similar conditions, revealed different measurement results from those previously obtained in Trials 1 and 2. The FGT transistor did not respond to the applied pulse train, even when increasing VDD from 500 to 800 mV. Figure 5c presents the new behaviors in the curves of Trials 3 and 4, where a maximum tunneling current of 2 nA is observed. The obtained current is 13 nA less than that measured in Trial 1. This current is even lower than the normal recorded output induced by pulse amplitudes lower than 400 mV, see Figure 5a. Interpreting these results leads to the conclusion that the dielectric layer was damaged. More precisely, it is believed that this happened when the tunneling current exceeded 8 nA.
To validate this assumption, another cell was placed under test. This cell was also a variant of Figure 1a with M1 dimensions: W = 4 µm and L = 60 nm.
Under conditions similar to the previous experimental trials, Figure 5d shows the output response of the first trial on this cell performed with VDD = 800 mV. Therefore, by comparing the plots from Figure 5c ). It can be considered as the maximum voltage that can be trapped by a gate. b) Another threshold appears around 650 mV after which the output changes to a resistor-like behavior. It starts when the value of the tunneled current is around 13 nA. The resistive behavior appears to indicate a change in the physical characteristics of the gate dielectric and seems to be independent of transistor dimensions. c) The output response is symmetric on the up and down sweeps of the pulse train amplitude and is not reproducible once the tunneled current exceeds 13 nA. d) The measured gate leakage currents in the experimented circuits were in the range between 2and3 nA when the amplitudes were below 450 mV. Such low range appears to result from normal electro-magnetic interference (EMI) with other on-chip components. Tunneling Independence on MOSFET Width: Another important characteristic of the device's dielectric was revealed by comparing different measurements of all tests. The currents tunneled through FGTs' dielectric layers do not vary with the change in MOSFET dimensions. Figure 6 shows the variation in tunneled current versus the pulse sweep amplitude for different ITC configurations. As the amplitude increased, the tunneled current followed an exponential upwards trajectory independent of MOSFET's type and dimensions.

Capacitive Cells
Additional FG features, like retention time, could be explored by experimenting with the circuits of Figure 1c,d.
VCO-Based Verification: To verify the proper functionality of the VCOs in Figure 1d, a voltage sweep was applied on the gate of M9 (defined by V g ). The corresponding output frequency was measured on node P 68 . The measurement results are presented in Figure 7a along with computer simulation results for the same cell. The two curves are very close to each other, descending from 52 MHz at V g = 0 V to reach 12 MHz at V g = 1.6 V which is M13's threshold voltage. Figure 7b shows two curves representing the measurement results collected for the floating-node VCO in the capacitive cell (CC) of Figure 1d. When the circuit was disabled by holding a high voltage on node EN12, no change in VCO2's output frequency on node P 67 was noticed when sweeping the pulse-train amplitude. However after the circuit was enabled by forcing 0 V on node EN12, the output frequency dropped from 50 MHz at point A on the curve (see Figure 7b) to 40.85 MHz at point A′. This frequency variation occurred for pulses' amplitudes increasing gradually from 550 mV at point A to 680 mV at point A′. The frequency remained stable at 40.85 MHz between points A′ and B. At point B, when the amplitude reached 800 mV, another significant change in behavior was observed, and the VCO's output frequency started following that of node P 68 . Therefore, we can recognize different regions of operation in the curve of Figure 7b which are compatible with the findings previously reported in this article. In each of these regions, both FGT's current and frequency curves are affected around the same voltages (550 and 800 mV), indicating changes in the tunneling path(s). Around 550 mV (at point A in Figure 7b), the change in VCO2's output frequency measured at node P 67 is related to the observed increase, around the same pulses'  Figure 5d or that of Trial 2 in Figure 5c. In addition, for the voltage range between 650 and 800 mV, the slight change (almost negligible) in VCO2's output frequency between points A′ and B in Figure 7b can be, once again, related to changes in slopes of the tunneled current curves of transistor M1 in the plots of Trails 2 and 1 in Figure 5c,d, respectively. Around 800 mV and beyond (after point B in Figure 7b), VCO2's frequency started to decrease from 40 to 12 MHz. When compared to the measured frequency curve on P 68 in Figure 7a, both VCOs' frequencies are very close to each other. Moreover, the curves of M1's tunneled currents in Trials 2 and 1, respectively in Figure 5c,d, show important changes in the curves' slopes around this voltage (800 mV). We believe that around 800 mV one of the parallel leakage paths between M12's drain and C 2 (or their equivalent nodes in other circuits in Figure 1) broke, making it possible for VCO2's frequency to decrease with a steep slope.
Retention Time: The threshold voltage for transistors M5 and M6 of Figure 1c is between 350 and 565 mV depending on the post-fabrication process corner. Measuring the retention time in these circuits was difficult with this high voltage threshold compared to the maximum possible voltage on C 1 which is around 450 mV. Nonetheless, one of the fabricated chips had a low threshold voltage for transistor M6, probably due to process variations. This was the only cell in which we were able to measure a trapped voltage on a floating node. This voltage is detected due to the current traversing transistor M6 when no other on-chip cell or transistor was activated. The corresponding observed retention time for this device is 12 months at the time of writing this article. Figure 8 shows that transistor M6 current is 271.25 nA as recorded by ammeter A1 of Figure 1c with a 1 MΩ in-series resistor. We were able to calculate the internal voltage of the floating node from the MOSFET drain-current equation in its linear region, which leads to: V G − V TH ≃ 8 mV. In other words, V G is very close to V TH and can be estimated to be around 358 mV based on the discussion in Section 3.1.1.

Model
The plots of Figure 6 show the effects of sweeping the pulse amplitude on different MOSFETs in the design with variable channel widths. Measured data proved that the current tunneled through MOSFET's dielectric is independent of channel width. All curves are exponential and started from below 1 nA (between 0.5 and 0.8 nA) at an amplitude of 350 mV and grew to reach their maximum (5 nA) at an amplitude of 500 mV. Using MATLAB interpolation tools, the polynomial equation of the trend line was approximated to a fourth-degree polynomial. Using reverse Taylor expansion of the exponential equation, the curves can be modeled by the following equation: where I 0 is the initial current at time t = 0, and {B, C} are two process related constants. The plot of Figure 9 summarizes the complete model inspired by the results measured based on the performed tests on 1 V MOSFETs in the chips. When the pulse amplitude is lower than 350 mV, the measured current is dependent on the exact circuit's physical structure, and in this case, it is less than 1 nA. When the bias across the dielectric exceeds 350 mV, the current enters an exponential leakage region following Equation (1) until the curve enters a linear region when the pulse amplitude is in the vicinity of 550 mV for which a tunneled current of the order of 6 nA is observed. When entering this region, the device loses its ability to trap charges as the dielectric starts to develop a resistor-like behavior with an equivalent resistance of around 40 MΩ. After crossing the 1.2 V threshold, which is the estimated maximum tolerated voltage   Figure 1d with respect to voltage sweeps for: a) V g , and b) pulse train amplitude.

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for a 1 V MOSFET in a 65 nm process, the dielectric insulator starts to degrade. Therefore, at some point, when the insulator is completely damaged, the MOSFET's gate metal becomes connected to the substrate, thus creating a short circuit. In this region, the tunneled current is MOSFET specific, that is, it changes according to the MOSFET's dimensions.
Combining these four regions summarizes the dielectric behavior in a 65 nm process with a 2 nm dielectric thickness. The first three regions (no leakage, exponential leakage, and linear leakage, see Figure 9) are common among all transistors, independent of their dimensions, whereas the fourth region (dielectric breakdown) varies according to the dimensions of the device under test. The device remains in this region until reaching a pulse amplitude high enough to cause substrate damage, hence the chip becomes unusable and unreliable. Figure 10 shows the simulation results of the memristor emulator sub-circuit (SX) depicted in Figure 3. The circuit's transient response to a 1 MHz sinusoidal input on terminal A is a pinched hysteresis loop for the current, i sx , and a cyclical hyster-esis loop for the state, SX V C . The pinched loops are presented in Figure 10a when the amplitude of the applied sinusoidal signal was 200 and 400 mV, respectively. Similarly, Figure 10b presents the cyclical-loop responses due to the same amplitudes of the sinusoidal input, A1 V . It is important to note that the maximum voltage across C SX is 550 mV when the amplitude of the applied sinusoidal signal is 400 mV. This voltage across C SX does not exceed the desired CT voltage threshold. In other words, by copying SX V C to FGT V C , CT will operate in its exponential region, and shall not step into the linear leakage region where the device's behavior becomes incapable of trapping charges. Figure 11 shows the simulation results of the pulse generator sub-circuit presented in Figure 3. When a pulse train (Pulse Train 1) having a short rising time (20 ns) and a long falling time (200 ns) for every pulse is applied, the corresponding branch generates a positive pulse train on PT with pulses that have very thin pulse-widths and are of calculated amplitudes shifted by an offset voltage of  Figure 12 shows the transient response of our CTMC. The simulation consists of three phases, two of which are for CT charging while the third is for CT discharging. In this setup, SX V C is considered as the reference voltage for FGT V C . However, we can only control SX V C through A1 V (see Figure 10). Changing

The Complete Cell
www.advelectronicmat.de A1 V (which is not shown in Figure 12) causes the changes in SX V C , and based on FGT V C 's value, the comparators decide the operating mode of the pulse generator whether charging, discharging or off. Based on Figure 12, it is clear that when SX V C is larger than FGT V C , the decision circuitry orders a charge signal to the pulse generator, allowing PT to be positive. After around 12 µs, FGT V C reaches SX V C ε − , a time instant at which CT must retain its value with the help of other circuit components. Hence, we can notice the short charging signals between 10 and 50 µs. At 50 µs, when A1 V changes, SX V C changes accordingly, and consequently, the circuit re-enters the charging phase until time 62 µ ≈ s. Later, at time 100 = µs, SX V C changes so that . This change forces the circuit to enter a discharging phase to discharge FGT V C . On the other hand, to compare the leakage currents and the voltage decays on the CTMC capacitors, C SX and C FGT (Figure 3), we charged both capacitors up to 400 mV then we connected all CTMC terminals to the ground (0 V). After that, we measured the leakage currents (I(C SX ) and I(C FGT )) and the voltage decays of both capacitors (i.e., SX V C and FGT V C ), and the corresponding transient responses are plotted in Figure 13. From the figure, we notice that the voltage SX V C decayed to reach a 0 V just 40 µs after the simulation started. This voltage decay was caused by a considerably high leakage current (I(C SX )) which varied between 0.1 mA at time t = 0 s and 10 nA at time t = 150 µs. On the contrary, the voltage FGT V C did not decay during the whole simulation time, and the leakage current I(C FGT ) was almost negligible (3 fA) as compared to I(C SX ). These simulation results show the difference in retention times between the CT and the memristor emulator CTMC sub-circuits. In other words, the CTMC can be beneficial for applications that require long data retention times.

The CT Cell
CMOS technologies have progressed a lot ever since 65 nm was launched. In recent processes, dielectric thicknesses may be less than or equal to 1 nm, whereas the reported thicknesses for 65 nm are around 2 nm. When we decided on 65 nm as a target technology for our research, we had expectations on the behavior of its dielectric based on the existing literature, and we were confident that it was suitable for our end application. The tunneling voltage thresholds that we expected were quite far from our laboratory measurements. For example, we anticipated that charge tunneling would start around 1.5 V and that the dielectric breakdown voltage would be experienced around 3 V. However, the actual numbers, as reported in this paper, were 350 mV and 1.2 V for the tunneling and the breakdown voltage thresholds, respectively. This is surprising for a technology rated for long-term sustained operation at 1 V supply voltage. Based on our experience, we believe that it is very risky to predict the exact tunneling voltage for any more advanced technology without in-laboratory measurements, especially with the lack of physically validated models for floating gate  www.advelectronicmat.de devices. In short, although we believe that our observations theoretically apply to all CMOS processes with thin gate dielectric, the voltage thresholds separating different behavioral regions of the tunneled current will vary based on the dielectric thickness and materials involved.
Moreover, since our behavioral model for FGT's tunneled current is time-independent, Figure 9 is only a 2D curve (current vs voltage). In the laboratory, we selected the best-collected results of the performed experiments. All our observations about the tunneled current remained consistent with respect to the amplitude of the applied pulse train. That is, as long as the pulses' amplitude remained under 1.2 V, the magnitude of the tunneled current was time-independent. Table 1 shows how the CTMC compares to exiting resistive devices, including memristors. Our device can outperform its competitors in terms of data retention and endurance should its operating voltage range be respected. The reported CTMC numbers are estimated based on our theoretical knowledge of the transistors used. For example, the recorded retention time of the CT under test in Figure 8 is greater than 2 years without a significant change in the measured current. We expect this retention time to continue increasing with a slight decay in the measured current until the device reaches a retention time of 10 years as mentioned in the literature on FGT-CTs. [26] Similarly, we expect the CTMC to have an endurance greater than what it reported in the literature for similar devices which is 10 5 cycles. [10] It is safe to expect a higher endurance because our CTMC's operating voltage range (between 350 and 650 mV) does not stress any transistor causing a breakdown in its dielectric. Moreover, the proposed cell architecture is highly flexible and configurable according to application needs although the reported CTMC occupies a large surface area per unit cell, see Table 1. Our reported CTMC can be utilized in an inference engine similar to the recently published Artificial Intelligence Unit (AIU) by IBM. [55] In addition, we are confident that the CTMC is a proof of concept confirming that we can fabricate, using conventional CMOS transistors from a standard 65 nm process, a memristive cell with up to 10 years of data retention time. For us, the main goal was to design, fabricate, model, and simulate such a cell using a reliable CMOS process. In light of the difficulty encountered in obtaining experimental results that confirm the theoretical models that we proposed, we did not yet optimize the circuit for scalability, power consumption, or precision. While waiting for a reliable and accessible memristive device with a long retention time, our CTMC cell based on a mature CMOS process is very appealing for applications that need (or will need) robust and reliable devices exhibiting memristor functional behavior.

Cell Architecture and Design Flexibility
Our proposed CTMC has a large silicon area when compared to other memristor-emulating circuits. However, to the best of our knowledge, a memristive emulating circuit with a long data retention time using conventional CMOS devices with thin gate-dielectric has not been reported before. Moreover, by looking at CTMC's architecture (presented in Figure 3), one can classify the circuit parts into two different categories: a) Fundamental parts represented by the SX and FGT sub-circuits, and b) auxiliary parts represented by the current mirrors, the logic circuitry and the pulse generator sub-circuits. Each fundamental component (the SX and FGT sub-circuits that are 6T1C and 3T1C cells, respectively) uses a conventional capacitor which occupies a major proportion of CTMC's area. These capacitors can be replaced by MOS capacitors, which occupy smaller areas compared to conventional MIM and MOM capacitors, at the expense of a larger leakage current.
On the other hand, the auxiliary parts in CTMC's architecture are shareable among multiple cells. In this article, these  auxiliary sub-circuits are integrated into CTMC's architecture because of their significance for a successful proof-of-concept demonstration. In addition, the pulse generator circuitry presents a simple solution to a challenging problem by supplying calculated positive (or negative) short pulses that otherwise would only be provided by expensive test equipment or peripheral circuits. Having these shareable and configurable sub-circuits can increase both system's scalability and efficiency when used in large-scale systems dedicated to either computing or data storage. The CTMC cell can be easily embedded with in-memory and near-memory computing systems, more precisely, the resistive crossbar arrays required for performing vector-matrix multiplications in deep neural networks. The CTMC can operate in two different modes: a) An independent mode, that is, without sharing any sub-circuits with its neighboring cells, and b) a shared mode, that is, sharing the auxiliary sub-circuits with other co-linear CTMC cells when parsing the structures by rows or columns. The shared mode can also include sharing of other fundamental SX sub-circuit when parsing the crossbar structures sequentially on a cell-by-cell basis. This operation mode can be useful in dense memory-storage arrays such as NOR-structured flash EEPROM arrays.
The proposed CTMC-based arrays are quite similar to NORstructured flash EEPROM arrays. When comparing these structures, the following facts should be considered. Despite the similarity between the CT and the EEPROM cell, it is of interest that the gate-dielectric thickness for tunneling-based charge trap cells is either greater than 5 nm [56] or prohibited to be less than 8 nm, [57] whereas our CT traps charges behind 2 nm thick gate-dielectrics. Second, our CT, which is only a proof of concept, can support up to 16 resistance levels (4-bits) which is greater than or equal to most of the reported numbers of resistance levels for non-volatile memory (NVM) cells (such as 2.3-bits in ref. [58] and 4-bits in ref. [57]). Third, the high cross-interference and the electric stress due to cell programming are challenges facing NOR-structured EEPROM arrays. [26] In our case, the CTMC allows reducing the effects of these challenges because: a) the pulse amplitudes used are lower than 650 mV, which is safe for all circuit components, even for the targeted 1 V transistor; and b) it is possible, at the expense of reducing cell density per unit area, to integrate with every cell a pulse generator sub-circuit due to the CTMC's flexible topology. Fourth, the CT cell, which resembles the EEPROM in topology, is only a sub-circuit of the proposed CTMC which has a wider range of applications than NVM cells. As a matter of fact, one of CTMC's advantages is its ability to function as an NVM cell. Finally, the access to cutting-edge technologies, in which NVM cells are fabricated, is restricted for researchers in academia, and we hope that such restrictions will be removed in the future.

Conclusion
In this article, we proposed a reliable and robust memristive cell implemented using a standard 65 nm CMOS process. The cell comprises a charge trap (CT) that we designed and characterized experimentally under the same process on a 1 mm 2 chip we fabricated. The reported results helped to establish the CT's behavioral model relating the observed tunneled current to the applied pulse-train magnitude. This behavioral model defines four regions of operation based on the applied voltage's amplitude. In the first three regions, all tested transistors, independent of their dimensions, showed a similar electrical behavior that, on the contrary, varies with transistors' dimensions in the fourth region.
Based on the developed model, we adapted a memristor emulator from the literature to match our CT's operating conditions. After that, we integrated both cells (the CT and the memristor emulator) in our CTMC, which also integrates some digital and analog circuitry to control the CT charging and discharging processes. Computer simulations for the CTMC's architecture confirm its functionality, robustness, and design flexibility when used in complex architectures.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.