Integrated Memristor Network for Physiological Signal Processing

Humans are complex organisms made by millions of physiological systems. Therefore, physiological activities can represent physical or mental states of the human body. Physiological signal processing is essential in monitoring human physiological features. For example, non‐invasive electroencephalography (EEG) signals can be used to reconstruct brain consciousness and detect eye movements for identity verification. However, physiological signal processing requires high resolution, high sensitivity, fast responses, and low power consumption, hindering practical hardware design for physiological signal processing. The bionic capability of memristor devices is very promising in the context of building physiological signal processing hardware and they have demonstrated a handful of advantages over the traditional Von Neumann architecture system in accelerating neural networks. Memristor networks can be integrated as a hardware system for physiological signal processing that can deliver higher energy efficiency and lower latency compared to traditional implementations. This review paper first introduces memristor characteristics, followed by a comprehensive literature study of memristor‐based networks. Physiology signal processing applications enabled by these integrated memristor networks are also presented in this review. In summary, this paper aims to provide a new perspective on physiological signal processing using integrated memristor networks.


Introduction
Physiological activities are closely related to physical and mental health of human beings. However, due to the variability of each individual and the intrinsic nature of physiological signals, there are many limitations in detecting patients' physiological power and speed are limited by the data transfer bandwidth between storage and computing. To solve this problem, a promising route is to break the boundary between computation and storage, enabling calculations inside storage memories. Unlike traditional CMOS technology, the new neuromorphic chips simulate bionic artificial synapses and artificial neurons from bionic perspective, which has obvious advantages in terms of speed, power consumption, and hardware cost ( Figure 1). Memristors based on resistive random-access memory (RRAM), phase change random access memory (PCM), ferroelectric random access memory (FRAM) have been extensively researched in simulating the function of biological synapses and neurons. [10][11][12][13] The memristor-based neural network is composed of many neurons, and the memristor neuron has a simple structure, high integration density, and good non-volatility to store the neural network weight matrix. We map the matrix elements to the conductance value of the device at the corresponding position of the memristor array. According to Ohm's and Kirchhoff's current law, the vector-matrix multiplication (VMM) operations at the neural network's core can be executed efficiently. Based on the characteristics of memory and integrated memristor neurons, physiological signal processing algorithms such as perceptron, [21] convolutional neural network (CNN), [22] and reservoir network [23] have been realized (Figure 1). The integrated memristor neural network can process the sequence of physiological signals in different modes or regions in real time and directly describes the linkage between human's physical or mental states and physiological representations. As shown in Figure 1, it is widely used in brain-computer writing, [19] human authentication, [18] eye movement recognition, [20] etc. In recent years, many research have emerged to investigate the usage of memristors in the fields of neural synapses, neural morphology computing, logic computing, etc. Unlike the existing work in the literature, our manuscript elaborates on the memristor characteristics and integrated network at a high level and promotes the application of integrated memristor networks in physiological signal processing.

Characteristics of Memristors
Human brain is a vast and complex system composed of hundreds of billions of neurons, each connected with tens of thousands of synapses. It performs various computing functions through the activities of various neural networks and is an advanced intelligent system with low power consumption, high density, and high parallelism. Therefore, learning from the brain structure and information processing methods, neuromorphic computing that combines computing and memory has become a very promising direction of research [24] and plays a significant role in physiological signal processing. Memristor brings new vitality to neural morphology computing due to its similarities to biological synapses and neurons. The memristor is the fourth primary passive electronic device in addition to resistance, capacitance, and inductance. [25] Among all the emerging devices, RRAM attracts the most attention for its simple structure, high speed, low cost, good scalability, and high integration density, etc. Its device structure is a sandwich structure similar to a capacitor, called metal-insulator-metal Figure 1. Schematic diagram of physiological signals processing framework. The article is organized from micro to macro: device characteristics, network structure, and applications. In terms of device characteristics, we elaborate on the contributions of memristors for simulating bionic neurons and synapses. Reproduced under the terms of the CC-BY license. [14] Copyright 2022, The authors, published by Wiley. In terms of memristor networks, we describe in detail the types and structures of physiological signal-based memristor networks. For example, memristor arrays can be used for parallel processing of neural signals. Reproduced under the terms of the CC-BY license. [15] Copyright 2022, The authors, published by AAAS. Transformer network can be decoded EEG of Imagined Speech. Reproduced with permission. [16] Copyright 2022, IEEE. Reservoir computing can be used for biosignal processing. Reproduced under the terms of the CC-BY license. [17] Copyright 2016, Frontiers. In physiological signal applications, we have extensively investigated the application scenarios of physiological signal detection implemented based on memristors. For example, resnet model can be used for human authentication using ECG signals. Reproduced under the terms of the CC-BY license. [18] Copyright 2021, The authors, published by Wiley. Brain physiological signal can be used for brain-to-text communication. Reproduced with permission. [19] Copyright 2021, Springer Nature. EOG can be recognized eye writing activities. Reproduced with permission. [20] Copyright 2022, IEEE.
www.advelectronicmat.de (MIM), which can be reduced to nanoscale easily as shown in Figure 2a. [26] Under the applied electric field, the insulator may exhibit a resistance switching phenomenon. The device has a low resistance state (LRS) and a high resistance state (HRS), representing logic values "1" and "0," respectively. The process of applying a voltage stimulus to change the device state from HRS to LRS is called "set." On the contrary, switching from HRS to LRS is called "reset." At the initial state of each device, usually HRS, a larger voltage, compared to "set" process, is required to trigger the resistive switching of subsequent cycles, which is called "forming" process. The switching method of RRAM is divided into unipolar and bipolar according to whether it is related to the polarity of the applied voltage. For unipolar devices, the switching direction only depends on the amplitude of the applied voltage, while for bipolar devices, it also depends on the voltage polarity (Figure 2b-d). As a nonvolatile memory, RRAM devices do not change their resistances even if the applied voltage is removed. A small read voltage that does not change the resistance state is applied to read data from the device.
Currently, there are many explanations for the mechanism of resistance switching. The materials of metal electrodes and insulator layer in the middle are the dominant factors, while the mechanism is also related to the operations. It is commonly believed that the resistance switching is mainly due to the conductive filament (CF), which connects the top and bottom electrodes in the dielectric. The formation and rupture of conductive filament correspond to the LRS and HRS of the device, respectively. According to different conductive filament components, the resistive switching can be divided into three mechanisms, including the thermochemical mechanism (TCM), valance change mechanism (VCM), and electrochemical metallization (ECM). For VCM-based devices, the accumulation and neutralization of oxygen vacancies in the insulating layer under the applied electric field with different polarities lead to the resistance switching phenomenon. The above two mechanisms are based on the principle of anion migration and do not require the activity difference between top and bottom electrodes [27] (Figure 2e,f). However, ECM is based on metal ion migration and electrochemical reactions. Generally speaking, active and inert metals are used as anode and cathode materials, respectively. Under the control of the electric field, the migration of metal ions forms the conductive metal filament, controlling the transition of the resistive state.
Metrics of memristors will affect the performance of physiological signal processing systems, so it is imperative to assess the properties of devices. Memristors can be used in simulating biological synapses and neurons to calculate various neural networks, such as artificial neural networks (ANN), spiking neural network (SNN), etc. As artificial synapses, memristors can be used in digital and analog computing based on compute-inmemory (CIM). CIM is able to improve the processing of multiple physiological signals. [28,29] We can use online learning to update synaptic weights at any time and store the pre-training weights in the memristors for offline learning. An artificial neuron is another critical component of the neural morphology hardware system. Memristor can also build various neuron models, represented by Hodgkin-Huxley (H-H) model and the leaky integrate-and-fire (LIF) model, to realize the functions of biological neurons such as integrating information and nonlinear transformation. SNN is more similar to the calculations in biological neural systems compared to ANN. It is also more suitable to be implemented with neural morphological devices because traditional CMOS hardware systems consume long latency and high energy. The artificial synapse and neuron based on memristors can be a promising solution for these problems with a hardware-based SNN for physiological signal processing. In the next section, we will introduce the basic theory and the latest development of artificial synapses and neurons based on memristors.  [30] Copyright 2014, Elsevier. c) 20 set/reset cycles after DC forming at the compliance of 100 µA for Ta 2 O 5 -based device. d) The switching voltage for HfO 2 and Ta 2 O 5 cells. Reproduced with permission. [31] Copyright 2016, IEEE. e) Schematic of Pt/Ta 2 O 5−x /TaO 2−x device and internal oxygen vacancies movement mechanism. f) Scanning electron microscopy image of a 30-nm crossbar array (left) and TEM cross-section of a cell (right). Reproduced with permission. [32] Copyright 2011, Springer Nature. www.advelectronicmat.de

Artificial Synapse
When a neuron receives a stimulus signal, its connection with neighboring neurons can be enhanced or suppressed, and the synapse's weight represents the connection's strength. According to the duration of change, it can be divided into longterm plasticity and short-term plasticity. The long-term increase and decrease of synaptic efficacy correspond to long-term potentiation (LTP) and long-term depression (LTD), respectively, which last for hours or even days. As one of the manifestations of long-term plasticity, spike-timing-dependent plasticity (STDP) is a Hebbian learning rule in the form of temporal asymmetry (Figure 3a), and is the primary mechanism of biological learning and memory. STDP describes the dependence of synaptic weight on the time interval between pre-neuron and post-neuron being stimulated. If the pre-neuron receives Figure 3. a) Spike-timing-dependent plasticity (STDP) learning rules. Reproduced with permission. [52] Copyright 2019, Royal Society of Chemistry. b) The mechanisms of device nonlinearity during SET and RESET process. Reproduced with permission. [53] Copyright 2018, IEEE. c) Linearity of the device with one Ti inserting layer (left) and two Ti inserting layers (right) in an HfO x -based memristor. Reproduced with permission. [40] Copyright 2021, Elsevier. d) Endurance (left) and retention at 150 °C (middle) properties of Pt/TaO x /Pt device and Arrhenius plot of extrapolated data retention properties (right). Reproduced with permission. [48] Copyright 2008, IEEE. e) The circuit diagram of Hodgkin-Huxley (H-H) neuron composed of two Mott memristors, each with a characteristic parallel capacitance. f) The bistable current-voltage curves and scanning electron micrograph of the NbO 2based memristor. Reproduced with permission. [54] Copyright 2013, Springer Nature. g) Illustration of an ion channel embedded in the cell membrane near the soma of a biological neuron and corresponding relationship with each element in leaky integrate-and-fire (LIF) neuron circuit. h) Under the stimulation of multiple continuous pulses, the response of the integrate-and-fire circuit with different membrane capacitance C m and axial resistance R a . Reproduced with permission. [22] Copyright 2018, Springer Nature. www.advelectronicmat.de a stimulation earlier, the connection between the two neurons will be enhanced, that is, the long-term potentiation of the synapse. Otherwise, the long-term depression will be caused. In the spike neural network (SNN), localized learning rules such as STDP are generally used to update synaptic weights. Compared with the STDP learning rule, spike-rate-dependent plasticity (SRDP) is another one, which means that the synaptic weight will rise with the increase of pulse frequency. Different from long-term plasticity, short-term potential (STP) and shortterm depression (STD) only last a few seconds to a few minutes and then gradually return to the initial state. Short-term plasticity is generally considered to perform computing functions related to spatiotemporal information in the biological nervous system [33] and is expected to play a role in physiological signal processing.
Because of the similarity between the memristor and biological synapse, the memristor has excellent potential in constructing the neural morphological system. Under the stimulation of continuous pulses, the resistance or conductance of the synaptic device representing the connection strength shows continuous changes similar to the LTP and LTD processes of biological synapses. Therefore, the device may remain in the intermediate resistance between LRS and HRS to achieve higher storage density. With various intermediate conductance states, we can use a device to represent more bits and continuously adjust the device's conductance for analog computing. Using the multilevel capability of memristor cells fundamentally enhances hardware efficiency. If a single device is used to represent the synaptic weight, poor device metrics may incur lower network parameter accuracy, resulting in a significant degradation in the accuracy of the final results. Although it is possible to represent a single weight through multiple devices for higher accuracy, this will lead to greater hardware overhead and more complex peripheral circuits.
The device can maintain stable long-term plasticity after repeating 10 8 cycles in 2010, which realized LTP/LTD using Ag:Si/Si-based memristor. [34] A well-designed voltage pulse applied to the top and bottom electrodes of the device with diffusion limiting layer (DLL) insertion generates different conductance states related to the pulse time, and the result is similar to STDP behavior. In order to reduce the complexity of circuit and algorithm design, the diffusive memristor (SiO x N y :Ag) and the TaO x -based nonvolatile memristor are developed, which can both realize the SRDP and STDP learning rules. [35] STDP is realized by simply applying a short pulse with high voltage and a long pulse with low voltage. This is because the dynamics of the diffusive memristor provide an inherent timing mechanism, so there is no need for the complex hand design of pulses. Shortterm plasticity is generally realized by the instability of conductive filament formed by ion movements and the key is to directly stimulate the device with pulses without forming process. In this case, there are fewer oxygen vacancies in the device, which is not conducive to forming stable conductive filaments, making the device volatile. Ag nanoclusters can simulate the short-term plasticity on the Ta/Ag-NCs/Ta 2 O 5 /Pt/Ti memristor. Moreover, STP to LTP and STD to LTD conversion can be realized by increasing the pulse amplitude or the number of repeated pulses. The same results are reflected in other memristors such as diffusive memristors, WO 3 -based memristors, etc. [36] Good linearity, high endurance, and retention are necessary when a memristor is used as a synaptic weight in physiological signal processing. Each of these performance metrics of RRAM has reached a very high level, but degradations accompany it in other metrics. It should be pointed out that the requirements for specific device metrics are largely dependent on detailed applications. [37] Different application scenarios have different requirements for memristor metrics. The following section will introduce the developments and progress from different applications' perspectives.

Linearity
For analog switching behaviors in devices, synaptic plasticity's linearity and symmetry are critical, [38] affecting synaptic weights' adjustment accuracy during online learning and thus the network performance. The evolution process of conductive filament is usually divided into two stages, which are controlled by the drift process and diffusion process, respectively, as shown in Figure 3b.
The linearity of synaptic devices is usually solved by limiting the conductive filaments. SiO 2 DLL is inserted into the TaO xbased device to limit the diffusion rate of ions, thus homogenizing the growth and dissolution rate of conductive filaments and improving the linearity. Doping agent Al caused O-poor and O-rich regions in the HfO 2 layer to limit the growth of conductive filaments and effectively increased the linearity of the device. [39] Interface engineering is considered an effective way to obtain more linear switching. The interface state of HfO x can be recombined by inserting Ti as a buffer layer to form an oxygen vacancy concentration gradient to enhance the linearity. [40] The results are shown in Figure 3c.

Endurance
In an online learning application based on a memristor synapse, the synaptic weight needs to be updated frequently, so devices must be written and erased constantly. However, because of the internal ion dynamics of RRAM, the device may be permanently damaged each time when switching the resistance states. The number of times a device can be switched to ensure distinguishability, which is defined as the device's endurance. [41] For devices based on anion migration, tantalum oxide-based RRAM devices seem to have the best endurance characteristics. In the device structure of Pt/TaO x /Ta, the endurance of 1 × 10 10 cycles can be observed. [42] Due to the local switching phenomenon, endurance performs better in the bi-layered switching element. In Pt/Ta 2 O 5−x /TaO 2−x /Pt [32] (Figure 2e,f) and Pt/TaO x / Ta 2 O 5 /Pt [43] devices, they both reported that endurance could realize up to 1 × 10 12 cycles. The reason why TaO x -based devices have such good endurance is mainly due to the thermodynamic properties of materials. There are only two stable solid phases in the TaO system. The conductive channel and the matrix material form thermal stability, so it has higher stability during the switching process.
Furthermore, the electrode material will also impact the variability. [44] An improvement in endurance is observed by www.advelectronicmat.de replacing TiN/Ta 2 O 5 /Ta with Ru/Ta 2 O 5 /Ta structure because of the interaction between oxygen and the bottom TiN electrode. In addition to the attention paid to the material composition and structure, endurance can also be improved through external circuit control. By adding appropriate series resistance in the process of set and reset, a significantly improved endurance of the TaO x memristor is observed. [45] This is because the dynamic voltage divider between the series resistor and the RRAM cell reduces the switching variability.
The device based on cation migration will have a poorer endurance, mainly because the internal metal conductive filament has more significant variability. The prepared threshold switching (TS) device is prepared Ag/HfO x , which realized more than 1 × 10 8 cycles of endurance. [46] The device's performance can be effectively improved by doping and inserting nanocrystals into the oxide layer. By inserting Au or Cu into HfO x , endurance can reach 1 × 10 8 cycles at 85 °C. In general, the technical requirements for endurance are above 1 × 10 9 cycles, while the performance of TaO x -based RRAM is the best among all kinds of devices, reaching 1 × 10 12 .

Retention
Besides endurance, the retention of devices is also an essential part of reliability. Retention describes how long the resistance state can remain stable after the device is written to a specific value. Due to the introduction of pre-training synaptic weights in offline learning, device conductance is not updated frequently, and there is little demand for endurance. However, to make reliable inferences after programming, these applications have high requirements for retention.
Currently, many kinds of devices can meet the technical requirements of retention. In devices with Ti/HfO 2 /TiN, a storage time of more than ten years at room temperature has been demonstrated. [47] The resistance state's stability corresponds to the stability of the redox reaction, so the resistance change material (TaO x ) with the lowest absolute value of the reaction Gibbs energy of the redox reaction is selected. [48] Using a device structure of Pt/TaO x /Pt, a retention time of more than 10 years at 85 °C is predicted (Figure 3d). LRS is more challenging to maintain in RRAM devices because HRS is the initial state, which will stay in the absence of an external stimulus. In the device of TiN/TaO x /Ta 2 O 5 /TiN, the failure of LRS to HRS at high temperatures has been observed, and the retention time reaches more than ten years at 117 °C. [31] Due to the relatively higher activation energy of Ta/HfO 2 , this device possesses excellent stability. It has been confirmed that it can keep 7 × 10 4 years at 85 °C, and even more than ten years at 162 °C. [49] Interestingly, the HRS state is more difficult to sustain in the Ta/HfO 2 /Pt structure, possibly because the conductive filaments are relatively strong in LRS. For multilevel devices which can store multiple different resistance states in a cell, the probability of failure increases due to the narrowing of the gap between different resistance states. Therefore, the retention of such devices is relatively poor, [50,51] and it may take a period to refresh or perform new online training in bionic applications.

Artificial Neuron
In the living organism, the neuron is a nonlinear processing unit and a crucial nervous system part. About 10 11 neurons are connected by synapses and cooperate to receive, process, and transmit information. As another cornerstone of neuromorphic computing, artificial neurons are of fundamental significance to constructing brain-like intelligent systems, which have attracted widespread attention in the past few decades. Moreover, artificial neurons also play an important role in SNN, and the processing of time series by SNN has a wide range of applications in physiological signal processing. [55] The basic requirement of artificial neurons is to realize the potential accumulation processes and spike generation functions. Many neuron models have been proposed and used based on biological rationality. The H-H and LIF models are the most classic and widely used. The following will focus on introducing these two neurons based on the realization of memristors.

Hodgkin-Huxley (H-H) model
The H-H model [56] is the most accurate and complex neuron model to describe the electrochemical process of biological neurons, which can well approximate various firing behaviors of biological neurons. It is a 4D continuous model consisting of differential equations describing the conductance of each ion channel on the cell membrane and is commonly used to study the firing behavior and characteristics of individual neurons. The following two ordinary differential equations describe it: where I and C m are the total membrane current and capacitance per unit area, respectively. The membrane potential is denoted by V m while V i and i g (i = Na, K, l) represent the reversal potentials and maximum conductances of each channel respectively. n, m, and h are dimensionless probabilities between 0 and 1. α i and β i (i = n, m, h) are rate constants for the corresponding channel.
Both two NbO 2 -based memristors are used to build an H-H neuron circuit [54] and each memristor is connected in parallel with a capacitor and powered by a DC power supply with opposite polarity to simulate the opening and closing of Na + and K + ion channels in the model as shown in Figure 3e,f. The circuit is consistent with the H-H model, described by four coupled first-order differential equations, and has four dynamic state variables: conductive filament radii of memristors u1 and u2 and charges on the capacitor q1 and q2. The circuit can capture www.advelectronicmat.de complex neuron dynamics and realize many biomimetic properties. In 2018, H-H neurons were also realized in a similar circuit using memristors based on VO 2 , and 23 kinds of neuron firing behaviors can be realized by adjusting the input signal, parallel capacitance, and series resistance. [57] The system realizes richer neuron behavior based on the H-H model, which improves the prospect of bionic applications and increases hardware cost and operational complexity.

Leaky Integrate-and-Fire (LIF) Model
Because the calculation process of H-H neurons is too complicated, a simple LIF model is proposed, using a linear equation with only one variable ( Figure 3g where the meaning of each parameter is similar to the formula in the previous section. In addition to the charge term for the membrane potential, there is also a "leak" term, reflecting the diffusion of ions through the membrane. The LIF model only describes the generation process of the action potential, which is generated when neurons exceed a specific threshold potential (V th ) and do not include any ion dynamic process. [58] Therefore, a series of derivative models, such as the integrate-and-fire-orburst neuron model, is proposed to show more biological neurons' functions. Although the LIF model is not very similar to biological neurons, it greatly reduces the complexity in practical applications. The realization of leakage, integration, and firing functions makes it vital in constructing ANN and SNN systems. First, leakage is generally simulated by the relaxation process of the device, such as the ion diffusion in the diffusive memristor. [22] Leakage dynamics is a significant basis for spatiotemporal integration and nonlinear computation of signals. Second, the integration is achieved by exploiting the nonlinear physical process in the memristor, that is, the gradual formation of conductive filaments. Finally, the generation of the action potential is triggered by the strongly nonlinear transition process in the memristor, such as a sudden increase in the conductance of the device caused by the formation of conductive filaments. In contrast, the falling of action potential usually comes from the spontaneous inverse process of the volatile memristor. By connecting the memristor in series with a resistor and parallel with a capacitor, the LIF neuron is successfully simulated due to the diffusion dynamics process of Ag + inside the device, which reports a diffusive memristor based on SiO x N y :Ag. [22] The firing frequency of neuron can also be changed by adjusting the parameters of resistor and capacitor ( Figure 3h). But in practice, the adjustment of resistance and capacitance will increase the manufacturing cost and circuit complexity. [59] By controlling the memristor in the memristor-coupled capacitor, neurons can be programmed into two different models exhibiting different spiking behaviors, which facilitates the simplification of the circuit. The NbO xbased memristor is used to expand the function of the artificial neuron. [60] Besides the basic functions of the LIF model, more functions such as gain modulation and dynamic logic are realized, which has made a significant attempt to build a highprecision bionic neuromorphic device.

Crossbar for VMM
Machine learning and signal processing algorithms must be implemented on edge computing hardware in the brainmachine interface and wearable electronics domain. These algorithms are usually data-intensive and require lots of repeated operations. Traditional general-purpose processors such as CPUs and GPUs usually cost significant energy and computing time to implement these algorithms. Because of the limit of Von Neumann architecture, CPUs and GPUs waste much energy on repeatedly data loading. However, edge computing hardware usually has a limited energy source and does not support the power consumption of CPUs and GPUs. Thus, custom chips with low power and low latency are more suitable for edge applications.
Memristive devices and memristor-based computing systems are candidates for resolving this problem. Memristors are non-volatile memory devices that require no static power and the written information does not fade after the power is off. The memristor-based in-memory-computing system uses an array of memristors to perform VMM in a parallel scheme. Because the data is processed when it is readout from memory, the cost of data loading in Von Neumann's architecture is eliminated. The high parallelism and low power enabled by memristorbased in-memory computing provide the opportunity for implementing algorithms on edge hardware. It also has the potential physiological signal processing. In this section, we start with the in-memory-computing paradigm enabled by memristive devices and then introduce the memristor-integrated chips for real-world applications.

Memristor Array for VMM
VMM is the crucial operation of training and inference in machine learning algorithms. It is also frequently used in signal processing. Traditional computing in Von Neumann's architecture usually costs a lot of time and energy to perform these algorithms because of frequent memory access and low parallelism. Unlike traditional schemes, the crossbar structure of memristive devices can conduct VMM in a single readout operation. Considering the crossbar shown in Figure 4a,b, a memristor is placed on each cross-point. According to Ohm's Law and Kirchhoff's Law, the current on ith column is: The conductance G ij is stored in the memristor crossbar. The current vector I represents the result of vector V multiplying the matrix G. The memristor crossbar enables VMM with low power and a high degree of parallelism. Besides, memristor also serves as the candidate for high-density and low-power nonvolatile memory. A memristor array can be built by fabricating memristors in a crossbar structure (also called a passive array). It is the most intuitive way to build a memristor array for VMM with Kirchhoff's Law. The fabrication process only includes metal www.advelectronicmat.de wire and a memristor device. However, there is no additional selecting element for each memristor. In other words, a single memristor in the crossbar cannot be defined as selected or unselected. The crossbar can only be operated row-by-row or column-by-column. There are also sneak paths in the crossbar that can make the readout current incorrect.
1T1R array uses a transistor and a memristor to form a cell in the array. This scheme resolves the selection problem. The gates of these transistors are connected to additional word lines. Therefore, the cells whose gates off do not disturb any data writing or reading. The sneak path problem is eliminated. Memristor fabrication in 1T1R array must be CMOS compatible. 1T1R structure is favorable when integrating a memristor array with peripheral circuits to form an in-memory-computing chip.

Passive Memristor Array
The first experimental demonstration of a single-layer perceptron network on a memristor crossbar used a 10 × 2 TiO 2−x memristor array. [21] The crossbar can perform both in situ and ex situ training. This work proves the idea of memristor-based ANN at the array level. Two memristors represent a signed value in the neural network differentially. Though the fabrication variation is significantly reduced by using e-beam-defined protrusions, the current-voltage curve of the device still displays nonnegligible variation. The in situ training method can reduce the effect of device variation because device conductance is dynamically configured during in situ training. Classification results help adjust conductance value. . Memristor array architecture a) SEM photo of 12 × 12 passive array, using Al 2 O 3 /TiO 2−x memristor at each crosspoint. b) Schematic of 1R memristor array for signed weight storage in a single-layer perceptron. An example of classifying the letter "z" is illustrated. Reproduced with permission. [61] Copyright 2015, Springer Nature. c) 1T1R array for the single-layer neural network. The input of the neural network is mapped to BLs of the array while the current from each SL represents neural network output. d) The fabricated 1T1R array. Reproduced under the terms of the CC-BY license. [65] Copyright 2017, The authors, published by Springer Nature. e) Schematic of bidirectional transposable neurosynaptic array (TNSA) architecture. CMOS neurons are interleaved into the array, supporting a configurable computing scheme. Reproduced with permission. [66] Copyright 2022, Springer Nature.

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Later, a 12 × 12 memristor crossbar circuit is constructed for a single layer perceptron. [61] The crossbar array is fabricated with Al 2 O 3 /TiO 2 memristor (Figure 4a). This kind of device enables a transistor-free structure. The I-V curve's nonlinearity helps reduce the passive array's sneak path problem. The device variation is also controlled sufficiently low. This crossbar demonstrates a single-layer perceptron network for pattern classification. It can classify pictures 3 × 3 pixel array into three patterns, "Z," "V," and "N" (Figure 4b). Because the array supports the transistor-free operation and the device variability is low, the opportunity for implementing a larger neural network is opened up.
With more devices integrated, a multilayer neural network can be achieved in a memristor array. [62,63] Two passive 20 × 20 Pt/Al 2 O 3 /TiO 2−x /Ti/Pt memristor arrays integrated with onboard mixed-signal hardware can demonstrate a multilayer perceptron classifier. [63] It exhibits 10× higher hardware complexity compared to previous passive memristor crossbars. In this work, two crossbars serve as two layers in the neural network. CMOS neurons are used onboard to conduct the whole workflow of a multilayer neural network. This work shows that the memristor crossbar can be implemented with CMOS circuits to perform more complex neural networks.
A hybrid chip with a passive memristor array fully integrated with CMOS circuits is then demonstrated. [64] The designed peripheral circuit is fabricated in a standard CMOS process, while the 54 × 128 memristor crossbar is wire-bonded above the passivation of the CMOS chip. The fabricated peripheral circuitry includes ADCs, DACs, and control logic. ADCs and DACs are implemented in each row and column. Therefore, the array can conduct both forward and backward VMM in full parallel. In this work, the memristor array is operated in the charge domain. Compared to the traditional method that uses the voltage/current domain, this can avoid errors due to I-V nonlinearity. The DAC gives a pulse whose width represents an input value and the ADC collects the charge to finish the VMM operation.

Active Memristor Array
A passive (1R) array can achieve the highest memory density, but it still faces the sneak-path problem during programming and reading. Regarding the larger array, the sneak-path current causes more nonnegligible dispersion. Moreover, to construct a functional computing system, a memristor array has to be integrated with other circuits (ADCs, DACs, and digital circuits), mostly CMOS-based. Therefore, it is essential to fabricate a memristor with CMOS-compatible materials. 1T1R structure helps to achieve more complicated applications on memristor arrays, including various neural networks, solving a partial differential equation and sparse coding. [67][68][69] In additional to this, more device structures, including 1T2R, 2T2R, 2T1R, and 4T1R, are introduced (Figure 5g-i). 2T1R cell could provide low-power near-threshold-voltage read operations. [70,71] It supports transpose read (TR). The voltage division between T1 and memristor device controls the current flowing through T2. This can enhance the R-ratio by ≈150× but cost more area than 1T1R structure.
The 1T2R structure does not require additional area cost. It uses voltage-mode sensing and senses the voltage division between two device cells (one is HRS and the other is LRS). [72,73] This structure improves 1.12× to 5.29× read margin compared to 1T1R structure. 2T2R structure is constructed using two 1T1R cells. [74] It uses a shared word-line and complementary bitlines. It can represent both positive or negative weights. The voltage division between two cells is readout using voltage-type sense amplifiers.
Special cell structure can also be used for applications such as multiplexers. 4T1R structure is deployed to build one-level, two-level, and tree-like multiplexers. [75] This scheme achieves 22% delay improvement compared to CMOS multiplexers.
The memristor fabrication process is foundry-friendly. In 2017, a memristor with TiN/TaO x /HfAl y O x /TiN structure was developed to construct a 128 × 8 1T1R array. [65] In this work, the transistor circuits are fabricated in a 1.2 µm standard CMOS process and the memristor devices are stacked on the wafer, connecting to the drain of transistors, as shown in Figure 4c,d. The device in this work can be analog-modulated and shows bidirectional switching behavior. The write-verify scheme can modulate the device's conductance more precisely. The energy consumption for face classification can be reduced to 1000× lower than CPU with off-chip memory.
1T1R structure provides an opportunity for fabricating a larger array and supporting more complex applications. [76][77][78][79][80][81] A 128 × 64 1T1R array with analog resistance states is demonstrated for analog signal and image processing. [82] The multistate property supports analog weights in VMM, while the high linearity of the device supports analog input vectors in VMM. The analog conductance from 300 to 900 µS is used, while 10 µS variation in writing can be tolerated. This work reaches a high device yield of 99.8% using Ta/HfO 2 /Pd memristors. This chip especially suits for analog signal processing such as discrete cosine transformation (DCT) and convolutional image filtering, which are frequently used in physiological signal processing.
Single-layer or multi-layer perceptron can be successfully implemented on a 1T1R array. However, to deploy memristorbased hardware for practical models such as CNN, high device yield and uniformity, high memory capacity, and proper architecture are required. A convolutional neural network is implemented on the memristor-based system using eight 128 × 16 1T1R arrays. The TiN/TaO x /HfO x /TiN memristor device is fabricated in the back end of the line (BOEL) with a standard CMOS process. Eight memristors PEs are allocated to different layers in CNN to reach the highest computing speed.
Prior works proved that the memristor array can support various signal processing. [77] In this work, a 1 kB 1T1R array can implement an FIR filter and neural network for classification. Because of the high energy efficiency of the memristor-based system, the memristor array is especially suitable for brainmachine interfaces. It is demonstrated that a memristor-based system can achieve nearly 400× energy efficiency compared to a CMOS system. It provides further opportunities to implant memristor-based circuits to brain-machine interfaces and other edge devices. The 1T1R array can also be used for spike detection. [83] Although the memristor arrays can successfully demonstrate signal processing and neural network applications, they www.advelectronicmat.de do not support straightforward utilization in practice. Offchip ADCs, DACs, and data buffers are used in these works. To fully enable the utilization of the memristor array as an on-chip macro, the memristor array needs to be fully integrated with peripheral circuits on the chip. In computing-inmemory chips, a memristor is often referred to as RRAM or ReRAM. A straightforward way is to integrate the 1T1R array with wordline drivers and sense amplifiers that can readout current from the array, [84,85] as shown in Figure 5a. In 2018, a 1 MB RRAM computing-in-memory macro was built in a 65 nm CMOS process (Figure 5b). It uses the distance-racing current-mode sense amplifier (DR-CSA) as readout circuit and Figure 5. a) RRAM computing macro using 1T1R structure. It uses a dual-mode WL driver (D-WLDR), a current reference generator (REFG), and a distance-racing current-mode sense amplifier (DR-CSA). b) Die photo of the 1 MB 1T1R RRAM macro. c) Shmoo plot of the computing-in-memory operation. (a-c) Reproduced with permission. [85] Copyright 2018, IEEE. d) The architecture of the fully integrated analog computing-in-memory chip. A multilayer neural network is implemented using both 2T2R and 1T1R array. e) Die photo of the chip. Reproduced with permission. [86] Copyright 2020, IEEE. f) The architecture of the 8 MB DC-current-free RRAM macro. It uses BL parasitic capacitance to integrate charges. Reproduced with permission. [86] Copyright 2022, IEEE. g) 2T1R cell structure. h) 1T2R cell structure. i) 4T1R cell structure.
www.advelectronicmat.de provides less than 16 ns readout time for the computing-inmemory operation.
Different array structures can be integrated to implement a complete neural network on chip. A fully-integrated 158.8 kB analog ReRAM chip realizes a complete neural network on the chip. [86] It uses a 2T2R array to present signed value and reduce IR drop (Figure 5d,e). The resolution-adjustable ADC is designed to realize a low-power analog-digital interface. Thus, the balance between accuracy and power consumption can be tuned during operation. The chip can implement a 784-100-10 MLP model for the MNIST database with 94.4% accuracy and 78.4 TOPS/W energy efficiency.
Most RRAM CIM macros have a tradeoff between inference accuracy, energy efficiency and flexibility. NeuRRAM with bidirectional transposable neurosynaptic array (TNSA) provides a solution to improve all three properties. [87,88]  Voltage mode sensing can largely increase energy efficiency. The highest energy efficiency of 1286.4-21.6 TOPS/W can be reached by building a DC-current-free ReRAM macro. [89] In this work, BL parasitic capacitance stores the MAC value in the charge domain; thus, DC current is eliminated (Figure 5f). During the discharge of BL, a voltage-to-time converter and a time-to-digital converter is used to readout digital MAC values. The DC-current free scheme especially suits to edge computing applications because it consumes energy much slower and there is minimum heat generation at the location of the computing device. The integrated RRAM chip provides a low-power solution to process physiological signal on edge devices.

Memristor Array Using Internal Dynamics
Memristive device not only shows its potential for resistive memory, but also displays its nonlinearity for computing. This nonlinear and dynamical behavior enables reservoir computing, [90,91] synaptic emulator, [35] and simulated annealing [92,93] in a memristor array.
When a memristor is used as a memory cell or computingin-memory cell, its digital or analog value is used. The resistance linearity is crucial for this kind of computing. In other computing schemes such as reservoir computing and nonlinear functions in neural networks, the realization of nonlinear functions is also important. Usually, these specially designed circuits for nonlinear computing cost a large area and high energy. Besides configurable resistance, the memristor exhibits temporal characteristics that can be exploited for nonlinear computing. Because the computing is done in the device's natural behavior, it is far more efficient than the specially designed circuits.
The internal short-term memory of WO x memristors can serve as a time-dependent nonlinear function in a reservoir computing (RC) system. This work fabricates a 32 × 32 WO x memristor array. The memristor-based RC system includes a reservoir layer and a readout layer. The reservoir layer computes temporal response and the readout layer is a fully-connected neural network. The input information is formulated to spike trains implemented on memristors of the reservoir layer. Spikes temporarily modulate the conductance of the device. A spike can stimulate the device to increase conductance, and the conductance then gradually decays. The device also responds differently when spiking incomes with different time intervals. Thus, information can be nonlinearly processed when input is a spike train.
In the hardware RC system, the memristors in the reservoir layer compute the nonlinear temporal response with spike trains and the memristors in readout layer store the weights, as shown in Figure 6d. During training epochs, only memristors in output layer are upgraded. Chaotic system forecasting and spoken-digit recognition are successfully demonstrated. The RC computing scheme can be further extended to memristorbased brain-computer interface system. [28] A Ta/TaO x /Pt memristor array can implement a chaotic Hopfield network for combinatorial optimization problems. [93] The intrinsic chaos in the memristor device provides the potential to jump out of the local minimum in the problem's energy surface. To map a transient chaotic Hopfield network on memristor crossbar, the devices in diagonal positions are set as self-feedback weights while others are set as constant parameters (Figure 6a-c). Therefore simulated annealing is naturally implemented by calculating VMM in a dynamical memristor array. The evolution of solving the 10-city TSP problem is simulated in this work.

3D Memristor Array
Because the 1T1R cell size only limits the scaling of RRAM, it has the potential to provide the highest memory density compared to other memory cells. Furthermore, when RRAM is integrated through 3D, it can reach even higher density and achieve more complex functions.
It is challenging to build 3D circuits using CMOS transistors in the standard CMOS process because the single-crystalline silicon channel cannot be built in a multilayer. However, because memristors are fabricated in metal layers, it is more achievable to build 3D memristor circuits. The memristor cells in the multilayer are stacked together; this structure does not support 1T1R cells. Therefore, fabrication and device operation require special techniques for operating a single cell without disturbance.
The kernel sliding on an image requires numbers of kernel VMM operations. It can be either time-consuming or area consuming. 3D memristor array provides an approach for conducting VMM operations with high parallelism and area density. To conduct a convolution kernel operation in www.advelectronicmat.de 2D memristor array, the 2D kernel or 2D input data must be unrolled to 1D vectors.
The first 3D memristor circuit demonstration includes eight layers of memristors, [94] as shown in Figure 7a,b. The 3D array supports efficient convolutional neural networks and video signal processing. All convolution VMMs can be done in parallel. Once the image is input in 2D format, the convolution result can be readout also in 2D format (Figure 7c,d). This scheme reaches both time and area efficiency. It only supports specific convolution applications. Integration with the transistor is further needed to adapt for more applications.
3D vertical RRAM integration is then scaled to 55 nm CMOS technology. [88] It offers an approach for 3D VMM with 8.32 TOPS/W (8 bit-in, 9 bit-weight, 22 bit-out). Its bit density reaches 58.2 bit um 2 . The RRAM integration uses a multilevel self-selective (MLSS) 3D VRRAM array (Figure 7e-g). Each cell in the array is a self-selective cell (SSC) that can perform selecting a property in 1R structure. A bilayer HfO 2 /TaO x is used to form the SSC. By utilizing SSCs, the array does not require SLs. It requires 32 WLs and 8 × 8 BLs for an eightlayer 2Kb array. Brain MRI edge detection and inference on the CIFAR-10 dataset are demonstrated with sufficient accuracy. The 3D-integrated RRAM chip is able to process physiological information with high density.

Integrated Memristor Network
The traditional storage-computing separation integrated circuit chip architecture faces many new challenges with the continuous improvement of computing and storage requirements for artificial intelligence applications. The rise of memristors has dramatically promoted the implementation of neural networks at the hardware level, reduced power consumption, and improved the speed of neural networks. Currently, neural network research based on deep learning has been widely used in artificial intelligence, and neural networks have also developed from artificial neural networks to spiking neural networks, which are very helpful for physiological signal processing.

Artificial Neural Network
To realize the function of the neural network through artificial design, McCulloch and Pitts studied how the human brain generates complex patterns through neurons in 1943, [24] and in 1958, [95] the perceptron appeared, which is the first artificial neural network. After that, artificial neural networks have been developed rapidly with a wide range of real-world applications. These applications could be divided into image recognition and  [93] Copyright 2020, The authors, published by AAAS Science. d) Memristor-based hardware system for reservoir computing. A memristor array serves as a reservoir in the system. Internal temporal states of memristors are used. Reproduced with permission. [90] Copyright 2019, Springer Nature.
www.advelectronicmat.de sequence data processing tasks, corresponding to feature image extraction and data analysis in physiological signal processing. The development of artificial neural networks leads to a boom in data and model complexity, which in turn requires a better hardware platform. Therefore, memristors, as one of the new memory devices, have also received attention.

Perceptron
Single-layer perceptron (SLP) is the first-generation artificial neural network and only consists of an input layer, an output layer, and their connections. As the extension of SLP, hidden layers can be added between the input and output layers to obtain multilayer perceptron (MLP). In contrast, MLP can increase its depth through the back-propagation algorithm to change the defect that SLP can only solve linear problems. No matter in SLP or MLP, the two adjacent layers are fully connected, and the value of the next layer's nodes is given by multiplying the value of the previous layer's nodes and the weights on the connection line. Therefore, the primary type of calculation in the perceptron model is matrix-vector multiplication, which means a crossbar can realize both the storage and calculation of the model.
Memristors can construct crossbars as nodes to realize the perceptron, [96,97] but the data type most perceptron utilized in software is FP32, which has excessively large data to implement for crossbars. Thus, perceptron needs to be quantized Figure 7. a) 3D memristor architecture. The pillar electrodes (red) are used as input while the staircase electrodes are output. b) TEM of 8-layer 3D memristor stack. c) Paradigm of 2D convolution in 3D memristor array. d) 3D illustration of convolution operation in the 3D memristor array. Reproduced with permission. [94] Copyright 2020, Springer Nature. e) TEM photo of the eight-layer stacked. f) Architecture of VRRAM-based nvCIM Macro. g) Die photo of the 2 kB. Reproduced under the terms of the CC-BY license. [88] Copyright 2022, The authors, published by Springer Nature.
www.advelectronicmat.de into a binary called BNN. The available binary RRAM device can implement the task. [84] This work fabricates a 16 MB RRAM chip based on the 130 nm technology node, implements a binary three-layer perceptron, and achieves close to 97% accuracy on the MNIST dataset. The device has only two conductance states corresponding to the binary weights of the model, and can represent the positive and negative weights by difference pairs in crossbars. Although the quantization of perceptron into binary can reduce the cost of network implementation, it will also lead to a decrease in task accuracy, which requires the multi-level characteristic of memristor devices to represent non-binary weights. Tsinghua University formed 1024 multi-level RRAM cells to build a three-layer perceptron, demonstrating the grayscale face classification task. [65] Besides the CMOS process compatibility, the analog non-volatile memory in the array also has bidirectional continuous weight modulation behavior, which enables the 1T1R structure to achieve both positive and negative values. During the inference stage, input voltage pulses are applied to the array via bit lines, and the currents are then weighted and summed on signal lines as shown in Figure 8a. Focused on the face classification task, the voltage pulses on bit lines are nine training image signals, and the total current output on signal lines can obtain three output values through activation functions to complete the classification. In addition, the array also realizes online training, and the write strategy without verification can be used during online training to simplify the training operation at the cost of a certain degree of accuracy, energy consumption and latency. This work can reach 88.08% accuracy on 9000 test images with the influence of noise through online learning and inference based on RRAM crossbars for the grayscale face image recognition task based on the Yale face database. Moreover, the RRAM cells in this work have eight conductance levels, implementing an 8-bit perceptron. Compared with the neural network computing based on the Intel Xeon Phi processor, the neural network based on the 1T1R array consumes 1000 times less energy in on-chip computing and 20 times lower in off-chip computing.
Like RRAM, PCM has multi-level conductance characteristics and can construct crossbars. [98,99] However, some non-ideal factors of devices can cause performance degradation, one of which is the conductance change caused by temperature change. In 2018, IBM designed a simple model to compensate Figure 8. a) Mapping between single layer in MLP and 1T1R array. Reproduced with permission. [65] Copyright 2017, Springer Nature. b) Implementation of 3 × 3 image classification task with 10 × 3 crossbar. Reproduced with permission. [100] Copyright 2018, IEEE. c) Schematic of RRAM-based synapses used for convolution. Reproduced with permission. [106] Copyright 2015, IEEE. d) Schematic of kernels in CNN implemented by the crossbar. Reproduced under the terms of the CC-BY license. [107] Copyright 2017, The authors, published by Gokmen, Onen, and Haensch. e) Schematic of training and inference process of ResNet based on PCM. Reproduced with permission. [108] Copyright 2020, Springer Nature.

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for temperature-dependent conductance changes in crossbars. [100] The PCM cells in this work have a non-insulating projection segment parallel to the phase-change segment in their structure, which helps reduce the device's field dependence and non-ideality factors such as conductance drift and 1/f noise. Through modulating the 12 conductance states of the PCM devices, this work constructs a 10 × 3 crossbar and implements a simple single-layer perceptron for classifying three kinds of images about numbers in Figure 8b. Due to the effect of temperature on conductance, the array suffers a noticeable drop in accuracy as the temperature rises. But it can be compensated for and restored to an accuracy close to 8-bit fixed-point multiplication by constructing a model whose formula is f (T) = 1 + α p (T − T 0 ), which is obtained by fitting the conductance change function. Besides, MLP could also be applied to EEG dataset processing [101] by classifying the input signal of brain activation.

Convolutional Neural Network
After deepening the layers of the network based on perceptron to obtain a deep neural network, a convolutional neural network can be obtained by adding convolutional layers. CNN can reduce the dimension of input data while retaining the main image features. A typical CNN consists of three parts: Convolutional layer, pooling layer, and fully connected layer. The convolutional layer extracts feature in the image through convolution operations, while the pooling layer uses pooling operations containing special convolution operations to reduce the parameter dimension significantly. Moreover, the fully connected layer, often placed at the end of the network, is similar to a perceptron, designed to implement the final classification task. Therefore, CNN has a stronger generalization ability than the multi-layer perceptron, leading to broader applications. The implementation of CNN based on memristor crossbars mainly includes the convolution operation and the fully connected layer. Like the previous perceptron, the fully connected layer can be implemented by matrix-vector multiplication, and the convolutional layer can also obtain an expression similar to matrix-vector multiplication after mathematical transformation. [102,103] Similar to perceptron, CNN also could be utilized for emotion classification. [104] With the emergence of ResNet [105] in 2015, CNN has developed rapidly. Moreover, memristor devices have been used to implement CNN. [106] Garbin et al. utilized binary-level HfO 2 memristors as synapses in CNN (Figure 8c). They confirmed that the variation of device conductance has little effect on the accuracy of the MNIST classification task after the hardware experiment, proving the potential of memristors to act as synapses in CNN. Further, IBM proposed mapping convolutional layers to memristor crossbars and implementing online training based on crossbars in 2017. [107] By downscaling and amplifying the signals, this work reduced the impact of noise and boundary constraints on the accuracy of online training while maintaining valid information. Besides, the influence of the stochasticity of memristors is also discussed based on the mapping method in Figure 8d.
After that, CNN networks based on memristors have been extensively studied. Vinay et al. mapped the weights of ResNet to PCM cells (Figure 8e), and implemented the CIFAR-10 classification task at an accuracy of over 93% and the ImageNet classification task at a top-1 accuracy of 71.6%. [108] Two types of ResNet, ResNet-32 and ResNet-34, are mentioned in this work, which differ in the number and size of their ResNet blocks and input/output channels. This work utilized differential pairs of multi-level PCM cells to represent positive and negative weights through equal scaling. Since writing noise from inaccurate programming and reading noise from temporal fluctuations, network performance can obtain an improvement of 3.8% accuracy by only adding Gaussian noise to the forward pass rather than both the backward and forward pass during training. In the hardware experiment, 1 million PCM devices are programmed iteratively by the write-verify method and measured their conductance change. Based on the observed behavior about conductance drift, the global drift compensation procedure is designed to compensate for the accuracy loss over time. Besides, 1/f noise also significantly impacted the network, which can be weakened by applying adaptive batch noise when adding noise to the forward pass.

Bayesian Neural Network
Regarding randomness, Bayesian neural networks are inescapable among deep learning techniques. In contrast to the perceptron-based artificial neural network, BayNN stores the weight expression in Gaussian distribution instead of a certain value, enabling BayNN to describe events with probability. In addition, events represented by probabilities are closer to actual physiological signals and can play a more important role in physiological assessment. Although BayNN has shown the potential to implement probabilistic machine learning, the computational cost of BayNNs has limited its application in edge devices. BayNN needs to repeatedly sample from the trained network weights and repeat inference based on the sampled weights, which makes the hardware cost of BayNN rise rapidly with the expansion of its parameter size. However, the inherent stochastic characteristic of memristors coincides with the requirements of BayNN for the Gaussian distribution of weights, leading to a boom in research about BayNN based on memristors.
There are different principles of stochasticity in memristor crossbars that can be applied to the weights of BayNN. Huaqiang Wu et al. first developed an implementation of BayNN in 2019, using the inherent RTN noise of RRAM. [109] As shown in Figure 9a, this work measured the RTN noise of one single device while reading the conductance and used N RRAM cells to represent one weight value to amplify the stochasticity of network weight. By sampling the weights through a single parallel read operation, the RRAM-based BayNN exhibits much higher resistance to random noise than traditional deep neural networks in adversarial tests. In addition, the cycle-to-cycle variability of RRAM can also be used to achieve this probabilistic sampling function. Akul et al. developed a device-circuit-algorithm co-simulation architecture for the MNIST dataset, and implemented a Bayesian neural network based on RRAM. [110] Due to the random oxygen vacancy filament dissolution process in the RESET process, the RRAM device will appear random www.advelectronicmat.de from cycle to cycle. Based on the stochastic characteristic, the gaussian signal circuit is designed in Figure 9b. Although this distribution gap is not a strict Gaussian distribution, closer to the lognormal distribution, the slight deviation from the Gaussian distribution did not impact the network accuracy in the experiment. In addition, PCM is one of the potential platforms for BayNN. [111,112]

Long Short Term Memory Network
LSTM is a time recurrent neural network, suitable for processing and predicting events with relatively long intervals and delays in time series and is designed to solve the problem of gradient disappearance in the RNN structure. Moreover, the sequence data in time series is the same type of data as in physiological signal processing. LSTM can remember long-term information through the design of the gate structure, but the structure requires repeated scheduling. Therefore, memristor crossbars have great advantages in realizing synaptic functions and memory-computing integrated architectures in LSTMs, which can achieve highly parallel high-speed and low-power operations and avoid von Neumann bottlenecks. Memristors can also be used in algorithms for sequential data processing, such as long-short-term memory networks. [113,114] The structure of LSTM, besides and the corresponding crossbar realization, is shown in Figure 9c.
The University of Massachusetts [116] first implemented LSTM on the 128 × 64 1T1R array, and the conductance of the memristor maps the synaptic weight shared by LSTM in different time steps. Moreover, the linear matrix multiplication is directly realized in the memristor crossbars without transferring data cyclically. In order to compensate for possible hardware nonideal factors, this work adopted RRAM-based online training on typical regression and classification problems such as the global airline passenger number prediction task and human gait recognition task, respectively. It reached the performance of 800 epochs and 79.1%. On text processing tasks, memristor-based LSTMs also perform well. IBM [117] mapped and encoded weight parameters into PCM in the case of high device inconsistency, and used monotonic write conductance and differential peering methods to improve network accuracy, and realized the forward inference of LSTM. For the first time, approximate software text prediction accuracy is achieved in an array of 2.5 M sizes, and  [109] Copyright 2019, IEEE. b) The structure of the RRAM crossbar designed for Gaussian-distributed BayNN. Reproduced with permission. [110] Copyright 2020, IEEE. c) The structure of LSTM and realized with crossbars. Reproduced with permission. [113] Copyright 2021, IEEE. d) The circuit diagram of memristive LSTM network. Reproduced with permission. [115] Copyright 2021, IEEE.
www.advelectronicmat.de the impact of multiple different methods on weight mapping accuracy and prediction accuracy is compared. Now it has verified the feasibility of memristor-based LSTM to perform linear regression prediction tasks, pattern recognition tasks and text prediction tasks, and verified the feasibility of memristor crossbars as a low-latency, low-power edge inference platform to run LSTM neural networks. Shiping Wen et al. [115] implemented memristive LSTM network for sentiment analysis with a circuit diagram as shown in Figure 9d. The network weights are divided into two pieces and stored inside the crossbar, and the activation functions are implemented in part d, and the read and write circuits of the memristive crossbars are shown in the part e. Therefore, the final output voltage of the circuit can be obtained.
Based on the implementation of the above models, memristors can realize various biological tasks as basic units, such as brain-computer interface, pulse detection, epilepsy detection, etc. Among them, the brain-computer interface (BMI), as an important part of human understanding of neural signals, has the potential to restore lost motor function and explore the mechanism of brain function. However, to record more neural signals, the number of detection electrodes has increased exponentially, which also poses new challenges to the signal processing capabilities of BMI. The pulse signal processing module based on the memristor can avoid the limitation of transmission bandwidth, achieving better performance. Tsinghua University proposed an RRAM-based neural signal analysis system in 2020, [77] with the bio-plausible characteristics of RRAM cells utilized for pulse analog signal analysis. Memristors participated in the construction of FIR filter banks and SLP in BMI. The SLP is similar to the one mentioned above, and the memristor-based filter bank has the advantage of parallel analog computing, which can calculate multiple FIR filters at one time, and generate waves of the characteristic frequency of neural signals through the filters. First, the coefficients of the filter are mapped to the conductance in the crossbars, and then the analog voltage signal containing the brain state information is inputted to the crossbars, with the sum of output current corresponding to the filter result. Based on the built neural signal processing interface, the RRAM-based system implemented epilepsy-related signal filtering and recognition, reaching an accuracy rate of 93.46% on the Bonn epilepsy data set and energy efficiency of nearly 400 times of the advanced CMOS system. The structure of artificial neural network model is summarized in Table 1.

Spiking Neural Network
The spiking neural network is called the third-generation neural network. Different from traditional neural networks, spiking neural networks can encode a large amount of information on precise time steps and exchange information through spike sequences. In terms of physiological processing signals, spiking neurons have more advantages than artificial neurons such as bionics, [119] physiological signal processing, [120] and event-driven. [121]

Spiking Coding
The spiking neural network converts different physiological signals into neural codes that can be trained and inferred by the network. Currently, the common neural encoding methods mainly include rate coding, temporal coding, bursting coding, and population coding [122][123][124] (Figure 10a). Rate coding is the average of neurons firing spikes over the corresponding spike period. The magnitude of the spike frequency can reflect the intensity of the stimulus. The stronger the stimulus is, the more high-frequency pulse sequences are. Spike rate coding can be viewed as a quantitative measure of neuronal output. [125] The temporal coding method records the firing time of the neuron's first pulse. After the pulse is generated, the neuron is inhibited until the next stimulus arrives so that the temporal spike limits the computing power of neurons. [126] However, temporal spike coding assumes that the first pulse contains all information, which can encode the brain's visual signals.
Bursting coding is a neuron activity pattern that widely exists in the brain. Bursting mainly records the behavior of neurons firing pulses densely and rapidly for a while. Due to subthreshold membrane potential resonance in postsynaptic neurons, bursting coding can provide an effective coding mechanism for selective communication between neurons. [126] Population coding considers that the joint activities of multiple neurons represent the neuronal information. Population coding can calculate the activity intensity of each neuron based on the weighted sum of specific direction vectors. [127][128][129] Sparse coding is a special kind of population coding, which emphasizes that neuron information is only expressed by a small number of active neurons in the larger group. [69] The number of neurons in sparse coding is much larger than the input dimension. Sparse coding has been widely used in signal processing because of its overcomplete memory capacity and energy consumption.

Spiking Neural Network Topology
At present, spiking neural networks have developed complex and diverse topological structures. Considering the topology implementation and the updating speed of network parameters, the most commonly used feedforward and recurrent spiking networks have gradually become the basic components of complex structures. [130][131][132] The neurons are arranged in layers in the feed-forward neural network, and each neuron is combined in a fully connected form. The spiking sequence of the input layer represents the specific task encoding, the hidden layer's spiking sequence represents the information transmission, and the output layer's spiking sequence represents the network task results. [133] Different from traditional artificial neural networks, feedforward spike neural networks can have multiple synaptic connections between two neurons, and each synapse has different delay and modifiable connection weights. The advantage of multiple synapses is that impulses from presynaptic neurons can affect the firing of postsynaptic neurons over longer time scales. [134] Recurrent spiking neural network has not only a feedforward connection but also a feedback connection. This feedforward and feedback connection can simulate the recursive connection mode of brain neurons, and this connection mode exchanges information through action potentials, which are short electrical pulses. [134] Recurrent neural networks are mainly divided into the fully recurrent spiking neural network [135] and the locally recurrent spiking neural network. [136] The fully recurrent spiking neural network is generally a single-layer structure, such as the classical Hopfield neural network. [137] Its topology is shown in Figure 10b. The Hopfield network contains multiple neurons, and the output of any neuron receives feedback information from other neurons (including itself). Hopfield network structure can affect any output by all outputs so that each neuron restricts the other.
The fully recurrent spiking neural network is difficult to converge due to its complex structure, so the locally recurrent spiking neural network is produced. Based on the feedforward connection network, the locally recurrent spiking neural network adds the feedback connection between layers. As shown in Figure 10b, the input of the hidden layer of the locally recurrent spiking neural network is composed of the output spike sequence and the feedback spike sequence of the previous layer, which can be divided into external feedback recurrent structure and internal feedback recurrent structure. [138]

Learning Rules for Spiking Networks
Spiking neural networks with efficient hardware acceleration can enhance the learning capability of embedded intelligences. However, the current learning rules of spiking neural networks are very complex, and there are major challenges in network design and hardware implementations. Memristors are nonlinear circuit elements with memory and synapselike properties, which are suitable for accelerating spiking neural networks. In physiological signal detection, memristors can build dynamically tunable spiking neural networks and improve the learning efficiency of the network. At the same time, the memristor-based spiking neuron circuit has strong robustness and fault tolerance in simulating the operating mode of the brain. [139] At present, typical learning rules of memristor-based spiking neural networks include: unsupervised learning algorithm spike timing dependent plasticity (STDP) [140] and supervised learning algorithm remote supervised method (ReSuMe). [141] STDP learning rule is to adjust the connection between neurons according to the learning order of neurons. For any two neurons, if the presynaptic neuron pulse starts earlier than the postsynaptic neuron, the connection strength between neurons becomes larger, and vice versa. [142] Simple STDP learning rules perform poorly in actual tasks. Currently, improved STDP learning rules include event-driven STDP rules and adaptive threshold-based STDP rules. [143] Furthermore, to improve the performance of SNN on classification tasks, the convolutional network is combined with the SNN network, which can increase the depth of layers of spike convolution. [144] ReSuMe proposes a supervised algorithm to learn the complex spatiotemporal patterns of spike sequences. ReSuMe learning rule combines the processes of representing synaptic weights as STDP and anti-STDP. ReSuMe has online processing capability, stability of the optimal solution and independent learning rules for each synapse. [145] The adjustment of synaptic weights characterizes ReSuMe only depends on the input and output pulse sequences and has nothing to do with the neuron model and synaptic type. [146] In addition, supervised learning also has the spike pattern association neuron (SPAN) algorithm [147] and the chronotropic algorithm, [148] which can generate accurate spike time series. The structure of spiking neural network model is summarized in Table 2.

Application for Physiological Signals Processing
Physiological signals detection has a wide range of applications in the biomedical field. The electrical brain signals are the electrical signals generated by the human body due to brain activity, which can be specifically classified into electroencephalogram (EEG), electrocorticogram (ECoG), and local field potential (LFP) depending on the acquisition site. [158] The ECG is a signal of the heart's electrical activity recorded by a noninvasive device and has been used as an indicator of various heart diseases. The EMG is a bioelectric signal recorded along with muscle contractions and is now used as a control signal in many human-computer interaction projects. The EOG mainly records the standing corneal-retinal potential caused by hyperpolarization and depolarization between the cornea and the retina. Its primary use is to develop powerful eye-movement controllers for people with disabilities, as most can better control their eye movement system. [159] The PPG is a straightforward and low-cost clinical optical measurement technique that uses infrared light to measure volume changes in blood circulation and then analyzes the results to monitor critical physiological indicators such as heart rate.
People can monitor various physiological indicators of the human body by analyzing these physiological signals. However, the data analysis of a single physiological signal has its limitations. In some cases, guaranteeing the interpretation accuracy www.advelectronicmat.de may not be possible. Therefore, scientists are now exploring how to improve the interpretability and robustness of the analysis results through the fusion analysis of multiple physiological signals. For example, when pathological monitoring of cardiovascular diseases is carried out, PPG data and ECG data are usually combined for analysis to obtain stronger robustness (Figure 11a). [160] Although the method of multiple physiolog-ical signal fusion analysis can achieve higher robustness and interpretation accuracy, the fusion analysis of multiple physiological signals will inevitably cause large power consumption and long processing latency problems, which essentially limit the development of multiple physiological signals fusion analysis. Therefore, manufacturing low-power consumption and low processing latency systems that can perform Figure 11. Application of amnestic blockers for physiological signal detection. a) The overview of the ECG pattern recognition system based on analyzed ECG waveform and ECGref and dPPG/dt pattern. Reproduced under the terms of the CC-BY license. [160] Copyright 2018, The authors, published by MDPI. b) Biological and circuit schematic of spike neural network. Reproduced with permission. [167] Copyright 2020, Springer Nature. c) Framework of SNN system for automatic diagnosis of ECG arrhythmias. Reproduced under the terms of the CC-BY license. [55] Copyright 2022, The authors, published by MDPI. d) Schematic of amnestic blocker simulated biological synapse. Reproduced with permission. [168] Copyright 2014, IEEE. e) Micrograph of memristor array for SNN application. Reproduced with permission. [168] Copyright 2014, IEEE. f) CMOS neuron and memristor synaptic weight update circuit. Reproduced under the terms of the CC-BY license. [169] Copyright 2021, The authors, published by Frontiers. g) Schematic of CMOS-RRAM neural network. Reproduced under the terms of the CC-BY license. [169] Copyright 2021, The authors, published by Frontiers. multi-physiological signal fusion analysis have become a current research hotspot. Neuromorphic computing draws inspiration from the brain's mode of operation, simulating how information is processed in living organisms and constructing structures similar to biological neurons and synapses when performing computations [161] (Figure 11b). The most prominent result of neuromorphic computing in terms of algorithms is SNN. Since in SNN, spikes are mainly used for encoding and the time factor is incorporated into the working model, SNN is mainly applied to process discrete events occurring within a sequence of time. In addition to the EEG mentioned above, ECG, EMG, EOG, and PPG are also time-series data; thus, SNN has a strong potential for processing these physiological signals. Studies have used SNN to classify ECG signals with promising results [55] (Figure 11c). For these reasons, researchers are increasingly interested in neuromorphic computing, and many studies attempt to implement SNN on computational chips in real time and efficiently. Because the information transferred between spike neural networks and the memristors can be used to make synaptic connections (Figure 11d), they can play an essential role in the hardware for implementing spike neural networks. As shown in Figure 11f, the neural network is mainly composed of CMOS neurons, CMOS control circuits and memristor synapses. The SNN circuits and the role of memristors in them are shown in Figure 11g, and these studies indicate the strong potential of memristors crossbar array in hardware used for SNN applications. Some studies have developed SNN chips with specific functions based on related principles (Figure 11e). Neuromorphic computing draws inspiration from the operation mode of the brain and simulates biological neurons and synaptic structures during computing. The hardware platform of neuromorphic computing is mainly neuromorphic chips. Currently, many institutions in the world are developing neuromorphic chips, such as TrueNorth designed by IBM, SpiN-Naker designed by the University of Manchester, and Loihi designed by Intel. [162] Neuromorphic chips have many features of biomimetic neural networks, such as event-driven computing, spike information communication, and physical proximity between memory and computing units. In addition, it also has the advantage of real-time signal processing. Because of its excellent characteristics of low power consumption and low latency, the neural morphology chip has become a potential solution to prepare multi-physiological signals fusion analysis systems.
Memristor arrays have now been shown to have their own inherent stochastic characteristics that can be used to efficiently implement Bayesian neural networks and generative adversarial networks. [109,163] Previous studies have concluded that Bayesian neural networks and generative adversarial networks have robust applications in processing physiological signals. [164,165] Similarly, memristors, because of their inherent dynamic properties and nonlinearity, have been considered for hardware implementation of reservoir computing, [166] which have made significant progress in real-time neural activity analysis, among others. [78] Memristor arrays have great potential to build energy-efficient and low-power physiological signal processing platforms in real time.

Brain-Computer Interface
Brain-computer interface (BCI) is a technology that originated in the 1970s and can establish a connection between the brain and the computer. It can parse the electrical we can understand signals in brain activities into information. We can interpret the ideas of BCI system users through the parsed information, and this process does not require neuromuscular control (Figure 12a). [170] BCI systems may reflect users' intentions by analyzing electrical signals in brain activities. Thus, it has the potential to help patients who cannot communicate with others due to diseases such as cerebral palsy and brain stem stroke that cause neuromuscular necrosis. [171][172] These application scenarios of BCI are mainly based on the development of current human brain physiological signal detection technology. Because the current BCI systems mainly parse the electrical signals in brain activity while considering the safety of electrical brain signal acquisition, most current BCI systems are developed based on EEG. With the development of semiconductor technology and computer science, scientists have developed robust algorithms and incorporated them into the latest semiconductor technology to develop more powerful physiological signal monitoring systems. They can rely on them to develop a new BCI system.
EEG is mainly divided into spontaneous EEG and evoked EEG, and these two kinds of EEG have developed corresponding BCI systems according to their own physiological signals detection systems. The BCI systems based on spontaneous EEG detection are mainly motor imagery BCI systems, [173] while the BCI systems based on evoked EEG detection are mainly visual stimulation BCI systems. [174] Currently, BCI systems developed based on motor imagery mainly manufacture a device that can recognize the motor intention of human hands. With the development of EEG detection technology and fast data processing module, users can monitor their EEG more conveniently in daily life. [173] Users are expected to control the mechanical arm independently. BCI systems based on visual stimulus mainly use brain responses, such as P300 and steady state visual evoked potential (SSVEP), to reflect the user's intention in brain activities by observing visual stimulus. In order to widely deploy BCI technology, sufficient high-precision information transmission capability is required. P300 and SSVEP are the main paradigms of BCI based on visual stimulation. Thus, we are supposed to compare them to select a better paradigm for BCI systems. After comparison, SSVEP has high communication speed and fewer user training requirements. [175,176] In addition to the abovementioned applications, EEG-based BCI systems have shown great potential in various applications, including post-stroke treatment [177] and emotion recognition. [178] With the rapid development of EEG acquisition technology, the number of EEGs are increasing significantly, which has higher requirements for EEG processing systems. At the moment, the traditional EEG processing systems may give rise to many problems such as long latency and large power consumption. Therefore, it is urgent to develop new EEG processing systems to meet the demands of high-speed and high-throughput EEG. The data processing process of EEG is mainly carried out for feature extraction, and deep neural networks are mainly used in this process for end-to-end deep www.advelectronicmat.de learning. [179] This suggests that the most essential and computationally expensive EEG processing operations are the multiplyaccumulate (MAC) operations. Thus, it is an attractive idea to accelerate the MAC operations in EEG processing. The MAC operations can be mapped to the memristor array through Ohm's and Kirchhoff's law (Figure 12b). Therefore, memristor arrays can provide low power consumption and low latency computational capabilities by implementing MAC in parallel in the analog domain, and it can break the limitations brought by the traditional Von Neumann architecture through in-memory computing. [180] Several studies are experimenting with memristor arrays to build efficient EEG data processing platforms. [28] In this study, the scientists developed a board-level verification system embedded in a 1T1R array to test the properties of memristors. Then they proposed a highly robust hybrid neural network structure based on the 1T1R array called the DSC-BiGRU network and analyzed its accuracy, network size, and robustness. In addition to the fact that memristor arrays can accelerate MAC operations, existing studies have demonstrated that 1T1R memristor arrays can also build multichannel parallel processing systems for neural signals, [15] as shown in Figure 12c. Such systems can excel in linear classification and have been used to predict epileptic seizures (Figure 12d,e). These studies show that memristors have a strong potential for constructing real-time processing systems for EEG signals. Besides using memristor arrays to speed up MAC-based the EEG data processing, there are also some research being done that use other neural networks for processing EEG signals. This is where spike neural networks (SNN) come into the picture for scientists, also known as third-generation neural networks, [181] mimic how information are encoded within biological systems. Like the brain, SNN encodes information through a time sequence of spikes. Thus, scientists thought using SNN to process EEG signals may lead to better results. Therefore, developing new SNN algorithms and architectures to effectively process EEG signals became a research problem at that time. Kasabov developed a new SNN architecture called Neucube to process EEG signals, and achieved great results (Figure 12g). [182] The SNN architecture of Neucube is shown in Figure 12f, which mainly consists of three modules: input data encoding Figure 12. Brain-computer interface system. a) Basic design of the brain-computer interface system. Reproduced with permission. [187] Copyright 2020, IEEE. b) Schematic diagram of the memristor array to implement vector matrix multiplication. Reproduced with permission. [180] Copyright 2018, Springer Nature. c) Multichannel processing system for neural signals. d) Training results of LDA classifier on channel signal segments and test results of trained LDA classifier on partial channel signal segments. e) Training and test accuracy of tenfold cross-validation multichannel processing system for neural signals. (c-e) Reproduced under the terms of the CC BY-NC license. [15] Copyright 2020, Science Press. f) Schematic diagram of SNN architecture of Neucube. Reproduced with permission. [182] Copyright 2014, Elsevier. g) Schematic of using Neucube for EEG analysis of brain-computer interface system. Reproduced with permission. [182] Copyright 2014, Elsevier. h) Schematic of brain-computer interface system for speech decoding. Reproduced with permission. [183] Copyright 2019, Springer Nature. www.advelectronicmat.de module, 3D SNNr module and output function module. Some researchers are trying to build an efficient EEG data processing platform using memristor arrays, which are also significant to developing BCI systems based on EEG.
There is currently some research on BCI systems based on detecting other types of electrical brain signals that can improve people's lives. In a recent study, [19] researchers researched the use of BCI to improve communication between patients unable to speak or move due to physical paralysis. The researchers asked the subjects to imagine holding a pen and writing sentences on paper as if they were not paralyzed. In the process of practice, this BCI system will use a neural network, that is, a machine learning method, to convert the action of intentional handwriting in neural activities into text in real-time. The final typing speed can reach 90 characters per minute, with an accuracy rate of 94.1%. This speed is very close to the average typing speed of the same age group (115 characters per min). This typing speed reaches 150 words per min, close to the level of ordinary people. [183] The results of this study show that BCI can help paralyzed patients establish a bridge with others. In other studies, researchers built a BCI system to decode brain activities to improve speech clarity and used deep learning methods to direct the conversion of brain signals into intelligible synthetic speech (Figure 12h).
The above research shows that in addition to helping paralyzed patients communicate with the outside world, BCI systems can also help patients with several other diseases. In addition, BCI has also improved the lives of the elderly. [184] With the growth of age, the functions of the human brain and body will continue to decline. However, as caring for the elderly requires a lot of energy and time, the related services are usually expensive, so many older adults cannot be cared for. In this case, BCI technology can help the elderly in many ways, such as helping them control household appliances, using mechanical arms to help them better complete their behavior, and using wheelchairs that their brains can control to help them solve their travel problems. Alzheimer's disease (AD) is prevalent in the elderly. [185] BCI can be used to detect early AD. This is an essential thing because Alzheimer's disease is likely to be treated with drugs in the early stage. The BCI systems developed in these studies illustrate how monitoring electrical brain signals can help improve people's lives in many areas.
Although many achievements have been made in the research of BCI systems, including advanced algorithms and broad application scenarios, there are still many problems and challenges in developing BCI systems based on detecting electrical signals in the brain. Traditional BCI systems perform data processing mainly by collecting the data, then transmitting the collected data to an external server for data calculation and processing off-chip, and finally returning the processing results to the device. However, using traditional remote servers and signal processing technologies to process these real-time data may produce intensive computing phenomena. It may lead to long data processing latency, slow system operation, large power consumption, and hardware occupation. [186] In this case, edge computing has become a desirable solution, which can shorten the system running time of BCI systems and allow the development of online BCI systems that can continuously interact and learn from the environment and update themselves. At present, edge computing systems usually need low-power compact devices, which can provide powerful computing power on BCI systems while reducing the data processing latency. However, if edge computing is to be used as the data processing method of BCI systems, then how to work within strict power and area constraints to handle large amounts of data becomes the bottleneck for manufacturing-related BCI systems, which also opens the way for research beyond CMOS solutions. At present, a very attractive solution is to use memristor devices. Although memristor devices are still in the early stage of technology development, they are currently considered ideal devices for edge computing due to their small size, low power operation, good compatibility with CMOS manufacturing processes, and volatile/nonvolatile characteristics. [82] Through the above work, we can assume that advanced devices such as memristors have promising applications in BCI systems for electrical brain signal detection.

Neuroprosthetics
Neuroprosthetics mainly refers to using electronic devices to replace the function of the damaged nervous system or sensory organs (Figure 13a). In addition to the possibility of replacing sensory organs, neuroprosthetics are now considered to provide new ideas for treating various neurological-related diseases, such as brainstem stroke, amyotrophic lateral sclerosis, [188] etc. (Figure 13b,c). The most successfully researched neuroprosthetics are for patients with impaired sensory organs, such as cochlear implants and wearable leg neuroprosthetics. [188,189] In addition to the previous research, current studies are trying to develop visual prostheses to help blind people see the world again. Neural spike detection is very important in developing neuroprosthetics for treating neurological disorders, focusing on detecting the timing of the spike delivery of individual neurons. Neural spike sorting is required after their acquisition to distinguish the firing activity of different neurons and to assign the recorded spikes to the individual neurons in the recording, which is the basis for decoding the neural activity in neuroprosthetics. However, large-scale real-time processing of neural signals may lead to problems such as large power consumption and low signal-to-noise ratio, [190] which also pose challenges for developing neuroprosthetics based on real-time neural spike signals. A potential solution is to implement neural spike detection and storage using memristors. In addition to implementing MAC operations based on Ohm's law and Kirchhoff's law, memristor arrays can be used to detect and store neural spikes potentials based on their rich internal dynamics brought by physical state changes, [191,192] and memristors can compress and store the information through resistance changes. Also the use of memristors for correlation operations has advantages such as low power consumption and good scalability. [193] In earlier studies, the inherent suprathreshold integration property of TaO x -based memristors was used to detect neuronal spikes, [193] after which studies implemented the use of 1T1R structured memristor arrays for neuronal spike detection [194] (Figure 13d), as well as studies that have developed closed-loop neurostimulators based on memristors and that allow real-time monitoring of neuronal populations, which also demonstrate the strong www.advelectronicmat.de potential of memristors for the fabrication of low-power realtime neuroprosthetics.

COVID-19 Detection and Patient Physical Status Monitoring
In late 2019, the virus called SARS-COV-2 emerged and quickly swept the world. Moreover, the disease it caused became the infectious disease now widely circulating worldwide, named COVID-19 by World Health Organization. According to the World Health Organization, more than 630 million people worldwide have been infected or have been infected with COVID-19, and it has caused more than 6 million deaths (https://covid19.who.int/). There is still no way to eradicate it, so the detection of COVID-19 has become an issue of concern worldwide. The most traditional way to determine if you have the disease is still the collection of secretions from the human body, which is then tested for nucleic acids. [195] However, since nucleic acid-based diagnostics take a long time from secretion collection to results and require visits to specific sites, there is no way to monitor human status in real-time. Also, patients with COVID-19 need to be isolated to prevent them from infecting others, so it will be necessary to efficiently allocate healthcare resources if people's COVID-19 status can be detected in real-time or predicted. Because of the abnormalities in the physiological indicators of people diagnosed with COVID-19, many studies are currently trying to detect and predict COVID-19 disease in users based on the monitoring data of human physiological signals and to monitor the health condition of patients diagnosed with COVID-19 in real-time in order to tailor individualized medical treatment. Current research has already been done in this area, where researchers have analyzed the data collected and found abnormalities in respiratory rate, heart rate, and HRV in COVID-19 patients, so they have collected the data and trained a convolutional neural network (CNN) to predict the disease at any given date, [196] and the architecture is shown in Figure 13e. This also indicates that CNN has a strong potential for COVID-19 detection simultaneously. The specific determination still needs to be made by  [197] Copyright 2021, The authors, published by Springer Nature. b) Wearable leg neuroprosthetics. Reproduced under the terms of the CC-BY license. [188] Copyright 2022, IOP Publishing. c) Device for electrical stimulation of human auditory system. Reproduced with permission. [83] Copyright 2009, Springer Nature. d) Schematic diagram of spike detection using 1T1R memristors. Reproduced with permission. [194] Copyright 2020, IEEE. e) Neural network architecture of COVID-19 prediction system. Reproduced under the terms of the CC-BY license. [196] Copyright 2020, The authors, published by Springer Nature. f) CNN-LSTM network structure for ECG signal classification of COVID-19 patients. Reproduced with permission. [29] Copyright 2021, Springer Nature. g) Topology diagram of LSTM neural network structure implemented in memristors crossbar array and data flow. Reproduced with permission. [116] Copyright 2019, Springer Nature.

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nucleic acid-based diagnostics, but it provides a promising idea for preventing and treating infectious diseases such as COVID-19. After a patient is diagnosed with COVID-19, scientists can use CNN and long short-term memory networks (LSTM) to monitor the patient's health in real-time so that medical practitioners can design individualized medical treatment for the patient [29] (Figure 13f).
Since COVID-19 is widely contagious and mutable, both COVID-19 disease determination and patient monitoring should minimize time consumption to enable timely treatment of patients, and it is desirable to have a small size and low power consumption so that users can use the device for a long time. It can be seen that CNN can play a crucial role in detecting COVID-19 disease and monitoring patients' physical condition by detecting physiological signals such as heart rate. Memristor-based neuromorphic computing systems are considered a potential solution to this problem because the convolution process of CNN has a large number of MAC operations, and the memristor array can realize the in-memory MAC operations by Ohm's law and Kirchhoff's law to reduce the power consumption and latency caused by data shuffling. [76] It has been shown that CNN can be fully hardware implemented by memristors, which also indicates that memristors have great potential for COVID-19 detection and patient body condition monitoring. It has also been demonstrated that LSTM can also be efficiently implemented by memristors crossbar array (Figure 13g). [116] These studies illustrate the great potential of memristors crossbar array for COVID-19 detection and patient physical condition monitoring.

Seizure Detection
Epilepsy is a chronic disease characterized by abnormal discharge of brain neurons. Typical symptoms include convulsions, rigidity, and loss of consciousness, which harm patients and their families. There are approximately 1% of people in the world suffer from epilepsy. Accident seizure detection methods are required to monitor the patients continuously and provide timely treatment. However, such methods are typically computationally expensive, which is not friendly for a resource-limited scenario such as closed-loop neuromodulation devices. [198][199][200] As shown in Figure 14a, a typical closed-loop neuromodulation device requires low power and low latency. In order to meet such requirements, novel NVM devices can be used to do seizure detection in a rapid and power-saving way.
Liu et al. demonstrated memristor-based brain-machine interfaces for seizure detection. [77] Figure 14c-e demonstrates their brain-machine interface concept and the system flow for seizure detection. They first used memristor arrays to construct four FIR bandpass filters. The input analog neuronal signal can be divided into the delta, theta, alpha, and beta, four different frequencies using these four filters. Then the biomarkers are extracted from the filtered signal. After that, they constructed a memristor-based single-layer perceptron for the brain state classification. They claimed their memristor-based system achieved about 400 times power efficiency compared to traditional CMOS circuits. There are two main reasons for the low power consumption. First, the analog signals are processed in the analog domain directly to avoid ADC energy consumption. Secondly, Figure 14. a) A typical closed-loop neuromodulation device architecture. Reproduced with permission. [198] Copyright 2018, IEEE. b) The proposed in vivo and in vitro concept of neuromodulation device. Reproduced under the terms of the CC-BY license. [201] Copyright 2022, The authors, published by American Chemical Society. c) The memristor array is analogous to the biological neural network, and the memristor's mechanism is similar to the biological synapse. d) The concept of the proposed brain-machine interface. e) The proposed seizure detection system flow. (c-e) Reproduced under the terms of the CC-BY license. [77] Copyright 2020, The authors, published by Springer Nature. www.advelectronicmat.de the memristor crossbar can perform in-memory computations, saving the energy consumption of frequent memory access in traditional Von Neumann architecture. As proof-of-concept work, some segments in the whole system such as biomarkers extraction are done in the software. Li et al. proposed a parallel convolutional neural network on memristor arrays for seizure detection and prediction. [202] To compensate for the accuracy loss due to digital-analog conversion and non-idealities of memristor arrays, they adopted quantization-aware training (QAT) and proposed a weight-offsetting method. Finally, the proposed network includes fewer parameters but achieves comparative results to the state-of-the-art methods. And by paralleling the different convolutional kernels on separate memristor arrays, the latency of the proposed network decreased two orders of magnitude than the previous memristive-CMOS architecture. It is noticed that the memristor part in this paper is based on the simulation. Zhang et al. designed a seizure detection system based on memristor arrays and integrated the system on a PCB board. [202] The system includes data preprocessing, short-time Fourier transform and memristor-arraybased CNN calculations. The FPGA on the board is responsible for controlling the whole flow and there are ADC/DAC circuits for interacting with the memristor array. The 1T1R memristor array they used achieves lower power consumption than CMOS circuits and shows promising detection performance, making it the ideal choice for wearable epilepsy devices.
Besides deep learning methods mentioned above, the reservoir computing system based on memristors is also an effective method for seizure detection. A typical reservoir system is composed of randomly connected recurrent neurons, which can nonlinearly map the input features into high-dimensional space. Moreover, in a reservoir computing system, the current state is affected by the input and previous states, enabling the system to behave in short-term memory. [166] Kudithipudi et al. designed a reservoir computing architecture for seizure detection. [17] They investigated several reservoir topologies and proposed a hybrid reservoir topology with more synaptic connections. The extra connections can facilitate the information exchange in the reservoir system and improve performance. They used a model to simulate the behavior of the memristor and then implemented the system on FPGA for hardware evaluation. They also proposed using a memristor crossbar to process the output of the reservoir system to further reduce the area cost. In the end, the system achieves reasonable detection accuracy and relatively low power.
There are other methods combined with NVM devices to deal with seizure detection. Dias et al. proposed using a memristor as a microprocessor to receive the signal and activate stimulations. [203] As shown in Figure 14b, their concept is to implement the closed-loop neuromodulation system in the brain. Furthermore, they used rat hippocampal neurons to do an in vitro experiment. The abnormal electrical activity of hippocampal neurons will set the memristor to the ON state, triggering the electric stimulation. When the hippocampal neurons are at the normal state, the memristor will transfer to the OFF state, thus cutting off the stimulation. Schindler et al. used hyperdimensional computing to detect seizures. [204] They claimed that hyperdimensional computing combined with a crossbar array could achieve high energy efficiency. The hyperdimensional vector is robust for noise interpretation and tolerated for vector superimposition, which is suitable for memristor crossbar implementation. The seizure data are mapped to hyperdimensional vectors and then these vectors are combined in the time domain and space domain. The hyperdimensional vector extracted from the seizure region is used as a prototype. The prototype is deployed to distinguish the seizure vector and the normal vector.
Seizure detection is a prudent medical problem with many strict evaluation criteria. Though some NVM devices based seizure detection methods are proposed, most are proof-of-concept trials based on simulations and PCB board-level integrations. Moreover, they lack a complete assessment of the results. Thus, a more complete and practical memristive system is required. The memristor-based in-memory-computing chip is an attractive research direction, due to its high energy efficiency and fast response for seizure detection.

Arrhythmia Detection
Arrhythmia is a common heart disease, which can cause a risk of sudden death. Real-time monitoring is significant for the treatment of arrhythmia. Electrocardiogram (ECG) is a biomedical signal to record the heart's electric activity. Observing the ECG wave can identify some heart diseases like arrhythmia. However, manual monitoring of ECG will be time-consuming and expensive. Thus the automated ECG monitor is necessary. There is a trend to integrate memristors into the automated ECG-based arrhythmia detection system due to the abundant characteristics of memristors. [205][206][207][208][209] Zhong et al. proposed a fully analog reservoir computing system for arrhythmia detection. [210] They integrated the analog reservoir, analog readout circuits, and STM32 on a single PCB board. The STM32 controls the flow, and masks are deployed to increase the reservoir states. Some noises are added during the training process, where the noise is used to simulate the device variation and mapping error. The experiment shows that the added noises improve the system's performance. The input and output signals of the proposed reservoir computing system are shown in Figure 15b. Compared with a digital system, the proposed fully analog system does not need ADC, which can save power and lower hardware costs, making it suitable for edge devices such as wearable ECG monitors. The comparison between different systems is demonstrated in Figure 15a. The authors claimed that the power of a fully analog system is three orders of magnitude lower than that of a digital system. Hassan et al. designed a two-layer connected memristor crossbar to detect arrhythmia. [204] They first designed a two-layer feed-forward neural network in the software and then implemented two-layer weights in two connected memristor crossbars. The accumulated current in the column of the array is connected to the summation amplifier. The IV curve of the summation amplifier here resembles the activation function tanh. Their experiment shows that memristors' variation degenerates the system performance but is still within a reasonable range. The system demonstrates a good trade-off between power and detection accuracy. Liu et al. used memristive fiber to construct textile memristors and demonstrated the potential to integrate www.advelectronicmat.de the textile memristor into smart clothes for arrhythmia detection. [211] The interwoven fiber naturally forms a crossbar array and shows good uniformity, which can be used as flexible processors. As a proof of concept demonstration, their arrhythmia detection result is based on software simulation. The simulation results show that the flexible memristor array can achieve reasonable accuracy.
Spiking neural network(SNN) is an emerging deep learning method inspired by biology and it shows significant advantages in low-power computing. Jiang et al. proposed to use of memristor crossbar-based SNN for arrhythmia detection. [205] Figure 15c demonstrates the computing process of the proposed SNN. The ECG data will be encoded to spikes first. And then, the spikes pass five convolution blocks, two fully connected blocks, and an output layer. The block contains an integrative unit and an adaptive unit. The integrative unit is responsible for integrating the information from the previous block and the adaptive unit is responsible for extracting features further. The SNN network is mapped on the memristor crossbar, as shown in Figure 15d. The accumulated current in the crossbar will be applied to LIF neurons, and once it is above the threshold, the neuron will fire. The system achieves 92.25% accuracy and low energy consumption, making it suitable for edge devices.
The memristor array and its internal dynamics like the reservoir show promising power and hardware cost advantages on wearable devices for arrhythmia detection. However, it is worth noting that the robustness of the memristive system needs to be further improved. It still takes a lot of effort to realize commercial memristor-based ECG wearable products.

Skin Temperature Detection
Skin temperature is an essential physiological indicator. It can reflect whether people are healthy and whether the abnormal temperature is a precursor of disease. Thus it is necessary to monitor skin temperature in real-time. The emerging devices provide a new choice for skin temperature detection in an energy-efficient way and the flexibility of some emerging devices shows excellent potential for wearable devices.
Bae et al. propose a sensor array for skin temperature monitoring. [212] The sensor array comprises multiple 1-thermistor and 2-memristor(1T-2 M) components. The unit thermistor is a carbon nanotube-based temperature sensor (CTS). The CTS is fabricated using multi-walled carbon nanotubes (MW-CNTs) and PDMS. It shows an excellent linear relationship between resistance and temperature, which makes it a suitable thermistor. Moreover, the structure of the memristor is Al-pEGDMA-CTS. The memristive characteristic is due to the formation and rupture of carbon filament in pEGDMA. As shown in Figure 16a, the intertwined CTS wires and Al-pEGDMA yarn can form the temperature sensor array. Figure 16b,c shows the details of the thermistor and memristor. When in operation, the two memristors will be set to a low resistance state (LRS) first, and then the sensing voltage will be applied to the CTS wire.  [210] Copyright 2022, Springer Nature. c) The proposed SNN computing process. d) The SNN network is mapped on the memristor crossbar. (c, d) Reproduced under the terms of the CC-BY license. [205] Copyright 2021, The authors, published by Frontiers Media S.A.

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Finally, the output current level will reflect the temperature. Compared with commercial temperature sensors, the proposed sensor array achieved comparable performance. Moreover, the flexible sensor arrays are built on cotton fabric, demonstrating its advantages on wearable devices. Rahman et al. proposed to use the memristor and thermoreceptor to mimic the thermoreceptor. [213] They connected the VO 2 resistor and memristor in series. Initially, the VO 2 resistor and memristor are in high resistance. When the appropriate temperature (70 °C in ref. [213]) is applied to the VO 2 resistor, the resistance of the VO 2 resistor will decrease by four orders of magnitude. Moreover, thus, the partial voltage on the memristor surpasses the SET threshold and triggers the memristor to transfer to LRS. It is noted that the transition temperature of the VO 2 resistor can be adjusted by introducing dopants. Therefore, it can be adjusted to the human temperature range as artificial skin receptors for temperature detection.
The temperature sensor is responsible for sensing temperature and memristor devices are responsible for controlling and processing. Memristor-based temperature detection system includes temperature sensors and memristor devices. A similar system architecture can also be deployed in other sensor systems such as pressure sensors and nociceptors.
With the development of novel NVM devices, sensing and computing could be fused in the future. The ADC would be removed and the computing would be processed in memory. Thus the power and hardware cost could be decreased further.

Respiration Monitoring
Respiration is an essential physiological signal. Therefore, it is necessary to find an efficient way to monitor breathing. Real-time monitoring of respiration can help people discover diseases such as sleep apnea syndrome, potentially leading to cardiovascular disease, brain injury, and stroke. Recently, novel NVM devices have provided a low-cost, eco-friendly, and sustainable way for respiration monitoring.
Song et al. fabricated a humidity sensor based on the Y7C peptide for sensing human respiration. [216] The humidity can change the charge flow in the Y7C peptide. For exhalation, the humidity near the sensor increases, and the current in the sensor increases. For inhalation, the decreasing humidity of the air causes the current to decrease. The humidity sensor based on the Y7C peptide also shows memristive characteristics. Therefore, it is possible to integrate neuromorphic computing and humidity sensing to achieve in-sensor computing. Moreover, the memristor and sensor based on Y7C peptide can be fabricated on silk substrate and are fully dissolvable, which can minimize side effects. Fu et al. proposed a neuromorphic interface for breathing monitoring. [214] The memristor fabricated by them is made of protein nanowires. Compared with traditional memristors, their protein nanowires-based memristor can operate under bio-amplitude (sub-100 mV), thus not needing pre-amplification circuits, which can save power. Figure 16c demonstrates their integrated neuromorphic interface. The interface consists of parts: receptor, neuron, and Reproduced with permission. [212] Copyright 2017, IEEE. c) The proposed integrated neuromorphic interface. d) The membrane voltage and output current of the neuron under abnormal breathing. (c, d) Reproduced under the terms of the CC-BY license. [214] Copyright 2021, The authors, published by Springer Nature. e) The architecture of the CIM engine. Reproduced with permission. [215] Copyright 2022, IEEE.
www.advelectronicmat.de backend control. A planar protein nanowire sensor is used as the receptor for the respiration monitor interface. A neuron composed of a memristor and a capacitor is served as the neuron and a LED circuit for neuron firing visualization is adopted as the backend circuit. The planar protein nanowire sensor can transfer respiration into spike voltage. The standard spike voltage will cause a stable membrane potential if respiration is normal and slow. However, if respiration is abnormal and fast, the rapid spike voltage will trigger the neuron to fire and light the LED. The results of abnormal respiration are shown in Figure 16d. The protein nanowire in this paper can harvest energy from humidity and is environmentally friendly, making it become the ideal candidate for wearable devices.
The artificial neurons based on novel non-volatile memory devices exhibit the advantages of low power and flexibility on respiration monitors. However, the current memristor-based respiration monitor is simple, and cannot accomplish complicated detection tasks. To deal with this problem, spiking-based neuromorphic computing systems could be used to detect diseases such as sleep apnea syndrome based on respiration monitoring.

Gesture Recognition
Electromyography (EMG) is a signal which reflects the current on the human body surface. The functionality of neurons and muscles can be judged through EMG. An EMG can also be used as the control signal of the human-computer interface; the typical application scenario includes prosthetic finger control [205] and hand gesture recognition. [216] Tian et al. [215] proposed a compute-in-memory engine for EMG-based hand gesture recognition. Figure 16e illustrates the whole system flow. The EMG data can be encoded into spikes using the Poisson spike encoder. Then the encoded spikes can pass the memristor crossbar, where the SNN weights have already been mapped. The MAC (multiply and accumulate) operations are processed parallel by the crossbar, and the accumulated output current on the BL line represents the results of MAC operations. All MAC operations could complete within one read period. Moreover, the MAC operations in the crossbar avoid frequent memory access in traditional Von Neumann architecture. After MAC operations, the output current is connected with the multiplexer block and subtraction circuit, which generates the pre-synaptic stimulus current. The stimulus current is sampled and processed by the LIF neuron. If the integrated current surpasses the threshold value, the neuron will fire. The CIM engine achieves an accuracy of 85.6% and shows good power efficiency, which makes it suitable for edge devices. Except for seizure detection, the proposed reservoir topologies can also be used for prosthetic finger control. [17] The authors used five classes of finger motion data and achieved a classification accuracy of 84%, indicating the feasibility of using the reservoir to process EMG data.
The EMG signal is a kind of non-invasive bio-indicator. It is easy to measure and the measurement devices are portable. Due to its low power consumption and hardware-friendly characteristics, the memristor-based in-memory-computing system coupled with artificial neurons is a promising method for processing EMG signals. Further research on building a more efficient gesture recognition system is required.

Conclusions
With the rapid developments of physiology, artificial intelligence, and other related fields, the proliferation of data volume and the increased computational task complexity put higher requirements for on-chip computational power and energy efficiency. This review aims to provide a new perspective on physiological signal processing from microscopic device characteristics to macroscopic memristor-integrated networks. At the microscopic level, memristors have good linearity, durability, and retention properties as a passive circuit device. This makes memristor promising for in-memory computing and near-memory computing. Physiological signal detection devices will gradually be used in end-to-end applications, so memristors are able to play their advantages of low power consumption and high energy efficiency. At the macroscopic level, with significant advantages in energy efficiency memristor devices, memristor-based neural networks are expected to be a new computing architecture in the era of brain-inspired computing and artificial intelligence.
Furthermore, the memristors can simulate cellular neurons and synaptic properties to build computational systems with complex information-processing capabilities. The memristor array can promisingly alleviate the data movements bottlenecks between storage and computation and integrate sensing and computation together to address high power consumption and high latency problems in physiological signal processing. In addition, neural network chips based on memristor devices enable the terminalization of artificial intelligence systems with human-like associative memory. This paper mainly reviews the progress of ANN and SNN with memristor neural networks. The development of ANN and SNN networks has gradually moved toward larger models and higher complexity. However, the computational power at the edge are constrained. Memristors are expected to solve these drawbacks, allowing complex AI models being adopted for different application scenarios.
Moreover, the gap between memristor device integration and the mature CMOS-based device integration is still a challenge, where the lack of neuronal loops is an important obstacle, which makes the memristor network currently underdeveloped in terms of online training. So far, most of the memristor networks for physiological signal detection, whether using ANN or SNN, are focused on the inference stage. Memristor neural networks will rise up in training as memristor integration improves, providing more supports in both inference and training for physiological signal processing.
Finally, physiological signal processing is widely used in the biomedical field and the advancements in integrated memristor networks promote the hardware developments of physiological signal processing. Physiological signals can be used as indicators of human's physical or mental states. Memristors, a novel hardware component that combines storage and computing, are critical in improving the efficiency of physiological signal processing hardware systems. In multimodal physiological signal processing, memristors can process data with lower www.advelectronicmat.de power consumption and higher robustness to provide timely diagnostic information for doctors. In the future, the applications using memristor networks in physiological signal processing will make greater progress and eventually become a significant breakthrough.