Logic‐In‐Memory Characteristics of Reconfigurable Feedback Field‐Effect Transistors with Double‐Gated Structure

The reconfigurable feedback field‐effect transistors (R‐FBFETs) with a double‐gated structure are designed and the logic and memory operations of a logic‐in‐memory (LIM) inverter comprising two R‐FBFETs are investigated. The R‐FBFETs exhibit an extremely low subthreshold swing of ≈1 mV dec−1, a high on/off current ratio of ≈107, and a long retention time of 10 s, owing to a positive feedback loop mechanism. The on‐current ratio of the p‐ to n‐channel modes is 1.03, which indicates a high degree of reconfigurability. The LIM inverter retains the output logic “1” and “0” states for over 50 s under zero‐bias conditions. The symmetric reconfigurable switching and memory operations of the R‐FBFETs enable the LIM inverter to perform logic and memory operations for a long retention time without a power supply.

In this study, we designed double-gated R-FBFETs and a LIM inverter comprising these R-FBFETs, as shown in Figure 1. Two 3 μm wide poly-Si gates were arranged side-by-side on the intrinsic channel region and the separation between these gates was 1 μm. The poly-Si gates near the p + drain and n + source were designated as Gates 1 and 2, respectively. The channel mode of the R-FBFET depended on the input voltage. In the p-channel mode, the drain-source voltage (V DS ) and Gate 1 voltage (V G1 ) were applied while Gate 2 was grounded. In contrast, in the nchannel mode, the source-drain voltage (V SD ) and Gate 2 voltage (V G2 ) were applied while Gate 1 was grounded. We examined the reconfigurability of double-gated R-FBFETs and investigated the LIM characteristics of an inverter comprising two double-gated R-FBFETs. Figure 2 shows the optical image (a) and reconfigurable switching characteristics (b,c) of the double-gated R-FBFET. In the V G1 (V G2 ) sweep from 2 V (−2 V) to 0 V, the transistor in the p-channel (n-channel) mode exhibited superior switching characteristics with an extremely low subthreshold swing (SS) of ≈1 mV dec −1 and a high on/off current ratio of ≈10 7 , owing to the generation www.advancedsciencenews.com www.advelectronicmat.de of the PF loop in the channel region. In the V G1 (V G2 ) sweep from 0 to 2 V (−2 V), the transistor in the p-channel (n-channel) mode remained in the "on" state because of the excess charge carriers in the potential wells of the channel region (see the band structures in Figure 3). The on-current ratio of the p-to n-channel modes was 1.03, which reveals a high degree of reconfigurability; the electrical symmetric behaviors of the R-FBFET take great advantages for implementing the logic gates. [29] Even when the gate length was changed from 1.0 to 3.0 μm, the reconfigurable switching characteristics of the R-FBFETs were nearly impervious as shown in Supporting Information. Although the device with a longer gate length was turned on at the larger gate voltage, the R-FBFETs exhibit the high symmetric on-currents in the p-and n-channel modes regardless of the gate length variation.

Results and Discussion
The memory characteristics of the R-FBFET in p-and n-channel modes are shown in Figure 3. Although the R-FBFET has a p + -i-n + structure, two heavily doped poly-Si gates induce virtual electrostatic doping in the intrinsic channel region. Thus, the n-doped Gate 1 and p-doped Gate 2 induce electrons (n*) and holes (p*), respectively, in the intrinsic channel region. In the pchannel mode (Figure 3a), during the write operation, the applied voltages (V DS = 1 V and V G1 = 0 V) induce the injection of excess charge carriers, thereby generating a PF loop in the channel region, and the transistor is in the "on" state. During the hold operation, applying V DS = 0 V and V G1 = 1 V maintains the excess charge carriers in the potential wells in the channel region. After holding the "on" state, the read current of the "on" state reached ≈1.8 μA μm −1 under the read condition (V DS = 1 V and V G1 = 1 V). The erase operation was performed at V DS = −1 V and V G1 = 1 V, under that condition the excess charge carriers are removed in the potential wells while restraining the carrier injection. After the hold operation, the read current was measured at a low level, indicating the "off" state. The difference in the read currents between the two states originates from excess charge carriers in the potential wells and the differential potential barrier height. For the "on" state, the excess charge carriers in the potential wells reduce the potential barrier height such that the PF loop can be generated under the read condition. In contrast, for the "off" state, the high potential barriers caused by the absence of the excess charge carriers in the potential wells prevent the generation of the PF loop during the read operation.    is similar to that in the p-channel mode. During the write operation, the transistor turned on with the generation of the PF loop. After the hold operation, the transistor remained in the "on" state, and the reading current reached ≈1.5 μA μm −1 under the read operation. After the erase operation, the low-level current was measured during the read operation. Consequently, the R-FBFET performed symmetric memory operations owing to the PF loop mechanism and double-gated structure. In spite of the relatively small on-current magnitude (≈2 μA μm −1 ), the R-FBFET can perform reliably reconfigurable memory operations owing to the extremely low subthreshold swing and high on-off current ratio. Figure 4a,b show the retention characteristics of the R-FBFET in the "on" state for the p-and n-channel modes, respectively, after a holding time of 10 s. During the hold operation, excess charge carriers remain in the potential wells of the p*-n* electrostatic doping region for both channel modes. Despite the recombination of excess charge carriers, a small amount could generate a PF loop under the read condition. Figures 4c,d demonstrate that the transistor maintained in the "off" state after 10 s for both channel modes. This implies that the potential barriers of the p*-n* electrostatic doping region effectively prevent excess charge carrier injection. Consequently, for all the states and channel modes, the R-FBFET exhibited outstanding retention characteristics owing to the p*-n* electrostatic doping region.
Two R-FBFETs were connected to perform inverting logic and memory operations, as shown in Figure 5a. The input voltage (V IN ) was applied to Gates 1 and 2 for the p-and n-channel modes, respectively. The LIM inverter performed logic and memory op-erations. Figure 5b) shows the timing diagrams of the LIM inverter with consecutive input voltage pulses. When an input logic "1" pulse (a V IN = 1 V with a V DD = 1 V and a V SS = −1 V) was applied, the output voltage (V OUT ) was changed from 0.3 (output logic "1" state) to −0.3 V (output logic "0" state). Applying an input logic "0" pulse (a V IN = −1 V with a V DD = 1 V and a V SS = −1 V) reversed the output logic state from "0" to "1". The V OUT swing of the LIM inverter is smaller than the V IN swing because of the presence of excess charge carriers in the p*-n* electrostatic doping region with capacitance components. The devices have the memory characteristics so that the V OUT swing is smaller than the V IN swing. The mismatch between the V IN and V OUT can be eliminated through the improvement of the device characteristics, which remains in our future research. The symmetric reconfiguration of the double-gated R-FBFETs enables the LIM inverter to perform the logic operation via the complementary state transition of the component transistors with one input pulse; note that previously reported LIMs required several sequential input pulses for logic operations because of the undefinable channel mode of component transistors. [6,8,30] Moreover, unlike previously reported LIMs, our LIM inverter used both input and output (I/O) as voltage signals. [5,6] This implies that LIMs composed of double-gated R-FBFETs do not require peripheral circuits to convert I/O types.
The LIM inverter performs memory operations without any external bias voltage. The retention characteristics for output logic "1" state is shown in Figure 6a. After applying the input logic "0" pulse, the initial V OUT decreased from 0.34 to 0.30 V for 50 s. And after applying the input logic "1" pulse, the initial V OUT remained at the voltage of −0.34 V, as shown in Figure 6b. Consequently, the LIM inverter held both logic "0" and "1" states for >50 s with zero static power consumption. The long retention times originate from the component transistors' memory characteristics and the LIM inverter's configuration. During the hold operation, the logic states are stored in the LIM inverter be- cause the excess charge carriers remain in the potential wells of a component transistor in the "on" state. Simultaneously, the other component transistor in the "off" state helps to hold the logic states by restraining the leakage of excess charge carriers. Therefore, although the retention time of an isolated R-FBFET in the "on" state is ≈10 s, the LIM inverter had a much longer retention time owing to the low leakage current of the other device in the "off" state. Our LIM inverter is superior to SRAM/DRAMbased LIMs for static power consumption because of its quasinonvolatile memory characteristics. [31,32] Consequently, we demonstrate that the LIM inverter can perform outstanding logic and memory operations based on the steep switching and memory characteristics of the R-FBFETs. More, the configuration of the circuit enables our LIM inverter to exhibit quasi-nonvolatile memory characteristics. These results indicate that our R-FBFETs exhibit promising application potential as building blocks for Si-based LIMs.

Conclusion
Here, the R-FBFETs exhibited highly symmetric switching characteristics between p-and n-channel modes, and these transistors had memory operations with a retention time of 10 s. Electrostatic doping induced by two poly-Si gates enhanced the retention time of the transistors by forming inherent potential barriers and wells. Furthermore, the LIM inverter comprising two R-FBFETs performed logic and memory operations. Particularly, the retention times for both output logic states were >50 s under the zerovoltage bias condition. This study demonstrates that R-FBFETs have promising potential for applications in silicon-based LIMs.

Experimental Section
Device Fabrication: The R-FBFETs were fabricated using full CMOS processes from a p-type (100)-oriented silicon-on-insulator wafer with a 100 nm thick top Si layer (doping concentration of ≈10 16 cm −3 ) and 2 μm thick buried oxide. The 400 nm thick and 3 μm wide poly-Si gates were formed by low-pressure chemical vapor deposition (LPCVD) on a 25 nm thick SiO 2 gate oxide layer that was thermally grown on the intrinsic channel region at 850°C. LPCVD-based tetraethyl orthosilicate (TEOS) was used to form the gate sidewall spacers. The p + drain and Gate 2 regions were heavily doped with BF + 2 ions at a dose of 3 × 10 15 cm −2 and ion energy of 30 keV. The n + source and Gate 1 regions were heavily doped with P + ions at a dose of 3 × 10 15 cm −2 and ion energy of 100 keV. The annealing process was then carried out at 1000°C for 30 min, followed by rapid thermal annealing at 1050°C for 30 s to activate the implanted dopants. Subsequently, a Ti/TiN/Al/TiN metal alloy was deposited in the drain, source, and gate contact regions after interlayer dielectric deposition using LPCVD-based TEOS. Finally, we fabricated an LIM inverter by connecting the two R-FBFETs.
Measurement: All electrical data were measured using a semiconductor parameter analyzer (HP4155C, Agilent), Tektronix AFG31102 arbitrary function generator, Tektronix MDO3054 mixed-domain oscilloscope, and Keithley 2636B source meter at room temperature. Owing to the limitations of the Keithley 2636B source meters, the input logic pulse width for the logic operation of the LIM inverter was chosen as 1 ms.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.