Terrace Engineering of the Buffer Layer: Laying the Foundation of Thick GaN Drift Layer on Si Substrates

Vertical GaN‐on‐Si devices are promising for the next‐generation high‐voltage power electronics with low cost and high efficiency. However, their applications are impeded by the limited thickness of crack‐free GaN layers and high threading dislocation density (TDD) in the layer. Buffer layers are crucial for stress control while they usually behave with poor surface morphology, which causes early stress relaxation in GaN and limited thickness. Hereby, a terrace engineering approach for the buffer layers is proposed. Through tuning the supersaturation ratio, the terrace width can be manipulated and an atomically smooth AlGaN buffer layer can be realized, which effectively reduces the compressive stress relaxation and provides a firm foundation for thick GaN growth. As a result, a 7.5 µm thick GaN drift layer with TDD as low as 8.6 × 107 cm−2 is achieved on Si substrates. The room temperature electron mobility of the GaN drift layer can be raised up to 1210 cm2 V−1 s−1. The fabricated PiN diode shows a high breakdown voltage of 1058 V as well as a high on/off ratio of 1012. This work thus truly demonstrates the potential of high‐performance and low‐cost GaN‐based electronic as well as optoelectronic devices on Si platforms.


Introduction
The emergence of wide bandgap semiconductors greatly promotes the advancement of power devices that are crucial in power electronics systems for high energy conversion efficiency. [1][2][3][4][5] Benefiting from the superior physical properties of GaN and large scale, low cost, mature manufacturing process of Si substrates, GaN-on-Si devices have become one of the greatly competitive candidates for the next-generation power electronics. [6][7][8] At present, GaN-on-Si power devices have been commercialized in the applications under 650 V such as fast chargers of mobile phones based on the nitrides based high electron mobility transistor (HEMT) structure. [9] However, for the application scenarios under higher voltage (up to kV) like inverters in electric automobiles, which occupies a much larger market, the inherent drawbacks like dynamic performance degradation greatly raise serious concern about the reliability and usability of these lateral GaN devices. [10] Hence, vertical GaN-on-Si power devices are recently attracting more and more attention. [11,12] They are believed to be more promising for the kV-class applications owing to their better device reliability, higher current density, and better thermal management. [13] For vertical GaN power devices, a thick and high crystalline quality GaN drift layer is crucial to block the high voltage under reverse bias. [14] However, due to the large lattice mismatch (≈17%) and thermal expansion coefficient mismatch (≈54%) between GaN and Si, it is quite challenging to grow crack-free and low threading dislocation density (TDD) thick GaN layers on Si substrates. [15,16] To overcome this obstacle, a buffer layer between them could be a solution, as the buffers can introduce compressive stress for the sequent GaN layer to compensate the thermal tensile stress during cooling down. In the past decades, several buffer layers, such as low-temperature AlN, [17,18] superlattice, [19,20] and compositionally graded AlGaN [21] have been put forward. The buffers can introduce compressive stress for the sequent GaN layer to compensate the thermal tensile stress during cooling down. These efforts have indeed addressed the crack issue for the buffers with a thickness of 3-5 μm, which is the typical thickness for lateral GaN-on-Si power devices. [22][23][24][25][26] However, for the vertical GaN-on-Si power devices aiming at kVclass applications, the above thickness does not meet the requirements for the GaN drift layer. In addition, the TDD in the GaN layer is still high, impeding the performance of vertical GaN-on-Si power devices. [27] It is thus essential to further increase the thickness and reduce the TDD in GaN layers on Si.
The key issue for this purpose is to maintain the compressive stress (in other words, to reduce the relaxation of the compressive stress) induced by the buffer layers during the GaN growth. There are several factors that can induce stress relaxation, including the dislocation inclination, surface islands coalescence, and surface roughening. [28][29][30][31] There were lots of works focusing on the dislocation inclination, while few reports paid attention to the surface morphology during the GaN growth. Since the GaN layers are directly grown on the buffer layers such as AlGaN and should sustain the compressive stress, the surface morphology of AlGaN could make great impact on the sequent GaN growth. However, up to now, the AlGaN buffer layers on Si substrates usually present island-like surface morphology with a high surface roughness. [32,33] This kind of surface morphology would inevitably lead to a 3D growth mode of the sequent GaN growth at the initial stage and thus relax the compressive stress. Consequently, the remaining compressive stress could not be sufficient and the thickness of the crack-free GaN layer is limited. Therefore, it is of great importance to achieve a smooth AlGaN buffer layer as the base of the thick GaN layers on Si.
In this work, a terrace engineering of the AlGaN buffer layer grown on Si is proposed and demonstrated. By modulating the supersaturation ratio during the AlGaN growth, we could tune the width of the surface terrace and then eliminate the islandlike surface morphology of the AlGaN. Based on this strategy, an atomic smooth AlGaN buffer layer on Si is successfully obtained. The smooth AlGaN buffer layer can effectively reduce the relaxation of compressive stress at the initial growth stage of GaN and finally boost the thickness of crack-free GaN on Si. As a result, a 7.5 μm thick GaN drift layer with TDD as low as 8.6 × 10 7 cm −2 has been achieved on Si substrates. The fabricated GaN PiN diode delivers a high breakdown voltage of 1058 V and a high on/off ratio of 10 12 . Such excellent performance should enhance the competitiveness of vertical GaN-on-Si power devices on the kV-class applications in the future.

Proposal of a Terrace Engineering for AlGaN Buffer Layers
A schematic diagram of the terrace engineering is shown in Figure 1. Generally, on the surface with high TDD, just like the AlGaN buffers on Si substrates (TDD of ≈10 9 -10 10 cm −2 ), the spirals with a certain terrace width will initially form around the TDs with screw component. [34] The sequent nucleation sites (at the step edge or on the terrace) are determined by the terrace width and diffusion length of adatoms. For AlGaN growth, we only consider the diffusion of Al adatoms here since the surface diffusion length of Ga adatoms is much longer than the terrace width. Due to the weak surface diffusion capability of Al adatoms, they prefer to nucleate on the terrace before being incorporated into the step edges. As more adatoms deposit on the terrace, the nuclei would be enlarged in their size and expand into big islands Figure 1. Schematic diagram of terrace engineering. a) Under a low supersaturation ratio, the adatoms tend to nucleate on the terrace rather than on the step edge due to the wide terrace of the initial spiral. As the growth proceeds, these nuclei expand into islands and the surface gradually presents island-like morphology. b) Under a high supersaturation ratio, the adatoms on the terrace could effectively migrate to the step edge and incorporate due to the narrower terrace of the initial spiral. As the growth proceeds, the spirals could continue, and a smooth surface can be achieved.
( Figure 1a, left), during that the spirals will be covered by the islands. Finally, the spirals disappear, and high-density islands appear on the surface instead, leading to high surface roughness (Figure 1a, right). To suppress the nucleation on the terrace, either the terrace width or the diffusion length of adatoms should be tuned to match each other. Since the typical diffusion length of Al adatoms is usually less than 50 nm and not very sensitive to the growth conditions, [35,36] tuning the terrace width is preferred. Conventionally, the terrace width could be tuned through the miscut angle of the substrates. [37,38] However, for the AlGaN surface with high TDD, the modulation effect from the miscut angle of substrates fails since the surface morphology is mainly mediated by the dislocations. [39] An alternative approach to modulate the terrace width is to tune the supersaturation ratio. [39,40] According to the BCF (Burton, Cabrera, and Frank) theory, [41] the terrace width of the spiral growth is inversely correlated with the supersaturation ratio. The higher the supersaturation ratio is, the shorter the terrace width is expected. If the terrace width of AlGaN is reduced by using high supersaturation ratio, the adatoms do not need to migrate a long distance to incorporate into the step edge (Figure 1b, left). Finally, the spiral growth can continue and a smooth AlGaN surface can be achieved (Figure 1b, right). It is thus, by adopting this smooth AlGaN buffer layer, quite promising to achieve a thick GaN layer towards highperformance vertical GaN power devices on Si substrates.

Realization of Smooth AlGaN Buffer Layers on Si
Two AlGaN samples (conventional and terrace engineered samples) with different growth conditions were prepared on Si substrates. The thickness of the AlGaN buffers was ≈400 nm and the Al composition was estimated to be ≈35% for both samples ( Figure S1, Supporting Information). The growth temperature was 1050°C. The supersaturation ratio was tuned by changing the V/III ratio during the AlGaN growth. For the conventional sample, the V/III ratio of the AlGaN layer was ≈1200. That is in the typical value range for AlGaN growth. [42,43] The AlGaN surface exhibits micro-sized islands with a root-mean-square (RMS) roughness of 2.99 nm (Figure 2a), which is a typical surface morphology of AlGaN buffer layer on Si substrates. [32,33] The formation of surface islands is mainly attributed to the limited diffusion length of adatoms, as discussed above. In addition, there are high density holes on the surface that seriously interrupt the propagation of the surface steps ( Figure 2b). In contrast, for the terrace engineered sample, a higher supersaturation ratio with a V/III ratio of ≈9000 was employed, while a smooth AlGaN surface with atomic steps could be observed clearly (Figure 2c). The surface RMS roughness is dramatically reduced to only 0.45 nm. The surface exhibits atomic steps, as shown by the white lines in Figure 2d. From the atomic force microscopy (AFM) images (Figure 2b,d), we can roughly estimate that the terrace width decreases from ≈200 nm for the conventional AlGaN to ≈90 nm for the terrace engineered AlGaN. We should emphasize that the terrace engineering could also be applied to grow smooth AlGaN with higher Al compositions. The obtained Al 0.49 Ga 0.51 N buffer layer can still exhibit clear atomic steps by employing the terrace engineering, as shown in Figure S2 (Supporting Information). It is worth noting that there are yet no reports of such smooth Al-GaN buffer on Si substrates within only a few hundred nanometers. In conclusion, by employing terrace engineering, the atomic smooth AlGaN buffer layers can be obtained, which can be utilized for laying down the foundation of high quality and thick GaN layers on Si substrates.

Effects of the Surface Morphology of AlGaN Buffers on the Sequent GaN Growth
To investigate the effects of the AlGaN buffer layers with different surface morphologies on the sequent GaN growth, two GaN samples with a thickness of 3 μm were grown on top of the AlGaN buffers. The GaN layers for both samples were grown with the same growth conditions. The in situ reflectance curves for the two samples are shown in Figure 3a. For the GaN grown on the conventional AlGaN, the amplitude of the reflectivity first decreases and then gradually recovers, indicating a 3D growth process followed by a 3D to 2D growth mode transition process. While for the GaN grown on the terrace engineered AlGaN, the amplitude of the reflectivity almost keeps constant during the whole growing process, indicating a consistent 2D growth mode of GaN. The different growth modes for the two samples are also confirmed by AFM images for the first 200 nm GaN layers (growth interrupted) on the conventional AlGaN and terrace engineered Al-GaN, respectively ( Figure S3, Supporting Information).
Since different growth modes would lead to different stress states in the upper GaN layer, Raman scattering experiment was therefore conducted to investigate the stress state of the two samples. Generally, the E 2 (high) phonon peak in GaN is used to quantify the stress, and a typical strain-free GaN shows an E 2 (high) phonon peak at 567.5 cm −1 . [44] As shown in Figure 3b, the E 2 (high) phonon peak position of the GaN grown on the conventional AlGaN exhibits an obvious red shift (Δ = −1.9 cm −1 ), indicating a tensile stress state in the GaN layer. In contrast, a blue shift (Δ = 0.4 cm −1 ) is observed in the GaN layer grown on the terrace engineered AlGaN, indicating a compressive stress state. [45] These results reveal that the compressive stress in the GaN grown on the terrace engineered AlGaN can be very well maintained, while most of the compressive stress in the GaN grown on conventional AlGaN is relaxed and even transits to tensile stress state after cooling down. The different stress states in the GaN should be attributed to the different surface morphology of the AlGaN buffer layers, as their Al compositions are similar ( Figure S1, Supporting Information). For the case of the GaN grown on conventional AlGaN, it is the rough surface and sequent 3D to 2D growth mode transition that lead to compressive stress relaxation. [46][47][48][49] In contrast, for the case of the GaN grown on the terrace engineered AlGaN, the compressive stress in the GaN layer could be well maintained due to the smooth AlGaN surface. The different stress relaxation behaviors for the GaN grown on the conventional and terrace engineered AlGaN are also confirmed by the geometric phase analysis (GPA) [50,51] near the GaN/AlGaN interface ( Figure S4, Supporting Information). An obvious negative strain gradient is observed near the GaN/conventional-AlGaN interface, while almost no strain gradient is observed near the GaN/terrace-engineered-AlGaN interface. It reveals again that the smooth surface of the terrace engineered AlGaN can effectively prevent compressive stress relaxation during the sequent GaN growth. In addition, the crystalline quality of the GaN grown on the terrace engineered Al-GaN is also improved. The full width of half maximum (FWHM) of the X-ray diffraction (XRD) rocking curve for the GaN (1 0 2) plane decreases from 440 to 354 arcsec ( Figure S5, Supporting Information). That is benefit from the atomically smooth AlGaN surface and the sharp GaN/AlGaN interface (Figure 4c). Thus, the

Toward the High Performance Quasi-Vertical GaN PiN Diodes
By employing terrace engineering for the AlGaN buffer, a thick GaN PiN structure was successfully grown on Si substrates. The cross-sectional SEM image of the whole structure is shown in Figure 4a. It mainly consists of a 400 nm terrace engineered Al-GaN buffer layer, a 2 μm GaN layer, a 1.1 μm n + -GaN layer for current spreading, a 7.5 μm n − -GaN drift layer, and a 420 nm p-GaN layer. The cross-sectional scanning transmission electron microscopy (STEM) image (Figure 4b) indicates significant dislocation inclination and annihilation near the GaN/AlGaN interface, which could be ascribed to the atomic smooth AlGaN buffer layer and the atomically sharp GaN/AlGaN interface (Figure 4c). Figure 4d shows the symmetric (0 0 2) and asymmetric (1 0 2) plane scans of the XRD rocking curves for the GaN layer. The FWHM of the rocking curves for the GaN symmetric (0 0 2) and asymmetric (1 0 2) scans are only 199 and 208 arcsec, respectively (Figure 4d). The TDD in the GaN drift layer is lowered down to 8.6 × 10 7 cm −2 as revealed by estimating the dark spot density in the panchromatic cathodoluminescence (CL) image (Figure 4e). Both the CL and XRD results indicate the high crystalline quality of the obtained GaN layer. Figure 4f shows the benchmark of the GaN drift layer thickness versus dislocation density for GaN on Si. [52][53][54][55][56] We can find that this work demonstrates the thickest GaN drift layer on Si as well as the lowest TDD up to now. Owing to the lower TDD, the room temperature electron mobility in the GaN drift layer can be raised up to 1210 cm 2 V −1 s −1 , which was obtained from the Hall measurements on a similar sample grown on a high-resistivity (HR) GaN layer ( Figure S7, Supporting Information). To the best of our knowledge, that value of mobility is also the highest reported so far for the GaN layer on Si. [52,[56][57][58] A quasi-vertical GaN-on-Si PiN diode was further fabricated based on this structure. Figure 5a shows the schematic diagram of the structure for the GaN PiN diode. Figure 5b displays the reverse current-voltage (J-V) characteristics of the PiN diode. Thanks to the thick GaN drift layer and low TDD, the breakdown voltage can be enhanced up to 1058 V. While the breakdown field is calculated to be 2.8 MV cm −1 , which shows progress compared with some previous reports, [52,59] it is still lower than the theoretically predicted value of ≈3.5 MV cm −1 for GaN. We believe the breakdown voltage can be further improved by the junction termination design optimization, the sidewall defects elimination, and the TDD reduction in the GaN drift layer. Figure 5c,d present the forward current-voltage characteristics. A remarkably high on/off ratio of 10 12 is extracted. That is one order of magnitude higher than the state-of-art on/off ratio of 10 11 reported for GaN PiN diodes on Si. [59] The high on/off ratio is mainly attributed to the low leakage current density (10 −9 A cm −2 @ −3 V), which could be correlated with the low screw-type TDD. The turn-on voltage is extracted to be 3.38 V (@ 1 A cm −2 ), which is close to the bandgap of GaN. Thanks to the high electron mobility, the PiN diode exhibits a high forward current density of 3.2 kA cm −2 (@ 9 V) and a low specific on-resistance (R on,sp ) of 0.95 mΩ cm 2 (@ 8 V). As such, by employing terrace engineering, we have nicely demonstrated a quasi-vertical GaN-on-Si PiN diode with excellent output performances.

Conclusion
In summary, we demonstrate a terrace engineering approach for the growth of AlGaN buffer layers on Si substrates. Based on such a strategy, the terrace width of the AlGaN buffer layer could be tuned by the supersaturation ratio, and the AlGaN buffer layers with clear atomic steps were obtained on Si substrates. The smooth AlGaN surface can then effectively prevent the compressive stress relaxation in the initial GaN growth and provide a firm foundation for the sequent thick GaN growth. With these advances, a 7.5 μm thick GaN drift layer with TDD as low as 8.6 × 10 7 cm −2 was achieved on Si substrates. The electron mobility in the GaN drift layer can be raised up to 1210 cm 2 V −1 s −1 .
Owing to the high crystalline quality thick GaN drift layer, the fabricated PiN diode also shows a high breakdown voltage of 1058 V and a high on/off ratio up to 10 12 . Our results demonstrate the potential of high quality GaN layers toward high-performance and low-cost GaN-based power devices as well as optoelectronic devices on Si platforms.

MOCVD Growth of GaN and AlGaN Buffers on Si:
The GaN layers in this study were grown on 4-in. Si substrates by metal-organic chemical vapor deposition (MOCVD) (Aixtron CCS). Trimethyl-gallium (TMGa), trimethyl-aluminum (TMAl), and ammonia (NH 3 ) were used as the sources of Ga, Al, and N, respectively. Silane (SiH 4 ) was used as the ntype dopant. Bis(cyclopentadienyl)magnesium (Cp 2 Mg) was used as the p-type dopant. Hydrogen (H 2 ) was used as the carrier gas. All the epitaxial structures started with a 300 nm AlN nucleation layer at a V/III ratio of ≈480 and temperature of 1070°C. It is followed by a 400 nm AlGaN buffer layer. The V/III ratio during the AlGaN buffer layer growth was modulated mainly via adjusting the NH 3 flux. And the TMAl flux was slightly tuned accordingly to keep a constant Al composition as possible. Then, the GaN layer was grown at the temperature of 1040°C with a V/III ratio of ≈4500. For the PiN structure, the n + -GaN layer was grown under 1050°C with a V/III ratio of ≈4500. The Si concentration was ≈5 × 10 18 cm −3 . The n − -GaN drift layer was grown under 1050°C with a V/III ratio of ≈5600. The Si concentration was ≈2 × 10 16 cm −3 . On the top, the p-GaN layers consist of a 400 nm p + -GaN layer (Mg concentration of ≈1 × 10 19 cm −3 and hole concentration of ≈3 × 10 17 cm −3 ) and a 20 nm p ++ -GaN layer (Mg concentration of ≈1 × 10 20 cm −3 ).
Device Fabrication of Quasi-Vertical GaN-on-Si PiN Diode: The p-GaN layers (including p + and p ++ -GaN) were first etched by an inductively coupled plasma (ICP) dry etching process using photoresist (PR) as the mask. The following process was ICP deep etching the n − -GaN layer using SiO 2 as the mask until exposing the n + -GaN surface. TMAH treatment (85°C, 1 h) was conducted to recover the etching damage on the n + -GaN layer surface and the sidewall of the n − -GaN layer. Then the cathode Ohmic contact ring with a width of 50 μm was completed by depositing Ti/Al/Ni/Au metal on the n + -GaN layer and annealing at 550°C for 5 min in N 2 . Next, the circular anode Ohmic contact was deposited on p-GaN with Ni/Au and annealed at 550°C for 5 min in oxygen. The radius of the anode electrode was 50 μm. And the distance between the anode region and the cathode region was 30 μm. Finally, junction edge termination was fabricated at the edge of the p-GaN layer to manage the electric field. showing a high forward current density of 3.2 kA cm −2 (@ 9 V) and a low R on,sp of 0.95 mΩ cm 2 (@ 8 V).
Characterization: The XRD rocking curve and reciprocal space mapping measurements were performed with a Malvern Panalytical X'Pert Pro MRD high-resolution X-ray diffractometer. Surface morphology images were obtained by the atomic force microscopy (Bruker Dimension Icon). STEM experiments were performed using a Thermo Scientific Themis Z system at 200 kV. SEM and CL images were recorded under 10 kV using an FEI Nova NanoSEM430 FEG thermal field emission scanning electron microscope. OM experiments were performed with the OLYMPUS BX60M system, and the images were acquired by a 3.0M Pixel CCD system. Raman scattering measurements were performed at room temperature with Ar + 514 nm laser lines as the excitation light source. Hall effect measurements in Van der Pauw configuration were carried out in a Bio Rad Accent HL5500 Hall measurement system.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.