3‐Masks‐Processed Sub‐100 nm Amorphous InGaZnO Thin‐Film Transistors for Monolithic 3D Capacitor‐Less Dynamic Random Access Memories

The capacitor–less embedded dynamic random access memory (eDRAM) based on oxide semiconductor (OS) transistors exhibits a promising future and thus has lead to a growing demand for nanoscale OS thin–film transistors (TFTs). In this work, a self–aligned top–gate (SATG) amorphous InGaZnO (a‐IGZO) TFT is demonstrated by using the simplest 3‐masks (3M) process, and the downscaling‐related issues are carefully addressed to strengthen its back–end–of–line (BEOL) compatibility and mass producibility. The gate insulator (GI) and associated interface defects of the TFTs are jointly optimized with 4–nm atomic‐layer‐deposited (ALD) AlOx on the pre‐oxidized a‐IGZO. The defects in a‐IGZO channel are further manipulated with a rapid thermal anneal (RTA) in oxygen. By virtue of the strengthened gate controllability and modified channel properties, the fabricated TFT with 97‐nm gate length (Lg) exhibits decent performance, such as a maximum on–state current (ION) of 32.4 µA µm−1, as well as clear linear and saturation characteristics. Based on such 3M SATG a‐IGZO TFTs with high device performance and inherently minimal parasitic capacitances, the developed capacitor‐less eDRAM bit cell achieves a wide sensing margin and a long retention time of over 500 s. A highly manufacturable oxide TFT technology for high–performance and high–density monolithic–3D (M3D) integration is thus well established.

In theory, the self-aligned top-gate (SATG) OS TFT has the smallest parasitic capacitance, superior downscaling capability, and minimal processing steps, and thus could be a more feasible solution for the M3D capacitor-less eDRAM. [32,33] Nonetheless, the SATG a-IGZO TFT with sub 100-nm gate length (L g ) has rarely been reported. During the channel length downscaling, the self-aligned S/D-augmented short-channel effects (SCEs) can hardly be suppressed by the insufficient gate controllability of incumbent gate insulators (GIs), such as the commercially favorable plasma-enhanced chemical vapor deposited (PECVD) silicon oxide (SiO x ). Thus far, the SiO x GI of a-IGZO TFTs has been thinned down to 8.6 nm, [34] whereas it is still insufficient to cope with the sub-micro channel. An even thinner equivalent oxide thickness (EOT) demands the atomic layer deposited (ALD) high-k dielectrics, such as Al 2 O 3 , [35][36][37] HfO 2 , [38,39] ZrO 2 , [40] etc. However, the top-gate ALD GI readily causes the chemical reaction damages to underneath OS layers. The resultant abundant defects in the a-IGZO active layer or at the channel/GI interface give rise to an increased off-state current (I OFF ), large hysteresis, and poor bias stabilities. [41][42][43] Another bottleneck for nanoscale SATG a-IGZO TFTs is the formation of abrupt S/D homojunctions. The n + -IGZO S/D is usually populated by the oxygen vacancy (V O ) or hydrogen (H) species through the plasma treatments, [44,45] metal-induced metallization, [46] H doping, [47] or other methods. Nevertheless, the low formation energy and fast diffusion coefficient of such donor defects can readily cause the lateral defect diffusion from n + -type S/D into the a-IGZO channel, thus resulting in the graded S/D junctions, defective channel, and channel length shrinking (ΔL). [48][49][50] The nanoscale ΔL becomes quite crucial for the implementation of sub-100 nm length TFT, otherwise the noticeably increased channel carrier concentration may result in severe performance deteriorations, e.g., large I OFF , nega-tive threshold voltage (V TH ) shift, and subthreshold swing (SS) degradation. [51,52] In this work, a simple 3-masks (3M) process for SATG a-IGZO TFT was developed to scale down the EOT and L g to 2.4 nm and sub-100 nm, respectively. First, 4-nm AlO x and HfO x were comparatively implemented as the GIs of SATG a-IGZO TFTs. The AlO x -gated TFT exhibited a much lower gate leakage current (I G ) and trap state density (N it ). Nitrous oxide (N 2 O) pretreatment on a-IGZO was also conducted to improve the relative immunity of a-IGZO against the ALD-induced damages. Furthermore, we elucidated the impact of oxygen (O 2 ) post-annealing on the carrier concentration of the submicron a-IGZO channel. By virtue of the interface and channel engineering, a 97-nm SATG a-IGZO TFT was successfully demonstrated within 3 masks. Additionally, the capacitor-less eDRAM bit cell based on such 3M SATG a-IGZO transistors exhibited a superior retention time longer than 500 s. These results reveal that the proposed 3M SATG TFT with nanoscale L g and ΔL explores the great mass-production potential of OS-driven high-density M3D memories. Figure 1 illustrates the process flow and electron microscopy images of the fabricated SATG coplanar a-IGZO TFT. [52] The fabrication process flow with 3 masks shown in Figure 1a is explained in detail in the Experimental Section. The top view scanning electron microscope (SEM) and cross-sectional scanning transmission electron microscope (STEM) images, together with the corresponding energy-dispersive spectroscopy (EDS) profile, in Figure 1b-d depict the top gate and source/drain metal and a selfaligned coplanar TFT structure with sub-100 nm L g and ultrathin GI, respectively.

Results and Discussion
Among all the high-k materials, AlO x and HfO x are the most common GIs of reported bottom-gate OS TFTs. [35,36,38] In order to investigate the ultrathin high-k GI based on TG structure, Figure 2a,b compares the transfer characteristics of the 3M-proposed SATG a-IGZO TFTs with GIs of 4-nm AlO x and HfO x , respectively. During the ALD process, water (H 2 O) or ozone (O 3 ) is used as the wet or dry oxidant, and (CH 3 ) 3 Al (TMA) or [(CH 3 ) 2 N] 4 Hf (TDMAHf) is adopted as the aluminum (Al) or hafnium (Hf) source, respectively. For the ALD AlO x -gated TFT, the replacement of H 2 O with O 3 could achieve an improved SS, a more positive V TH , and a much lower I G (Figure 2a), due to the suppressed hydroxyl (-OH) residuals in the dry oxidized AlO x . [41] Compared to the AlO x (O 3 +TMA)-gated a-IGZO transistor, the EOT of HfO x (O 3 +TDMAHf) GI can be further thinned to 1.7 nm ( Figure S1, Supporting Information), while the electrical characteristics are quite similar, except for the dramatically increased I G and much higher N it , as summarized in Figure 2c and Table 1. This inferior performance could be plausibly attributed to the insufficient band offset and a highly defective interface between HfO x GI and a-IGZO channel. [53] It is reported that N 2 O plasma pretreatment on the active layer can readily compensate for the top GI-induced damages. [54] Figure 2d,e compares the forward and reverse sweep transfer curves of the proposed 4-nm AlO x (O 3 +TMA)-gated a-IGZO TFT with or without N 2 O plasma pretreatment, and the corresponding dependences of voltage hysteresis (V Hys ) on the gate voltage Table 1. Parameter summary of the 3-masks SATG a-IGZO TFT with 4-nm ALD gate insulator. (V GS ) sweep ranges. Here, V Hys is defined as the difference between forward and reverse sweep of V GS at a constant drain current (I D ) of 10 −10 A μm −1 . All devices are with a 2.4-μm gate length. For the TFT without N 2 O plasma pretreatment, a pronounced V Hys is observed, and increases up to 25 mV within V GS of ±1.5 V. By contrast, when a-IGZO was pre-oxidized by N 2 O plasma before the AlO x deposition, such hysteresis was largely eliminated, and no longer depends on the V GS sweep range ( Figures S2 and S3, Supporting Information). Generally, the hysteresis generation originates from electron trapping by defects at the AlO x /a-IGZO interface. [55] Deeper trap states may get charged under larger V GS stress, causing a more significant shift of sweep curves. The N 2 O-eliminated hysteresis could be associated with the reduction of various defects at the a-IGZO/AlO x interface, such as V O , -OH, and metal interstitial (M i ), [41] thus suggesting a relative immunity of N 2 O-passivated a-IGZO to the subsequent ALD-activated chemical reactions. Nevertheless, even with a 2.4-nmEOT of optimized ALD AlO x , a noteworthy "SCE" was still observed on SATG a-IGZO TFTs with L g shrinking from 0.8 to 0.2 μm ( Figure S4a, Supporting Information). As aforementioned, in the SATG coplanar a-IGZO TFTs, the high-density carriers in the n + -IGZO S/D may laterally diffuse into the channel and form the graded homojunctions with at least several sub-micron ΔL, thereby leading to undesirable performance deteriorations. To alleviate this, post-anneals are usually implemented in the O 2 ambient furnace to passivate the channel defects. [56] Despite the lowered carrier density across the entire active layer, the simultaneously decreased carrier mobility and increased series S/D resistance could drastically suppress the on-state current, as shown in Figure S4b (Supporting Information).
In order to mitigate the undesired impact of O 2 anneal on the S/D extension regions while achieving the effective oxygen supplement into the channel, several elaborate architectures and processes have been proposed, such as a buried oxygen tunnel for the defect passivation in the gate-capped OS regions, [57] an oxygen blocking layer inserted below the OS film, [58] and the raised IGZO stack in S/D as the oxygen buffer layers, [31] etc. In contrast, the proposed 3M architecture is much more simplified, where O 2 can readily diffuse into the channel through the exposed a-IGZO regions. To avoid the excessive oxidization of S/D, here we utilize an O 2 rapid thermal anneal (RTA) to modulate the overall carrier concentration. Figure 3 shows the impact of O 2 RTA on the transfer characteristics of the 3M SATG a-IGZO TFTs with various L g s. The drain voltage (V DS ) is fixed to be 0.1 V. For the 0.8-μm device, as shown in Figure 3a, no significant changes occur after 10-s O 2 RTA, but a slightly positive V TH shift and on-state current (I ON ) decrease are observed with an additional 20-s anneal. By comparison, the 0.5μm device in Figure 3b, with an initially negative V TH , is distinctly improved by 10-s RTA, and similarly, I ON reduction is observed after the total 30-s anneal. Note that with L g scaling to 0.2 μm (Figure 3c), 10-s anneal is no longer sufficient to adjust the channel carrier concentration to a normal value. The excellent I D modulation can be eventually obtained in the shown range of V GS after 30-s oxygen supplement, indicating the high effectiveness of channel defect passivation. Meanwhile, the well-maintained high I ON for all devices suggests a still highly conductive n + -IGZO in S/D extension regions.
As speculated in Figure 3d-f, some thermally stable donors, such as metal substitutional defects, [59] may be formed in the repeatedly processed S/D extension regions, while these relatively vulnerable defects in the channel, like V O , can be easily repaired by the oxygen annealing. The X-ray photoelectron spectroscopy (XPS) results ( Figure S5, Supporting Information) show that the V O peak of a-IGZO film can be noticeably minimized by the 30s O 2 RTA process. Additionally, the Hall measurement results ( Figure S6, Supporting Information) exhibit that with 100-s argon (Ar) plasma treatment, the initial sheet resistance (R sh ) of both bare and AlO x -covered a-IGZO films can reach 10 3 Ω sq −1 . After the subsequent implementation of 30-s O 2 RTA, the R sh of bare a-IGZO film rapidly rises up to 10 9 Ω sq −1 , whereas the AlO x -covered film well maintains the initial value. This suggests that the AlO x deposition process may contribute to the formation of thermally stable donor defects in the S/D regions. Further exploration of the underlying mechanism could benefit the ultradownscaling of SATG OS TFTs. To clarify the impact of O 2 RTA time on the TFT performances under various L g s, the lateral carrier concentration distribution (n 0 ) in the bulk a-IGZO layer is illustrated in Figure 3df as well. Here, the lowest carrier concentration in the channel center (n ch ) under various annealing conditions is estimated by V TH of the measured I D -V GS characteristics in Figure 3ac. [49] Besides, according to the results of Hall measurements, O 2 RTA within 30 s has minimal impact on the carrier concentration in S/D regions (n SD ). On the other hand, the n ch changes by orders of magnitude in short-channel devices, so that a decent V TH can be obtained without lowering the I ON . From the comparison of transfer curves in Figure 3a-c, it can be concluded that a 10-s RTA may not be long enough to drive O 2 into the central region of a submicron channel. With an additional 20-s RTA, the adequate O 2 supplement suppresses the n ch to an appropriately low value, corresponding to a more positive V TH (Figure 3a-c). Moreover, the incidental decrease of I ON can be attributed to an increased S/D series resistance (R SD ), due to the oxidization-reduced n 0 in the diffusion region (i.e., the ΔL region).
The joint optimization of interface engineering and channel carrier modulation enables the further scaling of 3M SATG a-IGZO transistors. Figure 4a,b shows the typical transfer characteristics of the proposed TFT with 4-nm AlO x GI and 97-nm L g . The device exhibits a high I ON /I OFF over 10 9 , a slightly positive V TH of 0.07 V, and a maximum I D of 32.4 μA μm −1 at the power supply voltage of 2.0 V. Besides, no apparent hysteresis is observed between the forward and reverse V GS sweeps, suggesting the excellent interface between N 2 O-pretreated a-IGZO and ALD AlO x (O 3 +TMA). [41,52] The full range of SS versus I D is plotted in Figure 4c, with a minimum SS of 105.4 mV dec −1 extracted in the subthreshold regime, which can be further reduced by an optimized active layer, [56] a thinner EOT, [60] or more sophisticated strategies. [61] As for the output curves shown in Figure 4d, a clear pinchoff without current crowding is observed, indicating a good ohmic contact between the metal electrodes and n + -IGZO S/D regions. Additionally, the W-normalized R SD (R SD W) is extracted to be 6.7 Ω cm by the transmission line method (TLM), [52] which is comparable with the reported values of μm-level a-IGZO TFTs. [62,63] The influence of such R SD W can be excluded from the extrinsically measured I D to reveal an intrinsic I D . As shown in Figure 4e, the increasement from extrinsic I ON to intrinsic I ON is observed to be larger for the 97-nm device than for the 1-μm one, implying that the parasitic S/D resistance has a more detrimental impact on short-channel devices. [64] Furthermore, Figure 4f shows the extrinsic and intrinsic transconductance (G m ) versus V GS for the 97-nm device at V DS = 0.1 V. The extracted peak intrinsic G m of 7.3 μS μm −1 increases nearly threefold after eliminating R SD W. Apparently, even though the proposed S/D scheme is as conductive as that of μm-long devices, such R SD still becomes non-neglectable compared to the significantly decreased channel resistance of nanoscale transistors, giving rise to the observed decrements of I ON and G m in Figure 4e,f. Hence, a further reduction of parasitic S/D resistances is still desired for the I ON enhancement of nanoscale SATG OS TFTs. Table 2 summarizes the reported process details and performances of the short-channel oxide TFTs with channel lengths below 350 nm. To date, the SATG structure is less studied due to several issues as mentioned in the Introduction session, e.g., high-k GI-related interfacial reaction or lateral donor diffusioninduced defective channel. The proposed a-IGZO TFT with L g downscaled to 97 nm and EOT thinned to 2.4 nm, still possesses www.advancedsciencenews.com www.advelectronicmat.de  excellent characteristics, demonstrating the superior feasibility of the SATG architecture with the simplest 3M process. Note that although the top-gate stack can provide a natural protection for the OS channel in the SATG architecture, the inter-layer passivation is still essential for the M3D eDRAM, [65,66] and requires further development.

2T0C eDRAM Based on 3M SATG a-IGZO TFTs
The capacitor-less two-transistor (2T0C) eDRAM gain cell was then demonstrated using the proposed two identical 3M SATG a-IGZO TFTs (W/L = 1.5 μm/230 nm). Figure 5a,b shows the corresponding circuit schematic and SEM image, along with several coupling capacitors between the storage node (SN) and signal lines which could also contribute to the effective storage capacitance (C st ). Figure 5c illustrates the cell bias conditions during write and read operations. During the writing "1" operation, the SN is driven to a higher voltage level. Once the write transistor (W Tr ) is switched off, the charges stored in SN start to leak through the off-state current path of the write TFT. The voltage of the SN (V SN ) can be assessed by monitoring the drain current (I RBL ) of the read transistor (R Tr ) [7] and doing the polynomial fitting of V SN -I RBL curve ( Figure 5d). As shown in the extracted time evolution of I RBL and V SN in Figure 5e,f, the written "1 V" was well maintained at the switching-off moment of the write TFT. It is reported that V SN deterioration happens at write/read termination due to the non-negligible parasitic capacitance compared to C st . Its compensation requires a larger C st or specialized driving scheme. [29] In this work, benefited from the ultrashort ΔL and thus minimal G-to-S/D parasitic capacitance in SATG a-IGZO TFT, C st is dominated by the gate capacitance (C ox ) of reading transistor, thus maximizing the V SN sensing margin and enhancing its immunity to noise/coupling disturbance. Moreover, Figure 5f shows that the retention time of the 2T0C bit cell based on our 3M SATG a-IGZO transistors can reach above 500 s, by taking 0.1-V V SN drop as the retention failure criterion. The I OFF is thus estimated to be about 10 −19 A μm −1 . Table 3 benchmarks the most recent works reported for BEOLcompatible oxide-based eDRAM gain cells. While ultra-scaled OS TFTs (down to 50 nm) have been reported to enable an even longer retention time of the capacitor-less eDRAM, [6,12,30,57] our 3M SATG TFT shows a much simpler fabrication process, minimal parasitic capacitance, and comparable I OFF level. In addition, thanks to the efficient R SD optimization, the I ON of the read transistor reaches 6 μA μm −1 at V DS = 1.0 V, which is sufficient for our 5 fF capacitor to store 1 V within 10 ns. The C ox of the read transistor can be further scaled by the dimension miniaturization, thus enabling much faster access.

Conclusion
A SATG a-IGZO TFT technology with sub 100-nm L g was well established with the simplest 3M process flow. First, we systematically studied the top GIs of 4-nm ALD AlO x and HfO x . Due to larger band offset and less interface reaction between a-IGZO and AlO x , the SATG TFTs with 4-nm ALD AlO x GI have a much lower I G and N it . N 2 O pretreatment on a-IGZO is implemented to further alleviate the impact of ALD-induced reactions. Moreover, the performances of the submicron SATG a-IGZO TFTs are remarkably improved by using the post-treatment of O 2 RTA. 30-s adequate O 2 supplement modulates the channel carrier concentration to an appropriate value, thus enabling a slightly positive V TH without the noticeable current limiting. Based on the joint optimization of such interface engineering and channel carrier modulation, the 3M SATG a-IGZO TFT was successfully scaled down to sub-100 nm with well-maintained high performance metrics, including an I ON of 32.4 μA μm −1 , a decent V TH of 0.07 V, and a high on/off current ratio over 10 9 . A BEOL-compatible 2T0C eDRAM bit cell was successfully implemented using the 3M SATG a-IGZO TFTs, enabling a long retention time (>500 s) due to the ultralow I OFF of around 10 −19 A μm −1 . The competitive performance and high manufacturability make the proposed 3M-SATG OS TFTs an attractive candidate for eDRAM and relevant M3D applications.

Experimental Section
Device Fabrication: Figure 1a shows the detailed fabrication process of the SATG a-IGZO TFT. [52] First, a 500-nm-thick SiO 2 film was grown by thermal oxidation on an undoped p-type silicon wafer as the thermal oxide substrate. A 20-nm a-IGZO layer was deposited by DC sputtering using a ceramic target (In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 mol%). The flow rate ratio of argon/oxygen and working gas pressure during sputtering were set as 47/3 and 0.45 Pa, respectively. Then, the a-IGZO layer was patterned by wet etching to form active islands. N 2 O plasma treatment was performed for 120 s at 150°C. Afterward, 4-nm thick AlO x was deposited by ALD at 150°C as the gate insulator, with O 3 and TMA precursor as the dry oxidant and Al source, respectively. The sample was then annealed at 300°C in an oxygen environment for 1.5 h. E-beam lithography (Raith e-LiNE) was used to define the gate region. A 50-nm Ti/Au bilayer was then deposited consecutively by e-beam evaporation and lifted off as the gate electrode. With the Ti/Au bilayer electrode as an in situ etching mask, 100-s Ar plasma was performed to remove the exposed AlO x and synchronously form the n + -IGZO S/D with a sheet resistance of 10 3 Ω sq −1 . Subsequently, a 50nm Mo layer was deposited and lift-off as the S/D electrodes. Finally, the device was annealed in an oxygen atmosphere using RTP at 200°C to eliminate some radiation-related defects.
Thin Film and Device Characterization: Both bare and AlO x -covered a-IGZO films were characterized by the Hall measurement (Ecopia HMS-3000 Hall Effect Measurement System). The top-view SEM image of the fabricated TFT was obtained by e-LiNE (Raith). The cross-sectional STEM image was obtained by using focused ion beam (FEI Helios G4 UX) and Aberration Corrected TEM (JEM-ARM200F). The corresponding elemental composition was analyzed by EDS. All electrical measurements of TFTs were performed by an Agilent B1500 semiconductor parameter analyzer in dark at room temperature. The V TH was defined as the V GS satisfying I D = W/L × 1 nA. The SS was taken as the minimum dV GS /dlog(I D ) for I D ranging from 10 −12 to 10 −9 A μm −1 . The μ FE was derived by the following equation N it was calculated by using the equation below where k B is Boltzmann constant, T is the absolute temperature, and q is the electric charge. All parameters were extracted at V DS of 0.1 V unless otherwise specified.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.