Large‐Scale N‐Type FET and Homogeneous CMOS Inverter Array Based on Few‐Layer MoTe2

2D MoTe2 is regarded as a favorable candidate for semiconductor nanoelectronics integration. Chemical‐vapor‐deposition‐grown MoTe2 usually presents p‐type characteristics. In order to realize basic electronic units like complementary metal‐oxide‐semiconductor (CMOS) inverter, controllable fabrication of p‐ and n‐type transistors at large scale is of vital importance. Here, large‐scale MoTe2 n‐channel field‐effect transistor (n‐FET) arrays are successfully fabricated with seamless coplanar metallic 1T′‐WTe2 contacts to reduce contact resistance. High‐k HfO2 serves as a gate dielectric and its atomic‐layer‐deposition (ALD) process causes an n‐doping effect on the 2H‐MoTe2 channel. The FETs perform typical n‐type characteristics with average electron density and on/off ratio of ≈1.7 × 1013 cm−2 and 2.1 × 104, respectively. Furthermore, large‐scale homogeneous CMOS inverter arrays are fabricated, showing clear logic swing with low power consumption (≈0.4 nW) and high device yield (≈92%). Notably, their voltage transfer characteristics exhibit small hysteresis, and they work well after being kept in air for 16 months, indicating high device stability. The statistical results show that both the n‐FETs and CMOS inverters have high uniformity and reliability in performance. Significantly, this fabrication method is free from transfer processes and compatible with traditional silicon technology. This work paves the way for the application of few‐layer MoTe2 in semiconductor nanoelectronics integration.

The complementary metal-oxidesemiconductor (CMOS) inverter is one of the most important electronic units, in which the n-channel FET (n-FET) and p-channel FET (p-FET) are two basic components.][22] The corresponding fabrication is complicated and involves the material transfer process, which reduces the device yield and is not compatible with traditional silicon technology.In order to fabricate homogeneous CMOS inverter on identical 2D TMDC platform, controlling p/n-type conversion of the semiconductive channel is of vital importance.However, the conventional doping techniques, such as ion implantation, cannot be used to 2D TMDC materials, because the ion bombardment will impart serious lattice damage to 2D TMDC materials. [10][25][26] In contrast, the CVD-grown MoTe 2 usually presents p-type characteristics due to the air molecule adsorption. [27]ver the years, several attempts about realizing n-doping of MoTe 2 were reported, such as chemical doping, [28] electrothermal doping, [27] Ar plasma treatment doping, [29] and atomic layer deposition (ALD) of Al 2 O 3 induced doping. [9,10]][29] Notably, in all these works, the gate dielectric layer fabrication and the n-doping process were separate.Besides, compared to Al 2 O 3 , HfO 2 has higher k value and can guarantee better gate control capability. [30]However, no work about n-type MoTe 2 doped by ALD of HfO 2 was reported to date.
Another problem that limits the performance of 2D electronic devices is the high-resistance contacts between the 2D semiconductor and metal electrode, due to fermi-level pinning effect and the interface damages induced by the direct metal electrode deposition. [34,35]It has been demonstrated that using coplanar 1T′-MoTe 2 (metallic phase) to contact p-type 2H-MoTe 2 (semiconducting phase) is an effective method to reduce the contact resistance. [7,16]Finding appropriate materials to contact the ndoped 2H-MoTe 2 is equally important.
In this work, we successfully fabricated a large-scale few-layer MoTe 2 n-FET array.In order to reduce contact resistance, we fabricated coplanar metallic 1T′-WTe 2 source and drain electrodes by tellurizing patterned W film deposited by magnetron sputtering.Devices with coplanar metallic 1T′-MoTe 2 and conventional metals (Ti/Au and Pd/Au) electrodes were also fabricated for comparison.High-k HfO 2 was adopted as gate dielectric.We found that, compared to that of Al 2 O 3 , ALD process of HfO 2 has better ndoping effect on 2H-MoTe 2 .We also investigated the influence of 2H-MoTe 2 thickness on the device performance, and concluded that the ALD doping effect is better in thinner 2H-MoTe 2 .Notably, in this work, we accomplished fabricating gate dielectric layer and realizing n-doping in one step for the first time, which greatly simplifies the device process.The optimized n-type MoTe 2 FETs perform typical n-type characteristics with average electron density, mobility, and on/off ratio to be ≈ 1.7 × 10 13 cm −2 , 1.6 cm 2 V −1 s −1 , and 2.1 × 10 4 , respectively.Furthermore, we designed and fabricated a large-scale MoTe 2 -based homogeneous CMOS inverter array.The CMOS inverters show clear logic swing with low power consumptions and high device yield (≈92%).The average power consumption is 0.44 nW at the supply voltage of 1 V, close to the lowest value of the so-far reported TMDC-based CMOS inverters. [11,20,22]Moreover, the voltage transfer character-istics (VTCs) of the CMOS inverters exhibit small hysteresis and the performances of the CMOS inverters are even better after being kept in air for 16 months, indicating the high device stability in practical operation.Statistical results show that both the n-FETs and CMOS inverters are with high uniformity and reliability in performance.We attribute our achievement to the highquality CVD-grown 2D materials, the novel device structure, and the facile fabrication that is free from transfer process and compatible with traditional silicon technology.Our work paves the way for the application of 2D MoTe 2 in nano-electronics integration.

Results and Discussion
High-quality few-layer 2H-MoTe 2 film was grown on p + -Si/SiO 2 substrate via the CVD method by tellurizing Mo film deposited by magnetron sputtering. [14]The thickness of the 2H-MoTe 2 was controlled by the thickness of the Mo film.Optical images of as-grown 6 nm thick (corresponding to 7 layers) MoTe 2 , characterized by atomic force microscopy (AFM) (Figure S1d, Supporting Information), are shown in Figure S1a,b (Supporting Information).The MoTe 2 film is formed by circular single crystal 2H-MoTe 2 domains and the single crystal 2H-MoTe 2 domain increases with the growth time. [14,16]The Raman spectrum of asgrown 2H-MoTe 2 is shown in Figure S3 (Supporting Information), which consists of an out-of-plane A 1g (172 cm −1 ) mode together with a strong in-plane E 1 2g (233 cm −1 ) mode.The electrical property of as-grown 2H-MoTe 2 was characterized by fabricating back-gated FET, in which 1T′-MoTe 2 , p + -Si, and SiO 2 serve as the contact electrodes, gate electrode, and dielectric, respectively (Figure S1c,e, Supporting Information).The typical transfer curve presents p-type channel behavior with an on/off ratio of ≈ 8 × 10 4 .The hole density and mobility are ≈ 8.9 × 10 11 cm −2 and 14 cm 2 V −1 s −1 , respectively (Figure S1f, Supporting Information).
Based on the 2H-MoTe 2 film, we fabricated large-scale ntype 2H-MoTe 2 FET array with coplanar metallic 1T′-WTe 2 contacts.First, striped 2H-MoTe 2 /W patterns were fabricated on the growth substrate by UV lithography, reactive ion etching (RIE), magnetron sputtering (for depositing W film), and lift-off process.Next, the W patterns were tellurized to 1T′-WTe 2 by a second CVD process at a lower temperature (560 °C), forming striped 2H-MoTe 2 /1T′-WTe 2 patterns (Figure S2b, Supporting Information).The formation of 1T′-WTe 2 was confirmed by the appearance of well-resolved A g modes (124, 141, 171, and 219 cm −1 ) of 1T′-WTe 2 (Figure S3, Supporting Information) in its Raman spectrum.These coplanar patterns were further fabricated into isolated 1T′-WTe 2 /2H-MoTe 2 /1T′-WTe 2 array by UV lithography and RIE (Figure S2c, Supporting Information).After that, a layer of 25 nm HfO 2 gate dielectric was deposited by ALD.The ALD process also helps to do the n-type doping to the 2H-MoTe 2 channel (Figure S2d, Supporting Information).Finally, arrayed Ti/Au (10/50 nm) top-gate electrodes were fabricated by electron-beam evaporation (EBE).Figure 1a,b is schematic diagram and optical image, respectively, of the large-scale n-type 2H-MoTe 2 FET array.Furthermore, we characterized the interface between 2H-MoTe 2 and 1T′-WTe 2 using high-resolution transmission electron microscopy (HR-TEM) and selected-area electron diffrac- For comparison, we fabricated coplanar metallic 1T′-MoTe 2 and conventional metal (Ti/Au and Pd/Au) contacted n-type FET devices.In all the devices, 6 nm thick 2H-MoTe 2 and 25 nm HfO 2 layer serve as the channel and gate dielectric layer, respectively.The coplanar 1T′-MoTe 2 electrodes were fabricated by a similar method as that for coplanar 1T′-WTe 2 electrodes (see Experimental Section for details).The metal electrodes were fabricated on the two ends of 2H-MoTe 2 by EBE.The representative transfer curves of the four kinds of devices (the channel length of them is 20 μm) are shown in Figure 1g.All the devices exhibit clear n-type behavior.The statistical data of on-current of them are presented in Figure 1h and Figure S4a (Supporting Information).The average values of on-current of the four kinds of FETs with 1T′-WTe 2 , 1T′-MoTe 2 , Ti/Au and Pd/Au contact electrodes are 94.8 ± 7.2, 30.8 ± 4.9, 42.0 ± 10.1, and 12.0 ± 2.2 nA/μm, respectively, indicating that the contact resistance of coplanar metallic 1T′-WTe 2 is the smallest.Herein, the fact that 1T′-WTe 2 is better than 1T′-MoTe 2 may result from the lower work function of 1T′-WTe 2 , [36] which reduces the corresponding Schottky barrier heights from ≈113 to ≈64 meV (Figure S5, Supporting Information).We further investigated the influence of 2H-MoTe 2 thickness on the device performance.Herein, coplanar 1T′-WTe 2 and 25 nm HfO 2 layer serve as the contact electrodes and gate dielectric layer, respectively.The representative transfer curves of the FETs with MoTe 2 thicknesses of 6, 12, and 18 nm are shown in Figure 2c.The statistical data of electron mobility and on/off ratio of them are presented in Figure 2d and Figure S4b,c (Supporting Information).For the devices with 6, 12, and 18 nm channel thickness, the average mobilities are 1.33 ± 0.11, 0.71 ± 0.06, and 0.35 ± 0.06 cm 2 V −1 s −1 , respectively, and the average on/off ratios are 11.5 ± 2.0, 3.74 ± 0.51, and 0.83 ± 0.14 × 10 3 , respectively.These results show that the MoTe 2 FET has better performance when the channel layer becomes thinner.It is reported that electron-charge transfer from oxygen vacancies that exist at the interface [10,37,38] may be an important reason for the ALD-induced n-type doping in TMDCs.Therefore, it is comprehensible that the doping effect is better in thinner 2H-MoTe 2 .
To testify the performance uniformity and reliability of the devices fabricated with the above-optimized parameters (6 nm thick channel, 1T′-WTe 2 contacts, and 25 nm thick HfO 2 gate dielectric layer), we measured a 5×6 MoTe 2 FET array (as shown in Figure 1b).All the 30 FETs work normally and the transfer curves of all the 30 devices are shown in Figure S6 (Supporting Information).The electron densities, field-effect mobilities, and on/off ratios of the devices are narrow-distributed, with average values of 1.7 ± 0.1 × 10 13 cm −2 , 1.6 ± 0.1 cm 2 V −1 s −1 , and 2.1 ± 0.3 × 10 4 , respectively (Figure 3), indicating the high uniformity and reliability in performance.
To demonstrate the potential application of the n-type MoTe 2 in fabrication of logic device, we designed and fabricated large-scale MoTe 2 -based homogeneous CMOS inverter array.Each CMOS inverter is composed of an original p-type MoTe 2 transistor and a n-type MoTe 2 transistor doped by ALD method.
First, a wafer-scale high-quality few-layer 2H-MoTe 2 film was synthesized via the CVD method (Figure S7a, Supporting Information).Then large-scale isolated 1T′-WTe 2 /2H-MoTe 2 /1T′-WTe 2 /2H-MoTe 2 /1T′-WTe 2 array was fabricated directly on the growth substrate by similar method as described in fabricating n-type FET array (Figure S7b-d, Supporting Information).It is worth noting that before the following ALD n-doping process, the 2H-MoTe 2 is p-type.Then, Al 2 O 3 (15 nm) patterns were fabricated on the right 2H-MoTe 2 channel by UV lithography, ALD, and lift-off process to dope it into n-type (Figure S7e, Supporting Information).Notably, the reaction temperature of the ALD process for the patterned Al 2 O 3 layer was lowered to 80 °C to prevent the unnecessary contamination of the equipment from photoresist.Next, an 8 nm Al 2 O 3 seed layer and 20 nm HfO 2 gate dielectric were deposited in sequence by EBE and ALD, respectively, on the whole CMOS device (Figure S7f, Supporting Information).The seed layer is used to protect the left 2H-MoTe 2 channel from being n-doped during the later-on ALD process. [11,39]The electrical properties of the n-and p-FET components were characterized after the fabrication of the CMOS inverter array.The representative results are shown in Figure 4c, indicating that the ALD process for patterned Al 2 O 3 has completely converted the exposed right 2H-MoTe 2 channel from p-to n-type.Meanwhile, the left 2H-MoTe 2 channel remains typical p-type.Notably, for the two sweeping directions of gate voltage, the transfer curves present almost no hysteresis.We attribute this merit to the transfer-free fabrication approach as well as the encapsulation effect of the oxide layers.
Figure 4d shows the representative VTCs of the CMOS inverters at various V dd .For each applied V dd , the VTC shows clear logic swing.The corresponding voltage gain (the maximum value of (− dV out dV in )) plots and power consumption (V dd × I dd ) characteristics are shown in Figure 4e,f.The voltage gains are 1.1, 2.7, 5.2, 8.6, 11.5, respectively, at V dd = 1, 2, 3, 4, 5 V, satisfying the requirement of logic application.The peak power consumption is as low as 0.44 nW at V dd of 1 V, close to the lowest value of the so-far reported TMDC-based CMOS inverters. [11,20,22]In particular, for the two sweeping directions of V in , all the VTC curves present small hysteresis.Correspondingly, for identical V dd , the voltage gains and peak power consumptions change little, indicating that the CMOS inverters have high stability in practical operation.Figure S8 (Supporting Information) shows the noise mar-gin property of the inverter.The extracted noise margins for low and high input voltages are 0.41 V dd and 0.19 V dd .The total noise margin is ≈ 0.60 V dd , satisfying the requirement in multistage logic circuits.
We further investigated the dynamic switching behavior of the CMOS inverters.Herein, the inverter was driven by square wave V in with various frequencies (F).The high and low levels of V in are 5 and 0 V, respectively.Figure 5a,b shows the time-dependent V in and V out under F of 100 and 1000 Hz, respectively.We can see that the logic switching behavior is clear at 100 Hz and the flat part of the time-dependent V out curve disappears at 1000 Hz.The rising time (t r ) and falling time (t f ) are 0.4 and 0.9 ms, respectively, calculated at 10% and 90% of V out amplitude at 100 Hz.
Finally, in order to investigate the performance uniformity and reliability of the as-fabricated CMOS inverters, a 5 × 5 device array was measured.Among the 25 devices, 23 worked normally, corresponding to 92% device yield.The other two devices were burned during the measuring process.The VTCs of the 23 inverters are highly consistent as shown in Figure S9 (Supporting Information).All of them show clear signal inversion, indicating the high uniformity and reliability of the devices.The peak voltage gains and power consumptions of these devices are narrow-distributed, with average values of 0.86 ± 0.07 and 0.44 ± 0.03 nW, respectively (Figure 5c,d).It is worth noting that all the characteristics of the CMOS inverters presented above are measured after the devices have been kept in air for 16 months.The performances of original ones are shown in Figure S10 (Supporting Information).We can see that the performances of the CMOS inverters are even better after 16 months.We attribute the extraordinary uniformity, reliability, and ambient stability of the homogeneous CMOS inverters to the relatively high chemical stability of 2H-MoTe 2 , the reliable n-doping method, and the novel device structure.

Conclusion
In summary, we successfully fabricated 2D MoTe 2 -based largescale n-type FET Array.Coplanar metallic 1T′-WTe 2 was chosen as source and drain electrodes to reduce contact resistance and was proved to be better than coplanar metallic 1T′-MoTe 2 and conventional metals (Ti/Au and Pd/Au).High-k HfO 2 was adopted as gate dielectric.We found that compared to Al 2 O 3 , ALD of HfO 2 has better n-doping effect on 2H-MoTe 2 , and the n-doping effect is better for thinner 2H-MoTe 2 .Notably, we have accomplished depositing gate dielectric layer and n-doping in one step, which greatly simplifies the device fabrication process.The optimized large-scale n-type MoTe 2 FETs perform typical n-type characteristics with average electron density, mobility, and on/off ratio to be ≈ 1.7 × 10 13 cm −2 , 1.6 cm 2 V −1 s −1 , and 2.1 × 10 4 , respectively.Furthermore, we designed and fabricated a large-scale MoTe 2 -based homogeneous CMOS inverter array.The CMOS inverters show clear logic swing and high device yield of ≈ 92%.Besides, the CMOS inverters present low power consumptions, with an average value of 0.44 nW at V dd of 1 V.It is worth noting that the CMOS inverters exhibit small hysteresis in their VTCs and work well after being kept in air for 16 months, indicating high device stability in practical operation.Moreover, the statistical results show that these devices are with high performance uniformity and reliability.We attribute our achievement to the high-quality 2D materials, the novel device structure, and the facile and reliable fabrication that is free from transfer process and compatible with traditional silicon technology.Our work promotes the practical application of 2D materials in nanoelectronics integration.

Experimental Section
Synthesis of 2H-, 1T′-MoTe 2 , and 1T′-WTe 2 Films: The MoTe 2 (WTe 2 ) films were grown by tellurizing Mo (W) films at atmospheric pressure using a horizontal tube furnace equipped with mass flow controllers and a vacuum pump.First, Mo (W) films were deposited on p + -Si/SiO 2 (285 nm) substrates using magnetron sputtering.The substrates and Te powders were placed in a quartz boat, which was later inserted into a 1inch diameter quartz tube inside the furnace.After evacuating the quartz tube to < 10 mTorr, high purity Ar gas was let in at a rate of 500 sccm until atmospheric pressure was reached.Then Ar and H 2 were let in at flow rates of 5 and 7 sccm, respectively.The growth temperatures were 630, 530, and 560 °C, and the growth times were 3 h, 30 min, and 1 h for 2H-MoTe 2 , 1T′-MoTe 2 , and 1T′-WTe 2 films, respectively.After the growth, the furnace was cooled down to room temperature naturally.The thickness of the 2H-MoTe 2 was controlled by the thickness of the Mo film.The thicknesses of the 2H-MoTe 2 used in this work were ≈6, 12, and 18 nm, corresponding to the Mo films of ≈2, 4, and 6 nm.The thicknesses of 1T′-WTe 2 and 1T′-MoTe 2 used in this work were both ≈ 20 nm.For the patterned growth of MoTe 2 (WTe 2 ), Mo (W) film was pre-patterned by UV lithography followed by magnetron sputtering and lift-off process.
Fabrication of the FET Arrays and the CMOS Inverter Array: The main fabrication steps have been described in the main text.Here, some detailed information was provided as supplementary.The Ti/Au and Pd/Au electrodes were fabricated by UV lithography, electron-beam evaporation, and lift-off process.The Mo top-gate electrodes were fabricated by UV lithography, magnetron sputtering, and lift-off process.In the reactive ion etching (RIE) process, the gas used to etch both the MoTe 2 and WTe 2 films were Ar and SF 6 .In the atomic layer deposition (ALD) process, high-purity N 2 served as carrier gas.The precursors of HfO 2 were tetrakis (dimethylamido) hafnium and deionized water.The precursors of Al Characterizations: Both optical images and Raman spectra were collected by micro-zone confocal Raman system (WITec alpha 300R) attached with a 532 nm laser.The thickness of the MoTe 2 film was measured by atomic force microscope (Asylum Research, Cypher S).The HR-TEM was carried out using a transmission electron microscope (FEI Tecnai F20) with an acceleration voltage of 200 kV.The electrical measurements were conducted with semiconductor characterization system (Keithley 4200A-SCS), which was connected to a probe station.For the dynamic switching performance measurement, a function generator (Tektronix AFG 3102) and a digital oscilloscope (Tektronix DPO 2024) were employed to generate the V in and record the V out , respectively.Both the function generator and the digital oscilloscope had common ground with the semiconductor characterization system, which provided the V dd .All the characterizations were performed in dark and room temperature.

Figure 1 .
Figure 1.a,b) Schematic diagram and optical image of the large-scale n-type 2H-MoTe 2 FET array with coplanar metallic 1T′-WTe 2 contacts, respectively.The HfO 2 layer serves as the gate dielectric and the corresponding ALD process dopes the 2H-MoTe 2 into n-type.The optical image shows a 5 × 6 FET array.c-f) Characterizations of the interface between 2H-MoTe 2 and 1T′-WTe 2 .(c) TEM image at the interface.(d) SAED pattern taken from the MoTe 2 region, showing a single set of diffraction patterns with sixfold symmetry corresponding to the single-crystalline 2H-MoTe 2 .(e) SAED pattern taken from the WTe 2 region, showing a series of diffraction rings related to the polycrystalline 1T′-WTe 2 .(f) HR-TEM image at the interface.The 1T'-WTe 2 stitches seamlessly to the 2H-MoTe 2 .g) The representative transfer curves and h) statistical data of the average values of on-current of the MoTe 2 FETs with four different contacts.For each case, we randomly selected six devices for electrical characterization and statistical analysis at the source-drain bias (V ds ) of 1 V.

Figure 2 .
Figure 2. a,b) The top-gated transfer curves of the n-type MoTe 2 FETs with HfO 2 (red curve) and Al 2 O 3 (black curve) gate dielectrics.(a) The representative transfer curves.(b) The transfer curves of randomly selected nine devices in each case.c,d) The representative transfer curves and statistical results, respectively, of the n-type MoTe 2 FETs with channel thicknesses of ≈6, 12, and 18 nm.For each case, we randomly selected seven devices for calculating the average values of mobility and on/off ratio.For all the FETs, the channel length is 10 μm.
Finally, arrayed (40 electrodes were fabricated by magnetron sputtering as the common top gates for both the p-and n-MoTe 2 FETs.The schematic diagram and optical image of the large-scale MoTe 2 -based homogeneous CMOS inverter array are shown in Figure 4a,b, respectively.The corresponding CMOS inverter circuit diagram is shown in the inset of Figure 4b.Herein, the source of n-MoTe 2 FET is grounded, the source of p-MoTe 2 FET serves as the supply voltage electrode (V dd ), and the common top gate and the middle common 1T′-WTe 2 contact electrode serve as the input voltage (V in ) and output voltage (V out ) electrodes, respectively.

Figure 4 .
Figure 4. Characterizations of the large-scale MoTe 2 -based homogeneous CMOS inverter array.a,b) Schematic diagram and optical image of the CMOS inverter array, respectively.The ALD process for the patterned Al 2 O 3 layer (15 nm) fabricated on the right 2H-MoTe 2 channel dopes it into n-type.The Al 2 O 3 seed layer (8 nm) fabricated by EBE protects the left 2H-MoTe 2 channel from being n-doped during the later-on ALD process of 20 nm HfO 2 gate dielectric.The coplanar 1T′-WTe 2 serves as the contact electrodes.The channel length and width are 10 and 20 μm, respectively, for both n-and p-FETs.Inset: the circuit diagram of the CMOS inverter.c) The transfer curves of the n-and p-channel FET components in a CMOS inverter when the gate voltage sweeps back and forth.The arrows indicate the gate voltage sweeping directions.d) The VTCs of the CMOS inverter at various V dd when the input voltage back and forth.e,f) The representative voltage gain plots and power consumption characteristics, respectively, of the CMOS inverter at various V dd .The voltage gains are ≈ 1.1, 2.7, 5.2, 8.6, 11.5, respectively, at V dd = 1, 2, 3, 4, 5 V.The peak power consumption is as low as 0.44 nW at V dd of 1 V.The arrows in (d,f) indicate the sweeping directions of V in .

Figure 5 .
Figure 5. a,b) The dynamic switching behavior of the CMOS inverters.Herein, V in is square wave switching between 5 and 0 V, V dd = 3 V. (a,b) are time-dependent V out curves under frequencies (F) of 100 and 1000 Hz, respectively.The logic switching behavior is clear at 100 Hz and the flat part of the time-dependent V out curve disappears at 1000 Hz. c,d) The statistical histograms of (c) voltage gains and (d) peak power consumptions of the 23 devices measured on a 5×5 CMOS inverter array.The gains and power consumptions are narrow-distributed, with average values of 0.86 ± 0.07 and 0.44 ± 0.03 nW, respectively.
2 O 3 were trimethylaluminum and deionized water.The reaction temperatures of the ALD process for both HfO 2 and Al 2 O 3 layers in the FETs were 90 °C, while that for patterned Al 2 O 3 layers in the CMOS inverters was 80 °C.The thicknesses of the HfO 2 and Al 2 O 3 were precisely controlled by the counts of ALD cycles.