Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate

A pulsed laser annealing method is utilized to directly synthesize nickel silicide (NiSi) as a contact material to improve the contact of electric devices. Three laser wavelengths, 355 nm (ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), are used for the NiSi synthesis during the pulsed laser annealing process. A NiSi phase with low sheet resistance is formed by an ultraviolet laser annealing (ULA) process without damaging the polyimide (PI) substrate. With the integration of the ULA process‐induced NiSi into p‐nnel MOSFET (PMOS) and n‐channel MOSFET (NMOS) devices, the on/off ratio improves significantly, and the field‐effect mobility increases by 30% because of the reduction in contact resistance from 21 to 8.5 kΩ. In addition to the PMOS and NMOS, the gains of the CMOS inverter at different Vdd values are improved by at least 30%. Moreover, the static noise margin of 6T‐SRAM is elevated from 0.82 to 1 V at Vdd = 4 V. The ability of the ULA process to synthesize a high‐quality NiSi layer on a flexible substrate is demonstrated. The integration of NiSi into electrical devices offers a new pathway for improving the electrical behavior of flexible devices.


Introduction
Over the past few years, the emergence of Internet of things (IoT) in human society has not gotten rid of the development of wearable devices. [1]The wearable devices are flexible and often used for various sensors with digital logic circuits that can be directly put on the human body or combined with items, such DOI: 10.1002/aelm.202300353 as accessories, clothes, and shoes. [2,3][6] Nevertheless, several challenges remain in the evolution of flexible electronics, including the selection of the buffer layer, construction of the active layer, and degradation of the devices after bending.The lowtemperature environment is required for the processes mentioned above when conducting the experiment; otherwise, the flexible substrate will be damaged during high-temperature processing. [7]wing to the demand for a low-thermalbudget process for flexible devices, the utilization of a high-temperature process is confined, resulting in relatively poor electrical performance.For CMOS and SRAM technologies, metal silicides have been investigated to reduce the contact resistance in integrated circuits, resulting in better electrical performance of electronic components over the past decades. [8,9]For scaling down the dimensions of CMOS and SRAM technologies continuously, metal silicides on the contact of source/drain (S/D) regions remarkably impact both the intrinsic device resistance and the parasitic external resistance, as well as the RC delay and drive current.The advanced semiconductor industry employs three typical types of metal silicides: titanium, cobalt, and nickel silicides, namely TiSi 2 , CoSi 2 , and NiSi 2 , respectively.[12] However, it often fails to form the phase with the lowest resistivity at a smaller level because it suffers from a bridging effect, shows a higher possibility to react with SiO 2 and dopant, and under a narrow linewidth effect, which causes leakage current.As the technology node shrinks, CoSi 2 has emerged as an alternative to TiSi 2 owing to its lower resistivity, better thermal stability, less stress of the film, and superior selective etching ability. [13,14]However, applying CoSi 2 to even smaller scale of CMOS devices is difficult because of the high silicon depletion and the junction spiking problem caused by the high sensitivity to native oxide and oxygen environments.Starting from the 90 nm technology node in CMOS technology, nickel silicide (NiSi) is thought to be a more suitable option for electrical devices at a smaller scale.[17][18] In addition, NiSi does not exhibit a bridge effect or narrow linewidth effect at a small scale.Thus, NiSi was commonly applied to study the reduction in the contact resistance of planar devices until the appearance of FinFETs at the 14 nm technology node.
[21][22][23][24][25][26][27] The furnace annealing has the advantage of mass production; however, but it is a time-consuming and highthermal-budget process. [21]Another common method of annealing is rapid thermal annealing (RTA), which has a lower thermal budget than the furnace annealing process.However, stress may be produced in the materials because of the high rate of elevated temperature during RTA. [22]][25][26][27] However, few studies have integrated NiSi into flexible electronics.
In this regard, we investigated an efficient and heat-resistant pulsed laser annealing (PLA) method for integrating NiSi into a flexible device.Here, three laser wavelengths, 355 nm (ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), were used for the NiSi synthesis during the pulsed laser annealing process.XPS and TEM analyses were conducted to investigate the phase and crystalline quality of nickel silicide under PLA with different wavelengths.With the integration of ultraviolet laser annealing (ULA) induced NiSi into p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) devices, the on/off ratio improved significantly, and the field-effect mobility increased by 30% because of the reduction in contact resistance from 21 to 8.5 kΩ.In addition to the PMOS and NMOS, the gains of the CMOS inverter at different V dd values were improved by at least 30%.Moreover, the static noise margin of 6T-SRAM is elevated from 0.82 to 1 V at V dd = 4 V.We demonstrated the ability of the ULA process to synthesize a high-quality NiSi layer on a flexible substrate.The integration of NiSi into electrical devices offers a new pathway for improving the electrical behavior of flexible devices.

Results and Discussion
Figure 1a shows a schematic for the design of pulsed laser annealing methods for synthesizing NiSi as a contact window for contact resistance reduction, thus improving a poly-silicon thin film transistor.First, a SiO 2 /Al/SiO 2 thin film was deposited on a flexible polyimide (PI) substrate as a laser-stop layer.An amorphous Si layer, crystallized into polycrystal Si by an ultraviolet laser annealing process, was then formed on the top of the laser stop layer.After ion implantation and dopant activation, the sheet resistance of the poly-Si layer is ≈350 Ω sq −1 .Then, an extra 10 nmthick Ni thin film was deposited on the poly-Si layer by physical vapor deposition (PVD) after surface oxide cleaning.Three laser wavelengths, 355 nm (ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), were used for the NiSi synthesis during the pulsed laser annealing process.After the pulsed laser annealing process, the excess unreacted nickel on the surface of the samples was removed by dipping in 10% HNO 3 solution at 75 °C for 10 min.The reflectance of Ni as a function of the wavelength is shown in Figure 1b.The reflectance levels of Ni under ultraviolet, green, and infrared laser illumination were 43%, 60%, and 98%, respectively.From the ≈100% reflectance under the infrared laser illumination, whether the light absorption or the heat generated from the substrate and the buffer layer, which is dominated on the formation of the NiSi 2 , was investigated through further experiments.The reduction in sheet resistance first confirmed the formation of Ni-silicides film after the laser annealing. [28]The significant change of sheet resistance is related to the phase transition from pure Ni to NiSi x , which includes NiSi and NiSi 2 .Thus, the sheet resistance was measured with the increase of laser power to study the phase transition by the laser irradiation.The correlations between the sheet resistance and the laser power under different laser annealing conditions are shown in Figure 1c.The laser annealing process was carried out by an increase in laser power until the PI substrate could not withstand the thermal heating effect.Here, the relatively low laser power is required to reach the minimum value of sheet resistance.As a result, the sheet resistance under the ULA process started to decrease at the laser power value >0.6 W and the minimum sheet resistance of 33 Ω sq −1 can be achieved at a laser power of 1.1 W. The sheet resistance under green laser annealing (GLA) shows a trend similar to that under the ULA process, for which the sheet resistance value starts to reduce at a laser power of 0.5 W. Note that the minimum value of 35 Ω sq −1 at a power of 2 W can be obtained after the GLA process.Although the minimum values of sheet resistance occurred at different laser powers with ultraviolet and green laser annealing, the difference in the laser power required to obtain the lowest sheet resistance, which can be attributed to the difference in the reflectance of the Ni thin film.The ultraviolet laser with the lower Ni reflectance provides a higher laser energy to form a NiSi film.In addition, the sheet resistance of the nickel silicide film only significantly decreased after applying a higher power of 13 W for the infrared laser annealing (ILA) process while the substrate could not afford an even higher laser power.The increase of substrate temperature is a way to assist the material more facilely achieve the phase transition from Ni to nickel silicide and to protect the substrate from damage caused by high laser power.In the inset of Figure 1c, we changed the temperature of the substrate holder instead of the laser power to further investigate the phase formation of nickel silicide during the ILA process.The sheet resistance decreases with an increase in temperature, showing a minimum value of ≈50 Ω sq −1 when raising the temperature to 175 °C, namely the phase transformation starting temperature.To analyze the laser-annealed films, XRD was first used to identify the phases of the nickel silicide thin film after the ULA process with the laser power of 0.9 W as shown in Figure 1d.The diffraction peaks of NiSi 2 are located at 28.4°, 47.7°, and 56.5°.The diffraction peaks of the Si and NiSi films were located at similar positions, including 28.4°, 45.7°, and 56.5°, for which two of the peaks were at the same locations as the peaks of NiSi 2 . [29]o further distinguish the growth of the different phases of NiSi 2 and NiSi after applying the ULA process, XPS and HRTEM were used to investigate the compositions and crystalline structures of NiSi x .Figure 2a shows the XPS depth profiles obtained at different laser annealing processes, including ULA, GLA, and ILA processes.The depth of NiSi x was divided into three parts based on results after applying the ULA process.Part I is the surface region, Part II is the nickel silicide forming region, and Part III is the nearly poly-Si layer region.From the Part I region in the depth profiles, the ratio of Ni and Si is unstable, which should result from surface oxide formation when preparing the samples under each of the three types of laser conditions.From Part II region, a clear NiSi phase and a relatively stable Ni/Si ratio were observed in the XPS depth profiles of the ULA process.Mean-while, the ratio of Ni to Si in the GLA process was 4:6, which implied that the non-uniform phase of NiSi x was formed after the GLA process.For the depth profile of the ILA process, relatively low contents of Ni and Si in Part II were observed, which verified almost 100% Ni reflectance under the ILA process, resulting in the unsuccessful synthesis of NiSi.Furthermore, the evolution of the Ni 2p 2/3 spectra for each laser process is shown in Figure 2b, for which different periods of the Ar+ sputtering process were applied. [30,31]In the Ni 2p 2/3 spectra of the ULA process, the intensity was quite low at the surface (0 s), indicating that Ni does not appear at the surface and it is assumed that SiO 2 forms at the surface after the annealing process. [32]The Ni 2p 2/3 peak of the ULA process at greater depths (sputtering from 35 to 125 s) was located at 853.5 eV, corresponding to the position of the NiSi film, revealing the evidence of the NiSi formation after the ULA process.In the Ni 2p 2/3 spectra of the GLA process, the NiSi peak only appeared at a shallow depth (sputtering time of 55 s).The evolution of Ni 2p 2/3 spectra was also observed after the ILA process.The peak at the surface was more significant than those of the other two laser processes since the heating holder is more significant because of higher absorption by the metal holder than that of the targeted sample, resulting in the diffusion of Ni atoms to the surface of targeted samples.Non-reacted and pure Ni was observed at a depth of sputtering for 55 s, and the Ni -silicide peak appeared only at the depths of sputtering for 85 and 125 s, respectively.Further details of the crystalline structure and thickness of the laser-annealed NiSi films were discussed.Figure 2c-e presents HRTEM images of the nickel silicide films formed after the ULA, GLA and ILA processes, respectively.Figure 2c shows the nearly single crystal phase of the NiSi film after the ULA process from the SAED (Selected Area Electron Diffraction) results.The thickness of the NiSi film, being ≈20 nm, can be observed.To study the impact of the NiSi layer on device performance, we integrated the laser-annealed NiSi layer into the S/D contact of a p-channel MOSFET (PMOS) and a n-channel MOSFET (NMOS) devices.The corresponding electrical properties of the MOSFET with the nickel silicide contact formed by each laser illumination process were analyzed, with which a channel width (W) of 4 μm and a channel length (L) of 4 μm for the device were fixed in the I-V measurements.Figure 3a shows the transfer characteristics of the PMOS on a linear scale under different laserannealing conditions.The results demonstrated that the drain current (I D ) of devices after integrating NiSi grown with different laser sources and powers were higher than those without an integrated source, demonstrating the benefit of NiSi integration for contact.The best parameter of the ULA process can be achieved at the laser power of 0.9 W, which performed the highest I D .The I D decreases as the laser power increases under the same laser source.The highest I D of the PMOS with the ULA process is ≈1.5 times larger than the highest I D with the GLA process integration, corresponding to the better crystallinity of the NiSi layer (Figure 2).On the other hand, the I-V characteristics of the NMOS with a linear scale (Figure 3d) exhibited the highest I D performance when the NiSi layer was integrated using the ULA process at the laser power of 1 W. The I D performance of the NMOS integrated with the NiSi grown by the ULA process is better than that of the device integrated with the NiSi grown by the GLA process.Note that both are better than that without any integrated NiSi.The I-V characteristics of the PMOS and NMOS with a logarithmic scale are shown in Figure S2  ) is the slope of I-V characteristics for PMOS at V DS = −1 V and NMOS at V DS = 1 V, respectively.The fieldeffect mobilities of PMOS and NMOS devices increase by at least 30% after the addition of an integrated NiSi layer in the contact region.Moreover, the improvement in field-effect mobility decreases as the channel length increases because of the superiority of R ch over R c for longer channel lengths rather than R c of NiSi/Si contact.The on/off ratio also increases significantly after adding the NiSi layer owing to the improvement in field-effect mobility (Figure 3c,f).In addition to the comparison of the field-effect mobilities and on/off ratios with varying channel lengths, we compared the changes in the threshold voltage (V th ) and subthreshold swing (SS) before and after adding the ULA-integrated NiSi layer (Figure S3b,c,e,f, Supporting Information).The values of V th for the PMOS and NMOS approached 0 V after adding the integrated NiSi layer, indicating that we could fabricate PMOS and NMOS devices with smaller turn-on voltages.Meanwhile, the SS values for PMOS and NMOS devices decreased after the addition of the integrated NiSi layer, which enhanced the speed of turning on the devices.
To evaluate I-V characteristics of NMOS and PMOS devices under different laser-annealing processes at the same value of V d , we compared the I-V characteristics of devices at V d = |0.5|V and |1| V as shown in Figure 4a.The I d -V g curves present a slight increase in I d with larger V d .Moreover, the results show similar values of SS and V th at V d = |0.5|V and |1| V.The devices demonstrated a minor V d dependence on the I d -V g performance.In addition to the V d -dependence of the I-V curves, the contact resistance can be further calculated using the TLM method to verify the reduction in the contact resistance after adding the ULAintegrated NiSi layer as shown in Figure 4b.The total resistance followed the equation where R C is the contact resistance and R Ch is the channel resistance.R Ch can be calculated from the equation ) , where W eff is the effective channel width, or from the slope of the linear region presented in Figure 4b by the equation ) and C g μ(V g -V th ) is the slope of the lin-ear region.In Figure 4b, R ch were 18.7 and 20.4 kΩ derived by the slopes of the device without (w/o) NiSi and with (w/) integrated NiSi layer, respectively.More importantly, the value of R c for each device could be calculated from the y-intercept as shown in Figure 4b, which are 21 and 8.5 kΩ, respectively.The lower R c of the device with the integrated NiSi indicates that adding the NiSi layer improves the contact in the S/D region.The reliability of PMOS and NMOS devices is further discussed in terms of the hot carrier stress effect in Figure 4c and Figures S4 and S5 (Supporting Information), respectively.The voltages of V g and V d were controlled at constant −5 V for the PMOS device and 5 V for the NMOS device to study the Hot carrier effect, which led to the degradation of devices.The I-V characteristics of the PMOS device without NiSi and w/ NiSi under different stress times (Figure S4, Supporting Information) demonstrated similar electrical results.In contrast, the I-V curves of the NMOS device exhibited a significant gain in V th and leakage current for the w/ NiSi integrated device (Figure S5, Supporting Information).Moreover, the V th shift (ΔV th ) with respect to stress time for PMOS and NMOS devices were shown in Figure 4c,d, respectively.The ΔV th can be expressed by the power law function of time t n , ΔV th  t n , where time (t) is stress time, and n is the power law factor that could be calculated from the slope of the ΔV th curve.Generally, defects are mainly caused by carriers trapped in the gate oxide when n ranges from 0.1 to 0.3.Furthermore, when n ranges from is 0.3 to 0.6, most defects are generated from the interfaces between the channel, the gate oxide, and the grain boundary of poly-Si.Comparing the V th degradation curves of the w/o NiSi and w/ NiSi PMOS devices, the power law factors were 0.13561 and 0.20128, respectively, indicating that the dominant degradation was oxide trapping for the two types of PMOS devices (Figure 4c).When we compared the V th degradation curves w/o NiSi and w/ NiSi for NMOS devices, the n value of the NMOS w/ NiSi layer is 0.4186, which is larger by 0.3 than the n value (0.28351) of the NMOS w/o NiSi layer.The increase in the n value of the NMOS with the integrated NiSi layer indicates that the ULA process for the NiSi formation can be attributed to changes in the degradation mechanism.In addition, the n value of the NMOS with the integrated NiSi is much higher than that of the PMOS with the integrated NiSi because of the carrier difference between the electrons and holes for each type of device.
In addition to the typical electrical performance of NMOS and PMOS devices, we investigated the electrical properties of the CMOS inverter and 6T-SRAM with an integrated NiSi layer.Figure 5a shows the V out -V in characteristics (VTC) of w/o NiSi and w/ NiSi integrated CMOS inverters as the function of V dd for different supply voltages (V dd = 2, 3, and 4 V) measured by the nano-device parameter measurement system.The inset of Figure 5a shows an optical microscopy (OM) image of the CMOS inverter and the corresponding layout of the CMOS inverter, including a pair of NMOS and PMOS is shown in Figure S6a (Supporting Information).With the integration of the ULA-formed NiSi layer in the S/D contact region, the I-V characteristics become sharper, and the voltages for the input voltages (V in ) are located closer to V dd /2.The sharper curve is attributed to the reduction in the SS of the PMOS and NMOS devices.In contrast, the more ideal transition voltages of the CMOS inverter are attributed to the V th modulation with the ULA-integrated NiSi. Figure 5b shows the relevant gains (-dV out /dV in ) of the same in-verter at V dd = 2, 3, and 4 V.The peak gains increased by 34%, 44%, and 33% at V dd = 2, 3, and 4 V, respectively when the CMOS inverter was integrated with the NiSi layer, resulting in a higher switching speed while operating the inverter.We further investigated the benefits of integrating the ULA-induced NiSi with memory applications.Figure S6b (Supporting Information) shows the layout of the 6T-SRAM, composed of four NMOS and two PMOS.The stability of the 6T-SRAM can be derived using static noise margin (SNM), which is the side length of the maximum square in the two VTC of the devices.The higher the SNM value is the better the stability of the device is.The VTC of the 6T-SRAM without the integrated NiSi is shown in Figure 5c, and the values of SNM are 0.37, 0.53, and 0.82 V at V dd = 2, 3, and 4 V, respectively.Moreover, the unequal size of the squares owing to the imperfect value of V th at each V dd resulted in a smaller SNM value obtained from this device at varying V dd .In Figure 5d, the VTCs of the 6T-SRAM with integrated ULA-induced NiSi (at V dd = 2, 3, and 4 V) show larger SNM values compared to devices without the integrated NiSi because of the V th modulation in the previous discussion of the CMOS inverter.The SNM values of 6T-SRAM with integrated NiSi are 0.5, 0.78, and 1 V, and increase by 35%, 47%, and 22% compared to the w/o NiSi-integrated device at V dd = 2, 3, and 4 V, respectively.
As the ULA process for the NiSi formation has the advantage of synthesizing a NiSi layer at room temperature without damaging the underlying glass or flexible PI substrate.Therefore, it can be used for flexible devices.To demonstrate this concept, we separated the devices from the glass substrate as flexible devices by a direct mechanical peel-off process.The whole sample was illuminated by a UV light ( = 365 nm) for 15 min to release the UV tape from the sample.Note that a UV tape was placed on and attached to the surface of the sample because there was stronger adhesion between the UV tape and the sample than between the sample and glass substrate.After the direct mechanical peel-off process, the PI side of the sample was taped on another transparent supporting film.We investigated their flexibility and stability by measuring the overall electrical performances of the devices for various bending cycles.Note that all NMOS, PMOS, CMOS inverters, and 6T-SRAM were placed on a 6-inch flexible wafer, as shown in the top photograph in Figure 6a.The bending test was performed using an auto-stretch machine with a bending radius of 40 mm as shown in the bottom schematic of Figure 6a.The electrical characteristics were measured after several bending cycles of 10, 100,1000, and 10 000 cycles, respectively.The I-V characteristics of the NMOS exhibited similar results before 1000 bending cycles and are slightly degraded after 10 000 bending cycles as shown in Figure 6b.Meanwhile, the I-V characteristics of the PMOS also exhibit slight degradation after the bending test of 1000 cycles (Figure 6c).The degradation of the electrical performances of the NMOS and PMOS after bending suggests a deterioration in the performance of the CMOS inverter in the following measurements.The VTC of the CMOS inverter before and after 10 000 bending cycles are shown in Figure S7 (Supporting Information).The gain of the CMOS inverter before and after 10 000 bending cycles is shown in Figure 6d.All gains at V dd = 2, 3, and 4 V were reduced by 20% after bending because of the degradation of the SS of the NMOS and PMOS. Figure 6e compares SNM values of the 6T-SRAM before and after 10 000 bending cycles.The SNM values decrease by 10% after 10 000 bending cycles at different V dd .As stated above, the devices with the integrated ULA-induced NiSi exhibited good stability after bending.
The study demonstrated the capability of forming NiSi via the ULA process on a flexible PI substrate.The integration of NiSi greatly enhanced the electrical performance of the flexible CMOS inverter and 6T-SRAM devices.Overall, a new route for improving the function of wearable electronics, which is a significant part of the IoT generation, is proposed.

Conclusion
The low-thermal-budget PLA method was utilized to synthesize NiSi in the S/D region, which we integrated into several types of flexible electric devices.Three PLA processes with three kinds of laser wavelengths, namely ULA, GLA, and ILA processes, were used to compare the results of nickel silicide formation.From the sheet resistance measurements under each laser annealing process, nickel silicide with the smallest sheet resistance was formed by the ULA process at the lowest power of the laser without damaging the flexible PI substrate.XPS and TEM results were conducted to investigate the phases and crystalline quality of nickel silicide, exhibiting the formation of the NiSi phase with the best crystallinity after the ULA process.The on/off ratios of the PMOS and NMOS devices increase significantly and the fieldeffect mobility by 30% after integrating ULA-induced NiSi.In addition, the reduction in R c indicates evidence of improved electrical performance after the NiSi integration.The stabilities of the devices were further investigated using a hot carrier test.As extended applications, the voltage gain of the CMOS inverter was improved by 30% and the SNM of the 6T-SRAM was raised to 1 V at V dd = 4 V.

Experimental Section
Substrate Fabrication: Polyimide (PI) was obtained from a domestic polyimide foundry and slit-coated on a glass substrate to prevent stress caused by spin coating and CMP.Then, the preparation of the sample before the PLA process was started by depositing a sandwiched buffer layer of SiO 2 /Al/SiO 2 that SiO 2 was deposited by Oxford plasma-enhanced chemical vapor deposition (PECVD) process (13.56 MHz) at 350 °C and Al was deposited by physical vapor deposition (PVD) on a glass/polyimide substrate.The CMP process was utilized to have a flat surface followed by depositing a 100 nm-thick amorphous Si (a-Si) film using PECVD at 400 °C.Subsequently, the sample was placed in the annealing furnace at 450 °C at a high vacuum level for 2 h to eliminate hydrogen atoms that remained in the a-Si film after the PECVD process.Then, the a-Si film was crystallized into a poly-Si film by ultraviolet nanosecond pulsed laser annealing (UV-LSA,  = 355 nm) with a power of 2.5 W and partition of 0.35 mm.The CMP process was repeated to flatten the surface after crystallization.
Photolithography for Pattern Definition: The TEL CLEAN TRACK MK-8 track system, which can provide uniform and steady coating and development was utilized to coat the HDMS and photoresist on the substrate followed by substrate fabrication.All patterning processes here were per-formed using the TEL CLEAN TRACK MK-8 track system to coat the photoresist and develop the pattern, using EVG 62NT contact aligner to expose photoresist, and using LAM2300 etching instrument to etch out the patterns.
Metal Gate Deposition: After pattern definition, the high-k gate dielectric and metal gate materials were deposited on the poly-Si film.The substrate was immersed in a dilute buffered oxide etch (BOE) solution to remove the native oxide formed on the poly-Si film after photolithography.A SiO 2 layer was then deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) to prevent Hf diffusion.Following the ICP-CVD method, a 10 nm HfO 2 layer was deposited as a high-k gate dielectric layer by a plasma-enhanced atomic layer deposition system (PEALD).The PVD process was used to deposit 40 nm-thick TiN and 100 nm-thick Al layers as the metal gates on top of the high- dielectric layer.The Al layer was applied as the laser reflective layer, which had the same purpose as the buffer layer deposited on the PI substrate to prevent the TiN layer from being damaged by laser illumination.Subsequently, photolithography and etching were used to obtain the metal gate pattern.
Ion Implantation, Laser Annealing, and Deposition of Interconnection: Following metal gate patterning, an EHP-500 implanter was used for S/D implantation.BF 2 49+ is the p-type dopant, and P 31+ is the n-type dopant for the doping processes, which were done by ion implantation with a dosage of 5 × 10 15 cm −2 and an energy of 30 keV.Ultraviolet nanosecond pulsed laser annealing was applied with an energy density of 100 mJ cm −2 for activation.Subsequently, 300 nm SiO 2 was deposited as the passivation layer and the interconnect regions on the S/D were etched out after photolithography.A 10 nm-thick Ni layer was deposited on the S/D regions by PVD and transformed into NiSi by the PLA process.The unreacted Ni was removed by dipping the sample in 10% HNO 3 at 75 °C for 10 min.Finally, an additional connection on the metal gate was etched, and the interconnected regions on the S/D and metal gate were filled with Al to complete the overall devices fabrication.
Peel-Off Process for Flexible Devices: A mechanical peel-off process was used after completing the devices fabrication process.A UV tape was placed on and attached to the surface of the sample, and the sample could be easily detached from the glass substrate because there was stronger adhesion between the UV tape and the sample than between the sample and the glass substrate.After the detaching process, the PI side of the sample was taped on another transparent supporting film.Then, the whole sample was illuminated with the UV light ( = 365 nm) for 15 min to release the UV tape from the sample.

Figure 1 .
Figure 1.a) A schematic of pulsed laser annealing process for the formation of nickel silicide.b) Nickel reflectance at different laser wavelengths.c) Rs of nickel silicide under different laser conditions.(Rs = 300 Ω/□ w/o silicide) d) XRD results of nickel silicide using the ULA process.

Figure 2 .
Figure 2. a) XPS depth profiles after the PLA process.b) The binding energy of Ni 2p 2/3 after different PLA processes.HRTEM images of Ni-silicide after c) ULA, d)GLA, and e) ILA processes.

Figure
Figure2dshows the polycrystalline structure of the nickel silicide formed by the GLA process with a thickness of 16 nm.Thinner than that of the NiSi film formed by the ULA process.The SAED results in Figure2eshow that an amorphous nickel silicide film was formed with the thickness of the film being 15 nm after the ILA process.The TEM/EDS line scan profiles in FigureS1(Supporting Information)show the corresponding thickness of the film and atomic concentrations of Ni and Si for each laser process.The atomic concentrations of Ni and Si in the TEM/EDS line scan profile were in accordance with the atomic ratios of Ni and Si in Part II of the XPS depth profiles.To study the impact of the NiSi layer on device performance, we integrated the laser-annealed NiSi layer into the S/D contact of a p-channel MOSFET (PMOS) and a n-channel MOSFET (NMOS) devices.The corresponding electrical properties of the MOSFET with the nickel silicide contact formed by each laser illumination process were analyzed, with which a channel width (W) of 4 μm and a channel length (L) of 4 μm for the device were fixed in the I-V measurements.Figure3ashows the transfer characteristics of the PMOS on a linear scale under different laserannealing conditions.The results demonstrated that the drain current (I D ) of devices after integrating NiSi grown with different laser sources and powers were higher than those without an integrated source, demonstrating the benefit of NiSi integration for contact.The best parameter of the ULA process can be achieved at the laser power of 0.9 W, which performed the highest I D .The I D decreases as the laser power increases under the same laser source.The highest I D of the PMOS with the ULA process is ≈1.5 times larger than the highest I D with the GLA process integration, corresponding to the better crystallinity of (Supporting Information).The PMOS and NMOS devices used in the subsequent comparisons of electrical parameters and other applications were selected based on their best electrical performance by integrating the ULA-induced NiSi layer at the contact region of the S/D region.The output curves of the PMOS and NMOS with ULA-integrated NiSi are shown in FigureS3a,d, (Support-ing Information) respectively.Figure3b,e presents the comparison of field-effect mobility (μ) with varying channel lengths for the NiSi integration and without the NiSi integration of PMOS and NMOS devices.The field-effect mobility was calculated by the equation  = which L is the channel length; C g is the gate capacitance of HfO 2 gate dielectric; W is the channel width; and ( dI DS dV G

Figure 3 .
Figure 3. Electrical characteristics of PMOS.a) I-V characteristics under different laser processes.b) Field-effect mobility, and c) on/off ratio w/ and w/o ULA processes.Electrical characteristics of NMOS.d) I-V characteristics under different laser processes.e) Field-effect mobility, and f) on/off ratio w/ and w/o ULA processes.

Figure 4 .
Figure 4. a) V d -dependent characteristics of n/p-type Si-MOSFETs (W/L = 4/4 μm).b) R tot of Si-MOSFET versus channel length at V g of −2.8 V. Effect of Hot carrier stress.ΔV th -time curve for c) p-type TFTs and d) n-type TFTs w/ and w/o ULA processes.

Figure 5 .
Figure 5. a) VTC and b) voltage gain of flexible Si-CMOS inverter w/ and w/o ULA processes.VTC of flexible 6T-SRAM c) w/o ULA and d) w/ ULA processes.

Figure 6 .
Figure 6.a) A schematic of flexible device bending reliability test after the mechanical lift-off processes.Electrical characteristics under the bending test.b) I-V characteristics of NMOS and c)PMOS after 10 000 bending cycles.d) CMOS-inverter voltage gain and e) SNM values of 6T-SRAM before and after bending tests.