Fabrication of Large‐Area Organic Thin Film Transistor Array with Highly Uniform Water‐Borne Polyimide Gate Dielectric via Green Solvent‐Engineered Bar‐Coating Process

Here, the utilization of a highly uniform water‐borne polyimide (W‐PI) thin film as a gate dielectric layer for large‐scale organic thin film transistors (OTFTs) exceeding 100 cm2 is presented, employing the bar‐coating technique. The W‐PI thin films are obtained uniformly over a large area by systematically manipulating the surface tension of the water‐soluble poly(amic acid) salts (W‐PAAS) solution using alcohol as a co‐solvent in a “Green” process. The thickness of the W‐PI thin film is precisely controlled within the range of tens to hundreds of nanometers by adjusting key parameters, including the concentration of the W‐PAAS solution, wire diameter, and bar‐coating speed. As a result, 500 pentacene‐based OTFTs are successfully fabricated on a 10 × 10 cm2 substrate, utilizing a 280 nm thick W‐PI gate dielectric film. These devices exhibit excellent uniformity, with field‐effect mobility of 0.20 ± 0.02 cm2 V−1 s−1. Furthermore, the fabrication of electronic devices using an environmental‐friendly bar‐coating method on large‐area flexible substrates is demonstrated. This study highlights the considerable potential of eco‐friendly W‐PI thin films as dielectric materials, offering advantages such as cost‐effectiveness and high efficiency for reliable industrial applications.


Introduction
3][4][5][6][7][8][9][10] The OTFTs have been widely applied to chemical sensors, [11][12] flexible circuits, [13] and artificial skin [14,15] due to their promising properties such as high mechanical flexibility and ultra-light weight.For practical applications of OTFTs, a high throughput and large-area solution process is required.18][19][20][21] Although there has been extensive research on the fabrication of OTFTs, most of the focus has been on coating the organic semiconductor layer.Some studies have investigated achieving uniform coating over a large area, self-patterning, or controlling the crystal structure of organic semiconductors in active channels for OTFT.For example, Khim et al. demonstrated  OTFTs array and complementary IC fabrication using a wirebar-coating process. [16]Giri et al. achieved lattice-aligned crystals and high-speed production through lateral confinement of TIPSpentacene crystal growth during solution shearing. [17]Wang et.al. fabricated aligned PDPPT3-HDO films by bar-coating of o-xylene solution and reported a high mobility reliability factor of 87%. [18]n the production of large-area OTFT arrays, while organic semiconductors are patterned in a localized area, organic gate dielectrics are generally coated on the entire substrate, making it critical to establish a large-area uniform coating technology.[24][25][26] It is particularly important to ensure the even application of organic gate dielectric films with a thickness of 300 nm or less, as the coating thickness significantly impacts the electrical characteristics of the devices, such as driving voltage, I on /I off ratio, and leakage current.Therefore, the development of a large-area uniform coating technology for organic gate dielectrics is also essential to enhance the performance of these devices.][29] Although numerous studies have been published on the development of large-area solution-based deposition techniques for these polymers, they have inherent physical limitations in their properties compared to the widely used SiO 2 dielectric layer.
[32][33] However, most of the aromatic PIs are challenging to apply for insulating materials of flexible devices due to their high curing temperature for full imidization above 350 °C.In addition, specific polar solvents such as 1-Methyl-2-pyrrolidinone (NMP), Dimethylacetamide (DMAc), and Dimethylformamide (DMF) are required to prepare the PIs, which are very toxic and harmful to health.[36] In particular, W-PAAS exhibited enhanced hydrolytic stability and homogeneous thin film formation without pinholes under ambient air by forming an ammonium salt with the carboxylate groups of PAA.As a result, it was possible to significantly improve the yield of the fabricated device by over 98%.It means that most of the disadvantages of aromatic PI materials as a gate dielectric have been resolved and they can be applied to large-area processes.
Here, we report a large-area preparation for aromatic waterborne PI (W-PI) gate dielectric thin-film with an overall uniform thickness using a W-PAAS solution via a simple bar-coating method combined with green solvent engineering.To produce a large-area uniform thin film based on the optimized conditions, the morphology and thickness of the W-PI thin film were investigated according to the concentration of the solution, the barcoating speed, and the wire diameter.W-PAAS withstands temperature, humidity, and atmospheric changes and is uniformly coated on the substrate through a simple bar-coating process.In addition, a systematic investigation was carried out to optimize the surface morphology and dielectric properties of W-PI thin films according to multi-step thermal annealing temperatures.It was possible to fabricate a 280 nm thick, 10 cm × 10 cm large-area uniform W-PI gate dielectric layer with hydrolytic and electrical stability at a relatively low processing temperature of 250 °C.As a result, an array of 500 pentacene-based OTFTs was obtained and showed excellent device uniformity with mobility of 0.20 ± 0.02 cm 2 V −1 s −1 .Furthermore, a large-area OTFT array showing uniform device performance was successfully fabricated on the flexible substrate.

Large-Area W-PI Thin-films via Green Solvent-Engineered Bar-Coating Process
To manufacture a large-area device, a uniform, and thin W-PI gate dielectric film measured less than 300 nm was produced using W-PAAS aqueous solution via bar-coating on the 100 cm 2 glass substrate, as presented in Figure 1a.The barcoating method is a cost-effective and widely used technique for producing films over large areas.[36] The resulting W-PAAS was characterized using 1 H nuclear magnetic resonance ( 1 H NMR) and size exclusion chromatography (SEC), as shown in Figure S1 (Supporting Information).However, the use of aqueous solutions in large-area coating processes poses challenges due to the high surface tension of water.To overcome this issue, the incorporation of diverse alcohols as co-solvents, possessing low surface tension and exhibiting compatibility with water, into the W-PAAS aqueous coating solution has been explored.The selection of an appropriate alcohol, as a co-solvent, necessitates considering its ability to exhibit both low surface tension and a suitable evaporation rate throughout the coating process.The surface tension, vapor pressure, and boiling point characteristics of the different alcohols used are summarized in Table S1 (Supporting Information).
To enhance the coating properties while maintaining a highwater content, a fixed amount of alcohol was added to the primary solvent, water, not exceeding 5 wt%.The evaluation revealed that, at concentrations below 3 wt%, most alcohols did not significantly affect surface tension reduction or coating properties.However, exceeding 10 wt% of alcohol resulted in a low solution viscosity and uncontrollable film thickness.This occurrence can be attributed to the reduction of surface tension as the proportion of alcohol in the W-PAAS coating solution decreases.Figure 1b shows that the utilization of alcohols as co-solvents improved the coating properties of the W-PI thin film.The use of methanol and ethanol with high vapor pressures resulted in nonuniform films and rapid alcohol evaporation.Conversely, the use of alcohols with lower vapor pressures and higher boiling points than water, such as 1-propanol and 2-methoxy ethanol, led to a slow drying rate and uneven films.Fortunately, the use of isopropyl alcohol (IPA) as a co-solvent at a 5 wt% concentration resulted in a uniform film, as displayed in Figure 1b (bottom right image).IPA possesses a boiling point and polarity comparable to water, and its addition resulted in a decrease in surface tension from 66.97 to 44.93 mN m −1 , as determined through contact angle experiments.Consequently, subsequent experiments included 5 wt% of IPA as a co-solvent to ensure a uniform W-PI thin film over a large-area.
Optimizing the bar-coating process conditions is crucial for obtaining high-quality, large-area films with thicknesses below 300 nm to serve as a gate dielectric for OTFTs.In this study, the process conditions were optimized by controlling the wire diameter, solution concentration, and coating speed and carefully analyzing the morphology and thickness of the films.Figure 1c shows the impact of the W-PAAS solution concentration and wire diameter on the thickness of the resulting films.The coating solution used was a W-PAAS aqueous solution (water: 95 wt%, IPA: 5 wt%) with a solid content of 3-5 wt%, and the coating speed was fixed at 2 mm s −1 to minimize the shearing force effect.The concentration of the solution had a significant effect on the coating thickness, with an increase in concentration from 3 to 5 wt% resulting in a two-to fivefold increase in coating thickness.Moreover, an increase in wire diameter led to an increase in coating thickness, and the thickness variation with respect to solution concentration became more pronounced as the wire diameter increased.Thus, a uniform film thickness of around 300 nm, regardless of solution concentration, was obtained using a wire bar with a diameter of 90 μm.Further investigations were conducted to determine the impact of the W-PAAS solution concentration on the morphology of large-area PI thin films under varying barcoating speeds ranging from 2 to 15 mm s −1 .Wire bars with diameters of 50 and 90 μm were employed for bar-coating, and the results of film morphology under more detailed experimental conditions are presented in Figures S2 and S3 (Supporting Information).Even thinner film thicknesses could be achieved using a wire bar with a diameter of 50 μm, as shown in Figure S4 (Supporting Information).
Through careful consideration of various factors such as solution concentration, wire diameter, and coating speed, we were able to establish process conditions that resulted in uniform films over a large area.The thickness and morphology of the coating films under various process variables using a 90 μm wire bar are shown in Figure 1d.The coating film states were classified into uniform (○), non-uniform (△), and stripe (□) based on three criteria, and we identified the process conditions for forming a uniform film with a desired thickness of under 300 nm for use as a gate insulator in the green-shaded region in Figure 1d.By conducting experiments, we determined that the optimal process conditions for producing the most stable film on a large area involved using a 90 μm wire diameter, a 4.8 wt% W-PAAS solution concentration, and a 2 mm s −1 coating speed, as indicated by red stars in Figure 1d.The 280 nm thick-thin film coated under optimal conditions was employed as a gate insulator for OTFTs, and this will be discussed in detail in subsequent sections.

Large-Area Coating of W-PAAS Thin Films as Thermal Annealing Temperature
The degree of imidization has been known to significantly affect the electrical and mechanical properties of thermally (or chemically) converted aromatic PI materials from PAA precursors. [37,38]n this study, we carefully investigated the degree of imidization of our BPDA-pPDA-based W-PI thin film by setting four annealing temperatures from 50 to 350 °C and examining their electrical and structural properties during thermal imidization.First, the insulation properties of electronic components were evaluated using metal-insulator-metal (MIM) capacitors fabricated with W-PI thin films annealed at different temperatures.The dielectric constant and dielectric loss were measured, as shown in Figure 2a.The dielectric constant of the sample annealed at 50 °C without imidization was 8.38 (at 1 kHz), and the dielectric loss was high due to the presence of polar groups such as ─COOH and ─CONH.The dielectric constant of the 150 °C sample was slightly higher due to partial imidization, while the dielectric properties of the W-PI films annealed at 250 and 350 °C were almost equivalent and showed a typical dielectric constant of 3.2 for BPDA-pPDA-based PIs.The strength of the dielectric was tested for varying electric fields (E field ) by measuring the leakage current (I leak ) in the MIM capacitor.As illustrated in Figure 2b, an increase in annealing temperature led to a gradual reduction in the leakage current at 2 MV cm −1 .Insufficient imidization at 50 °C resulted in the persistence of numerous polar groups such as ─COOH, leading to a high leakage current value.However, after thermal treatment at 150 °C, the insulation properties were significantly enhanced, and above 250 °C, excellent insulation characteristics were observed, with a leakage current of less than 10 −7 A cm −2 .Our findings demonstrate that W-PAAS thin films can be completely converted to W-PI thin films by thermal treatment at 250 °C using 1,2-Dimethylimidazole (DMIZ) organic catalyst assistance. [34]These results were further confirmed through typical Fourier transform infrared (FT-IR) analysis to determine the degree of imidization (Figure S5, Supporting Information) and characterization for surface properties, including surface en-ergy and morphology of W-PI with different thermal annealing conditions (Table S2 and Figure S6, Supporting Information).
In order to be considered suitable for use in practical electronic devices, the insulators must possess the capability of being uniformly coated on substrates with non-uniform 3D structures, such as electrode patterns.Figure 2c presents the optical micrographs of the ITO-patterned glass substrate before and after coating with a W-PI dielectric film with a thickness of 280 nm annealed at 250 °C.After coating with a W-PI dielectric film, the refractive index was observed to change, leading to an alteration in the interference color and a uniformly bright purple color over a wide coated area with 280 nm of W-PI thin film.Additionally, the surface profile of the patterned ITO electrode area, indicated by a blue dotted line in the bottom image of Figure 2c, was found to be conformally coated with the same thickness along the Table 1.Dielectric constant and leakage current of W-PI via MIM device and electrical characteristics of pentacene-based OTFTs according to annealing temperature.

Annealing temperature [°C] Thickness [nm]
Areal capacitance [nF cm −2 ] at 1 kHz unevenness of the 240 nm thick ITO electrodes with a sharp edge, as demonstrated in Figure 2d.These observations provide evidence that the W-PI thin film was conformally coated on both the patterned ITO gate and glass substrate.
To investigate the effect of thermal annealing temperature on the fabrication of stable large-area W-PI gate dielectrics, device characteristics were measured using pentacene-based OTFTs with a BGTC (Bottom Gate/Top Contact) structure, as shown in Figure 2e.The AFM image of the pentacene crystal is shown in Figure S7 (Supporting Information).The sample heated at 50°C, has high polarity because the imide does not proceed, but the strong polar group (─COOH/─CONH) provides a repulsive force between PAA and pentacene, causing the pentacene to align vertically and grow.At 150 °C, imidization is not completely progressed, the pentacene is vertically oriented due to the polarity of the surface and has a large crystal size.However, at 250-350 °C, there is no polar group on the surface because complete imidization has progressed, so it has relatively small crystals of similar size to each other.The W-PI thin film, which was thermally treated at 50 °C, exhibited no device characteristics and was unsuitable as a gate dielectric.However, the W-PI thin films that were heat-treated at temperatures between 150 and 350 °C displayed stable insulation performance and device characteristics at low operating voltage.The W-PI thin film processed at 150 °C showed high mobility but shifted the turn-on voltage in the transfer curve.In the output graph of Figure S8 (Supporting Information), the saturation region is reached faster for films annealed above 250 °C.Notably, the thin film exhibited the best output value, mobility, and I on /I off ratio when processed at 250 °C.To examine the impact of surface charge trapping and polarization, bias stress was evaluated over time at constant V GS and drainsource voltage V DS , as shown in Figure S9 (Supporting Information).The results showed that at 150 °C, bias stress increased rapidly due to polarity and increased with time.It implied that the field effect mobility of a device with a partially imidized gate dielectric may be overestimated.Such polarization behavior can contribute to excessive current in the channel under bias stress.However, at 250 and 350 °C, there was no polarity, and charge trapping occurred at the interface, resulting in a gradual decrease in bias stress over time.The detailed electrical parameters of all the MIMs and OTFTs are summarized in Table 1.
As a result, we obtained a sufficiently electrically stable W-PI insulating layer 280 nm thick through thermal annealing at 250 °C, which was selected as the optimal condition for the large-area gate dielectric of the OTFT in subsequent studies.

Electrical Properties of Large-Area Device Arrays
The feasibility of producing large-area devices with consistent performance was investigated by assessing the characteristics of 256 MIM capacitors.The capacitors were fabricated on a 10 × 10 cm 2 ITO-patterned glass substrate, as depicted in Figure 3a.To ensure the comparability of the dielectric properties across all regions, the substrate was divided into 16 areas, and three MIM capacitors were randomly selected for characterization from each region.Figure 3b presents the average dielectric properties of the W-PI dielectric film obtained from 48 randomly chosen MIM capacitors in each region.Both the dielectric constant and dielectric loss values were similar in all capacitors, suggesting that the W-PI dielectric film can provide uniform coating properties regardless of the start-end points and the left-right points of the bar coating.
Moreover, the consistency of the electrical properties of 500 devices was examined by fabricating a large-area OTFT array consisting of 20 devices per 2 cm × 2 cm unit, as depicted in Figure 3c.When 100 devices out of 500 OTFT devices fabricated simultaneously were assessed, a transfer curve with a uniform profile was observed.And all the manufactured devices were verified to have a low gate current of 10 −9 A or less and exhibited stable operation, as shown by the blue and red lines in Figure 3d.
The electrical properties were characterized across a wide area, resulting in an I on /I off ratio of 2.67 (±0.20) × 10 4 and mobility of 0.20 ± 0.02 cm 2 V −1 s −1 .The remarkable achievement of uniform performance across all devices in terms of I on /I off ratio, mobility, and insulating properties is attributed to the consistent quality of the W-PI gate dielectric coating on the substrate.Moreover, the device fabrication yield was nearly 100%, consistent with previous reports of pinhole-free W-PI dielectric films. [34]igure 3e shows the spatial and statistical distribution of the mobility values for the large-area arrays produced on glass substrates.In our experiments, the yield was determined for the measured device when the I on /I off ratio was less than 10 2 or an undetectable turn-on voltage was defined as an inactive device.The average mobility values for each region are evenly distributed, as indicated by the uniform coloration of the map.The mobility measurements show no directional bias within the range of 0.15 and 0.23 cm 2 V −1 s −1 , irrespective of the coating direction.Significantly, no clustering of the mobility distribution is observed in specific regions, such as the substrate edges or center.These findings demonstrate that the optimized bar-coating process consistently produces a W-PI dielectric film across the large-area array.The ability to achieve an environmentally friendly, large-area process with low standard deviation and near 100% device yield holds great potential for practical applications in various fields.
Optimizing the dielectric coating conditions allowed for the bar-coating of W-PI thin film onto flexible substrates.In this study, a colorless PI flexible substrate was utilized, and the successful manufacturing of pentacene-based OTFTs was demonstrated, as depicted in Figure 3f.The devices exhibited stable structures without any signs of cracking or warping.Furthermore, stable and uniform transfer curves were obtained for all regions of the flexible OTFT devices, as illustrated in Figure 3f (inset).The measured mobility is 0.23 ± 0.06 cm 2 V −1 s −1 , and the I on /I off value is 1.27 (±0.36) × 10 4 (Table 1).The average mobility of the devices fabricated on the flexible substrate was comparable to that of the large-area devices produced on glass substrates, with yields approaching 100%.These results demonstrate the significant potential of large-area flexible electronic circuit production and suggest the early realization of W-PI dielectric materials as an eco-friendly process platform.

Conclusion
In conclusion, this study presents an environmentally-friendly approach for the production of large-area W-PI thin films uti-lizing a bar-coating technique with water-based PI precursors, specifically W-PAAS.We manipulated the surface tension of the W-PAAS solution through co-solvent engineering with alcohol, particularly IPA, to create a large-area gate dielectric coating.By optimizing the solution concentration, wire diameter, and coating speed, we could easily control the thickness of the W-PI thin film.Additionally, we systematically examined the degree of imidization and insulation properties through a thermal treatment process, resulting in a low-temperature process of 250 °C and excellent insulation properties.The W-PI thin films demonstrated highly uniform and stable insulation properties when coated over a large area using this coating method.Furthermore, we successfully produced 500 pentacene-based OTFTs with a 280 nm thick W-PI gate dielectric film on 100 cm 2 rigid and flexible substrates, utilizing a bar-coating method.The devices exhibited excellent uniformity, with mobility of 0.20 ± 0.02 cm 2 V −1 s −1 .Our eco-friendly and energy-efficient approach using W-PI dielectric has the potential to replace current toxic organic-based processes and can be readily adapted to flexible electronics.
Bar-Coating: To produce a large-area OTFT array, a bar-coating method was employed to coat a 4.8 wt% W-PAAS solution on a 10 cm × 10 cm ITO-patterned glass substrate using a wire-wound rod obtained from Kipae E&T Co.In order to improve the coating properties, 5 wt% IPA was added to the solution to lower the surface tension of water without affecting the surface properties of the film.Prior to the bar-coating process, the substrate was pre-treated with UV-O 3 for 3 min.After deposition of 0.5 mL of the W-PAAS solution, the substrate was coated at a speed of 2 mm s −1 using a bar wound with a 90 μm wire.Heat treatment was carried out at 250 °C.The samples were then subjected to an annealing treatment at five temperature conditions ranging from 50 to 350 °C, with the temperature of each sample increased in 30 min intervals and the total heat treatment time set at 2 h.
Device Fabrication: A simple MIM capacitor was fabricated to measure capacitance.Thermal evaporation with a shadow mask was used to deposit aluminum as the bottom and top electrodes.A 300 nm thick W-PI film was then coated between the two parallel electrodes.The MIM capacitor had an area of 1 mm × 1 mm.For the bottom-gate/top-contact (BGTC) configuration of the OTFT, a 10 cm × 10 cm glass substrate was used for device experiments according to the annealing temperature, and aluminum was used as the gate electrode.A 30 nm thick layer of aluminum was deposited using thermal evaporation.For large-area device fabrication experiments, a 10 cm × 10 cm glass substrate was used, and a 240 nm thick ITO electrode patterned with a photoresist was used for the gate electrode.The coating and heat treatment of the W-PI film were the same as for the gate dielectric coating process.A 40 nm thick pentacene layer was then thermally evaporated on the W-PI thin films under vacuum conditions to serve as the semiconductor layer.Finally, a 40 nm thick gold contact electrode was deposited using thermal evaporation through a shadow mask with a channel width of 1000 μm and length of 50 μm.All evaporation processes were carried out at an evaporation rate of 0.5 Å s −1 under high vacuum conditions of 3 × 10 −6 Torr.
Characterization: The 1 H-NMR spectra of W-PAAS were obtained using a Bruker Avance III HD 500 MHz spectrometer operating at 500 MHz with DMSO-d 6 solvent.Gel Permeation Chromatography analysis was performed on a Futecs model in N-Methyl-2-pyrrolidone (NMP) with 0.02 m of H 3 PO 4 and 0.02 m of LiBr at 50 °C with a flow rate of 0.8 mL min −1 on a Shodex (Showa Denko, Minato, Japan).The instrument was equipped with three poly(hydroxy methacrylate) columns (multi-pore) with molar masses in the range of 200-2 00 00 000 g mol −1 .FT-IR spectra were recorded using an ALPHA-P spectrophotometer (Bruker) to monitor the progress of thermal imidization of PAA in the wavenumber range from 4000 to 600 cm −1 .The surface morphology of W-PI thin films was investigated using an optical microscope (Nikon 50-POL).Thickness measurement was conducted using an alpha-step surface profiler (Kla-Tencor step DC50).The surface morphologies of W-PI thin films and pentacene layers at the nanoscale were observed using an atomic force microscope (Bruker Mulimode-8) in tapping mode.Surface energy was characterized by measuring the contact angles of deionized water and diiodomethane on the films using a contact angle analyzer (SEO Phoenix 450).The electrical characteristics of the transistors were measured using a Keithley 4200A-SCS semiconductor parameter analyzer.Experimental mobility (μ) was extracted from the saturation region of the I d 1/2 versus V g plot using the equation 2 where C i is the capacitance per unit area, and W and L are the channel width and length, respectively.The experimental threshold voltage (V th ) was extracted by extrapolating to I DS = 0 in the identical plot.The capacitance and dissipation factor of the MIM capaci-tors were measured using an Agilent E4980A precision LCR meter within a frequency ranging from 20 Hz to 2 MHz.All electrical performances were measured in ambient conditions.

Figure 1 .
Figure 1.a) Molecular structure and schematic diagram of the bar-coating process using eco-friendly W-PAAS solution for preparing a large-area uniform W-PI film.b) Visual representation of the impact of adding various alcohol co-solvents.The content of the alcohol solvents used was maintained constant at 5 wt% regardless of the type.All black scales represent 2 cm.c) The thickness of the W-PI thin film depending on the concentration of the solution and wire diameter during the bar-coating process at a speed of 2 mm s −1 .d) Variation in thickness and surface morphology of the W-PI thin film as a function of the concentration of the coating solution and bar-coating speed using a 90 μm wire-wound bar: uniform (○), non-uniform (△), and stripe (□).The coating solution used was a W-PAAS aqueous solution (water: 95 wt%, IPA: 5 wt%) in (c) and (d).

Figure 2 .
Figure 2. a) The variation in dielectric constant and dielectric loss was measured between 20 Hz and 2 MHz.b) The leakage current was measured as a function of thermal annealing temperature (ranging from 50 to 350 °C) at electric fields ranging from 0 to 3 MV cm −1 .c) OM images of ITO-patterned glass substrate before and after coating of W-PI thin film.The black scale bars represent 500 μm.d) Surface profile indicated by blue dotted line in the bottom OM image of (c).e) Transfer curve of pentacene-based OTFTs with W-PAAS gate dielectrics on an ITO-patterned glass substrate annealed at different temperatures and fabricated OTFTs with BGTC structure (inset).

Figure 3 .
Figure 3. a) Optical image of 256 MIM capacitors with a 280 nm thick W-PI gate dielectric on a 10 × 10 cm 2 glass substrate and b) average dielectric performance of 48 MIM capacitors.c) Optical image of 500 OTFTs with W-PI gate dielectric on a 10 × 10 cm 2 ITO-patterned glass substrate and an enlarged image of 20 devices in a 2 × 2 cm 2 area.d) Overlapped transfer curve of 100 OTFTs.e) Mobility distribution chart of 100 OTFTs fabricated through the bar-coating process.f) Optical image of 500 OTFTs with W-PI gate dielectric on a 10 × 10 cm 2 flexible colorless PI substrate and an overlapped transfer curve of 100 OTFTs (inset).