Inkjet‐Printed, Wafer‐Scale Organic Schottky‐Gate Transistors toward Single‐Battery‐Driven Integrated Logic

Organic field‐effect transistors switched by insulated gates are the most essential building blocks, while usually plagued with degraded gate control arising from complicated dielectric engineering. Subsequently, the resulting large supply voltage and power consumption remain an essential issue for portable electronics driven by a single battery of only 1.5 V. Herein, wafer‐scale organic Schottky‐gate transistor arrays using inkjet‐printed few‐layer organic semiconducting crystals are reported. The transistors exhibit steep switching characteristics with an average subthreshold swing of 55 mV per dec and high signal amplification efficiency over 45 S A‐1, attributed to efficient Schottky gating and enhanced charge injection. Thereafter, high‐gain inverters are successfully demonstrated with an ultralow power consumption of only 800 pW; also, they are integrated as 1 V driven sequential logic circuits. A coplanar double‐gate geometry is also introduced for low‐voltage, single‐device AND logic. Therefore, the work opens new avenues toward the sustainable advancement in single‐battery‐driven, ultralow‐power organic electronics.


Introduction
Tremendous progress has been witnessed in organic electronics to advance numerous electronic and optoelectronic devices, thus greatly promoting the development of the modern information DOI: 10.1002/aelm.202300395era. [1,2][5] Nevertheless, such switching behaviors are usually plagued with degraded gate control due to inevitably necessary voltage distribution at dielectric layers and charge traps at the semiconductor/dielectric interfaces. [6,7][14] Especially, when utilizing ultrathin film as the channel with excellent electrical modulation, such transistors can allow for a subthreshold operation with steep switching characteristics in low-voltage regions, which possesses great potential in achieving ultralow-power devices. [15]Very recently, ultrathin organic crystals constructed within several molecular layers have attracted growing interest, and they should be ideal channel materials for realizing subthreshold organic SGTs (OSGTs). [16,17][20] Therefore, the achievement of solution-processed OSGT arrays with ideal switching characteristics can provide new opportunities toward single-battery-driven organic electronics with ultralow power consumption but has not yet been experimentally demonstrated.
Herein, we show the first demonstration of OSGT arrays utilizing inkjet-printed ultrathin organic crystalline semiconductors (OCSs).Our transistors break the Boltzmann limit with a minimum subthreshold swing (SS) of 50.7 mV per dec, an ultralow average SS of 55 mV per dec over one decade of current, and a greatly enhanced signal amplification efficiency up to 45 S/A under 1 V operation.Such extraordinary performances are attributed to efficient Schottky gating due to the dielectricfree nature of our OSGTs.Also, enhanced charge injection can optimize subthreshold characteristics.These advances promise an excellent subthreshold operation with an extremely high output resistance of ≈10 11 Ω and transistor intrinsic gain over 10 4 .We also show that these device arrays scalable to wafer scale exhibit excellent uniformity and high yield in the transistor metrics.Thereafter, we successfully integrate our transistors as ultralow-power inverters (≈800 pW) and 1 V driven sequential logic circuits (flip-flop static random-access memory cells and seven-stage ring oscillators).Besides, our OSGT with a coplanar double-gate architecture can realize low-voltage, single-device AND logic.Therefore, our OSGTs with superior subthreshold operations unambiguously constitute a significant step towards ultralow-power applications of single-battery-driven organic electronics.

Device Design and Fabrication
In the conventional metal-oxide-semiconductor field-effect transistor (MOSFET) architecture, an applied gate voltage (V gs ) will cause a change in the surface potential (Δ s ) and a reduction of the energy barrier (qΔ s ) in the channel (upper panel of Figure 1a). [7]Note that the channel energy barrier drop qΔ s = qΔV gs /(1 + C s C ox −1 ) (C ox is the gate-to-channel capacitance and C s is the source-to-channel capacitance) is generally less than qΔV gs since the total capacitance of gate insulators is usually positive (Figure S1a, Supporting Information). [21]We consider utilizing a dielectric-free Schottky junction with much larger capacitance to replace the insulators of the MOSFETs at the gate terminal, also defined as Schottky-gate transistors (SGTs) (lower panel of Figure 1a). [15]Concerning device physics, without voltage distribution at dielectric layers as that in conventional MOSFETs, any variation in the gate potential will completely act on the channel with an ideal energy barrier drop, i.e., qΔ s ≈ qΔV gs (Figure S1b, Supporting Information).Hence, such transistors with simplified structures can show much more sufficient gate control than MOSFETs.
To this end, we built bottom-contact organic SGT (OSGT) arrays across 2-inch highly doped Si/SiO 2 wafers (Figure 1c, see Experimental section).Gate and drain (source) electrodes with high-precision pattern design and alignment are prepared by photolithography and evaporation (Steps 2 and 3 in Figure 1b).Then, organic semiconductor blends consisting of p-type organic semiconductor dioctylbenzothienobenzothiophene (C 8 -BTBT, 0.5 wt%) and poly (methyl methacrylate) (PMMA, 0.1 wt%) are directly printed onto the electrode patterns at a printing speed of 100 μms −1 (Step 4 in Figure 1b).In the process, a doublelayer structure consisting of C 8 -BTBT and PMMA is formed via vertical phase separation (Figure S2c, Supporting Information).Note that unlike conventional inkjet printing, which drips discrete droplets from the nozzle onto the substrate under pressure, we utilized ultrasonic vibration-controlled dispensing combined with antisolvent crystallization methods, enabling liquid meniscus formation between the substrate and micropipette for the stable and continuous crystallization of organic semiconducting films (Figure S2a-c, Supporting Information). [18,22,23]Subsequently, we characterized the crystalline properties of the printing films via cross-polarized optical microscopy.As the substrate rotates horizontally, the colors of the films obviously change from bright to dark, indicating few grain boundaries within the printing films (the upper panel of Figure 1d). [24]Furthermore, the film morphology is determined by atomic force microscopy (AFM) analyses, showing that the thicknesses of C 8 -BTBT and PMMA are ≈8 nm (corresponding to a trilayer molecular structure) and ≈1 nm, respectively (the lower panel of Figure 1d and Figure S2d, Supporting Information). [25]Thus, combining inkjetprinting and microelectronic processing technologies provides an effective method for the wafer-scalable fabrication of OSGT arrays with ultrathin OCSs.

Electrical Performance of OSGTs
To explore the electrical characteristics of OSGTs, typical transfer curves at various drain-source voltages (V ds ) are presented in Figure 2a.Our devices operate in enhanced mode with a nearzero threshold voltage (V th ) of approximately −0.3 V.The on/off ratio of our devices can exceed 10 5 under V dd of −1 V; even when V ds drops to −10 mV and −1 mV, our devices still demonstrate field-effect characteristics (see Note S1, and Figure S3a Supporting Information).These 1 V driven operating characteristics are essential for low-power scenarios. [26,27]Additionally, the measured I gs of ≈10 −11 A in our devices, which is a value comparable to that of organic bottom-gated MOSFETs, is attributed to the low reverse current of the Schottky junction (Figure S4a, Supporting Information). [28]In addition, a nearly negligible hysteresis of 7 mV in our devices is observed, indicating a good interface quality free from charge traps (see Note S1 and Figure S3b,c, Supporting Information). [19]urthermore, we evaluated the switching characteristics of our devices and fitted the linear plot of Figure 2a and Figure S5 (Supporting Information) in the subthreshold region by the following formula (Figure S6, Supporting Information): [29] where μ 0 is the carrier mobility, k B is the Boltzmann constant,  is the channel dielectric constant, W d is the depletion width, and Z and L are the thickness and length of the channel, respectively.In particular, the parameter m, defined as , is the body factor of the transistors, representing the controllability of gate electrode to channel surface potential. [30]deally, when m is equal to 1, any variation in the gate potential will completely transfer to the channel surface (i.e., ∂V gs ≈ ∂ s ).Subsequently, we benchmarked the m values with OSGTs under different printing speeds, organic MOSFETs, and Si MOS-FETs, respectively, as shown in Figure 2b.Organic MOSFETs demonstrate a large m of 1.7, mainly due to the existence of gate insulators and trap states.In contrast, OSGTs with different printing speeds exhibit far superior performance.Particularly, devices with the printing speeds of 100 μm s −1 (the channels consist of trilayer C 8 -BTBT molecules) show an optimal m in the range of 1.03 to 1.07 at different drain voltages, even surpassing that of Si MOSFETs (m is in the range of 1.1 to 1.4). [7]uch a nearly ideal m value is mainly attributed to the dielectricfree OSGT structure (C s C ox −1 ≈ 0), indicating that our devices can realize efficient gate control for sharp on/off switching characteristics.
We further extracted SS from the transfer curves to quantify the subthreshold characteristics according to the equation of SS = ∂V gs /∂(log 10 I ds ) (Figure 2c). [30,31]For the three V ds (−0.01 V, −0.1 V, and −1 V), we obtained SS with minimum values of 56.2, 51.3, and 50.7 mV per dec, respectively, thus breaking the Boltzmann limit (60 mV per dec).According to the best of our knowledge, our devices possess the record-low values of SS for organic transistors (see Table S1, Supporting Information).And these values are superior to those in OSGTs under other printing speeds (i.e., 50 μm s -1 and 10 μm s -1 ) and organic bottom-gated MOSFETs (Figures S4b and S7b,c, Supporting Information).In addition, SS is also equal to (1 + C s C ox −1 ) × ln(10) k B T/q = m × n, where the n value is the factor reflecting the charge conduction (ideally equal to 60 mV per dec at 300 K in the conventional MOSFETs). [30,31]Considering the m value and the SS as extracted above, the n values are estimated to be less than 60 mV per dec, indicating that there should be a tunneling behavior in the charge injection process at the source. [31,32]Moreover, based on the excellent subthreshold operation originated from the ultralow SS, the maximum transconductance efficiencies (g m /I ds ) of 43.1, 45.3, and 43.5 S A -1 at V ds = −0.01V, −0.1 V, and −1 V are extracted in the subthreshold region, respectively. [27]Similarly, all of these values exceed the Boltzmann limit of q/k B T = 38.7 S A -1 , reflecting the amplification capacities of our devices (Figure 2d). [27]Besides, we further explored the transfer characteristics of the OSGTs featuring with different channel widths.And with the decrease of the device widths, the electrical performances show an obviously downward trend, indicating the reduced charge injection at the source (Figure S8, Supporting Information). [7]he output characteristics of our devices are presented in Figure 2e.In the small V ds region, I ds is basically linear with V ds , implying Ohmic-like contact at the source. [33]Then, I ds quickly saturates as V ds further increases.This characteristic is explained as follows: under a certain gate voltage that turns the channel on, the drain voltage enables the asymmetric depletion region in the channel, and the ultrathin channel in our devices is easily pinched off at the drain terminal (see Note S2 and Figure S9, Supporting Information).The channel current thus continues saturating as the drain voltage increases, similar to a MOSFET.Furthermore, we plotted the output resistance (r o = ∂I ds /∂V ds ) and transconductance (g m = ∂I ds /∂V gs ) with different gate voltages in Figure 2f. [27]The output resistance and transconductance exhibit extremely high values of ≈10 11 Ω and ≈10 -7 S, respectively.Subsequently, we extracted the intrinsic gain of OSGTs, determined by the expression A i = g m r o . [26]The highest A i of 1.1 × 10 4 is obtained, which is much larger than that of Si MOSFETs (Figure 2f). [27]ur devices also exhibit excellent operational stability and yield.We first performed cycle stability measurements of OS-GTs under V ds = −1 V, showing little degradation in the device performance after 100 cycles (Figure S10a, Supporting Information).Additionally, an electrical stress of V dd = −1 V is applied to the transistors, exhibiting excellent stability under repeated gate voltage pulses with frequencies of 1 Hz (Figure S10b, Supporting Information).We further evaluated device variations by measuring 100 OSGTs at V ds = −1 V, which were selected from different regions on the 2 in.Si/SiO 2 wafer (Figure S11a, Supporting Information).The best values of SS (over one decade of I ds ), V th , on/off ratio, g m , and g m /I ds (over one decade of I ds ) are 55 mV dec -1 , −0.17 V, 5.7 × 10 5 , 10 7 S, and 45 S A -1 , respectively (Figure 2g,h and Figure S11b-f, Supporting Information).Then, the histograms of SS (over one decade of I ds ), V th , on/off ratio, g m , and g m /I ds (over one decade of I ds ) show Gaussian-like distributions with very small deviations of 4%, 0.03%, 0.14%, 0.27%, and 5.14%, respectively, indicating a very reliable performance uniformity of our inkjet-printed subthreshold OSGTs (Figure S11g, Supporting Information).

Contact Characteristics of OSGTs
The contacts at the source (drain) and gate terminals are another important aspect that affects the switching behaviors of OSGTs. [34]We first characterized the quality of the contacts at the source (drain).Notably, Au with a high work function of 5.0 eV is selected to contact the C 8 -BTBT layer (E F = 5.2 eV, HOMO = 5.6 eV) for effective charge injection. [35,36]Subsequently, temperature-dependent electrical measurements are performed in a symmetric Au/PMMA/C 8 -BTBT/PMMA/Au planar device structure with different PMMA concentrations, i.e., without PMMA, 0.05 wt% PMMA, and 0.1 wt% PMMA (Figure S12a-c, Supporting Information).Obviously, a Schottky-like contact appears within the entire temperature in the devices without PMMA When the PMMA concentration gradually increases to 0.1 wt%, the measured I-V curves show a transition to linear characteristics.Then, we extracted the Schottky barrier (Φ SB ) values of the three devices (see Note S3 and Figure S12d-f, Supporting Information).A good linear relationship between the extracted Schottky barrier Φ SB and the applied bias is observed; the Φ SB,0 at zero bias is easily extrapolated (Figure 3a).As depicted, Φ SB exhibits a downward trend from 183 mV to 84 mV as the PMMA concentration increases to 0.1 wt%, indicating the inserted PMMA layers for lowering the barrier. [37]On this basis, we further compared the transfer curves of OSGTs with different PMMA concentrations (Figure S13e, Supporting Information).In the devices without PMMA layers, the on/off ratio is only 10 with significant off-state currents of 10 −9 A due to the large Schottky barrier at the source (drain), thus weakening the device performance.And an extremely low off-state current of 10 −12 A in OS-GTs can be observed when the PMMA concentration increases to 0.1 wt%, indicating the efficient gate control (Note S4, Supporting Information).Consequently, the Au/PMMA (0.1 wt%)/C 8 -BTBT structure is regarded as the optimal choice for the quasi-Ohmic contact in our devices.
The charge injection behaviors at the source terminals are further revealed by plotting ln (I/V 2 ) versus 1/V curves under different temperatures (see Note S3, Supporting Information and Figure S12g, Supporting Information). [37]All contacts show logarithmic dependence, indicating that Fowler-Nordheim tunneling is absent due to the small barrier height. [38][39] Additionally, this behavior also contributes to the ultrasteep switching characteristics in OSGTs. [31]Therefore, these excellent results reveal that the ultrathin inserted interlayers (≈1 nm) between the metal/semiconductor interface formed by one-step inkjet-printed vertical phase separation significantly enhance the charge injection due to the lower barrier and quantum tunneling.
Contact resistance (R c ) also reflects the injection characteristics of organic transistors. [40][43] We performed transmission-line measurements to extract R c (Figure 3c).The measured I-V curves are linear at different channel lengths, and a R c of 390 Ω cm is extracted in our devices.Note that the R c obtained in our devices under coplanar architectures is competitive with most few-layer OCS-based MOSFETs; [19,25,40] this phenomenon is attributed to the enhancement of the charge injection.46] We further examined gate contacts by measuring the I-V curves, as shown in Figure 3d.We chose Ti as the gate electrode with a sufficiently low work function of 4.33 eV to achieve an effective Schottky contact at the gate. [47]Notably, our OSGT architecture can be regarded as two symmetric and back-to-back equivalent Schottky diodes in principle (Figure S13a, Supporting Information). [12]Subsequently, similar rectifying behaviors are observed in both diodes with an extremely low reverse current of ∼10 −11 A and a turn-on voltage of approximately -0.5 V. We also fitted the current curves by a Shockley diode equation: [35] where n is the ideality factor, V T = k B T/q is the thermal voltage, k B is the Boltzmann constant, q is the elementary charge, I 0 is the reverse bias current, R s is the series resistance, and W is the Lambert W function.An ideality factor n of 1.75 is achieved with a series resistance of 600 MΩ, reflecting that such excellent diode characteristics mainly arise from efficient carrier injection and high interface quality (Figure S15a, Supporting Information).Furthermore, the large Schottky barrier (Φ SB ) of 573 mV was further extracted from the temperature-dependent I-V curves (Figure S14, Supporting Information).Such behaviors confirm the excellent Schottky contacts for efficient gate control, thus yielding a sufficient channel depletion at the ultrathin organic semiconducting layer.We also examined the OSGTs with evaporated Al as the gate electrodes, which exhibited a much larger V th and SS (Figure S15, Supporting Information).Considering that the Ti and Al work functions are similar, [48] hence the observed differences in device performance are mainly due to the AlO x formed during the device fabrication (Note S5, Supporting Information). [49,50]

Logic Circuits Based on OSGTs
OFETs have been extensively pursued for large-area manufacturing and diversified applications. [2,25]In particular, the singlebattery-driven electronics are of significant interest for futureoriented portable devices, thus requiring low-voltage circuits with low power and high gain. [51,26]Taking advantages of superior gate-control capabilities and high-quality contacts, our devices with 1 V driven operation potentially enable battery-drivable and diversiform integrated logic.We designed inverter circuits consisting of a biased organic MOSFET (V bias = -1 V) and a subthreshold OSGT in a current-source loaded configuration (Figure 4a).Regarding the high intrinsic gain of OSGTs, the inverter circuits show steep voltage transfer characteristics with full swing output (Figure 4b).Simultaneously, we deduced a voltage gain (A v = ∂V out /∂V in , where V in and V out are the input and output voltages, respectively) of 145 V V -1 at the operation voltage of V dd = 1 V, showing the potential of our devices in amplifier circuit applications (Figure 4b). [52,53]In addition, the static power consumption, defined as P static = I dd × V dd , is calculated as low as approximately 800 pW, which is among the lowest values in various unipolar inverter technologies (Figure 4c). [52,54]uch high gain and ultralow power consumption are attributed to the unique advantages of subthreshold switching in our OS-GTs.Based on ultralow-power organic inverters, we integrated a pair of cross-coupled OSGT-based inverters to build a low-voltage flip-flop cell, which is the fundamental building blocks of static random-access memory (SRAM) (one of the sequential logic circuits) (Figure 4d,e). [55]When applying fixed input voltages in this flip-flop cell (V in = 0 V and 1 V at V dd = 1 V), two stable logic states (0.9 V and 0 V) were written into V out , respectively.As the input is opened (T = 20 s and 85 s), the output logic state of the flip-flop cell can still remain, thus indicating the stable memory function (Figure 4f). [56,57]Moreover, a seven-stage ring oscillator is fabricated to explore the dynamic performance of OSGTs-based inverters (Figure 4g). [57]The ring oscillators operate with a supply voltage V dd of 1 V and a gate delay () of 4 ms (Figure 4h).The transient responses of multistage cascaded inverters are exhibited in Figure S16 (Supporting Information), demonstrating circuit regenerative due to the high gain.This result reveals that the fabrication process of our devices possesses robustness and scalability for further integrated logic.More importantly, it is worth mentioning that biased MOSFETs are utilized in this work as the load transistors, changing to depletiontype or n-type OSGTs by appropriate material selection and device design could enable A v values and oscillation frequency (f OCS = 1/2n, where n is the number of stages) to improve by orders of magnitude. [43,57]inally, we introduced coplanar double-gate geometry to realize the AND logic function in a single transistor for circuit simplification (Figure 5a-c). [58]The additional gate has the same process flow as that of the single-gate OSGTs, which is more compact than conventional MOSFETs (Figure S17, Supporting Information).As shown in the inset of Figure 5d, we denoted the two gate voltages as G IN, 1 and G IN, 2 , respectively; the high voltage amplitudes (-1.5 V) represent "1," and the low voltage amplitudes (0 V) represent "0".Meanwhile, the channel output current is selected as the output signal, and the high (≥10 -10 A) and low output currents (≈10 -12 A) represent "1" and "0," respectively.If any gate gives a low input signal, the carriers in the channel are immediately depleted for a low output current due to the reverse-biased Schottky junction at the gate terminal; the corresponding graphical demonstration of the AND logic operation is shown in Figure 5a,e.Additionally, our devices demonstrate the single-device OR logic function under UV illumination (see Note S6 and Figure S18, Supporting Information).

Conclusion
We report the first OSGT arrays utilizing inkjet-printed ultrathin OCSs in a wafer scale, which exhibit a superior subthreshold operation with excellent electrical performances.In particular, an ultralow average SS of 55 mV per dec, a greatly enhanced transconductance efficiency up to 45 S A -1 , and an extremely high intrinsic gain over 10 4 are significantly achievable.These advances are attributed to efficient Schottky gating, also optimized by enhanced charge injection.Thereafter, ultralow-power inverters (≈800 pW) and 1 V driven sequential logic circuits are successfully demonstrated by integrating our subthreshold OSGTs.Besides, we realize low-voltage single-device AND logic by our OSGT with a coplanar double-gate architecture.Therefore, our inkjet-printed OSGTs can serve as a significant candidate for advanced organic electronics towards ultralow-power and single-battery-driven circuit applications.

Experimental Section
Fabrication of C 8 -BTBT/PMMA films: C 8 -BTBT (≥99%) and PMMA (≥80%) were purchased from Sigma-Aldrich and used without further purification.The precleaned 50 nm SiO 2 /Si substrates were cleaned in Characterizations of C 8 -BTBT/PMMA Films: For regular AFM, the characterizations were performed with an Asylum Research Cypher scanning probe microscope under ambient conditions.The cross-polarized optical reflection micrographs were obtained by a ScanPro spectro-microscope under white light.
Fabrication of OSGTs and Circuits: For the fabrication of OSGTs, 30 nm Ti electrodes were fabricated patterned on the SiO 2 /Si substrate as the gate electrodes by performing photolithography and electron-beam evaporation (EBE).Then, 1 nm Cr/29 nm Au source (drain) electrodes were deposited by alignment photolithography and EBE.Subsequently, the UVozone treatment (about 5 min) after the electrode preparation is necessary to provide a hydrophilic surface for the inkjet printing of the C 8 -BTBT films.Finally, the few-layer C 8 -BTBT/PMMA semiconducting films were aligned and printed onto the prepared electrodes by inkjet printing process.In the fabrication of OSGTs-based circuits, 50 nm SiO 2 /Si substrates are regarded as the backgate electrodes of biased MOSFETs, and the subsequent preparation processes are similar to that of OS-GTs.
Electrical and Optoelectrical Measurements of OSGTs and Circuits: All of the electrical measurements were carried out with a semiconductor parameter analyzer (Agilent B1500) in a closed-cycle cryogenic probe station under a vacuum condition of 10 −3 Torr.A 365 nm UV light-emitting diode (LED) driven by a signal generator was used as a light source to illuminate OSGTs from the top.The 365 nm UV LED light was calibrated by a UV-A meter (LS125, UVALED-X3 probe).

Figure 1 .
Figure 1.Fabrication of OSGTs and film characteristics.a) Schematic of MOSFETs and SGTs.b) Fabrication process flow of the OSGT arrays.c) The left panel is the photograph of OSGT arrays on a 2 in.wafer.The right panel is the optical micrograph of a 7 × 7 OSGT array and the scale bar is 600 μm.The inset is the single OSGT, and the scale bar is 100 μm.The length to width ratio (L/W) of the device channel is 10 μm/120 μm.d) Cross-polarized optical micrograph (upper panel) and AFM (lower panel) of inkjet-printed C 8 -BTBT/PMMA films.The scale bars are 80 μm and 5 μm, respectively.

Figure 2 .
Figure 2. Electrical characteristics of OSGTs.a) Transfer curves and gate leakage currents of the OSGTs at V ds = -0.01V, -0.1 V, and -1 V. b) Benchmark of the m values between OSGTs under different printing speeds, organic MOSFETs, and Si MOSFETs, respectively.c) Extracted SS at three V ds .The dashed line is the ideal SS limit of 60 mV per dec.d) Extracted g m /I ds at three V ds .The dashed line is the ideal g m /I ds limit of 38.7 S A -1 .e) Output curves of the OSGTs with V gs ranging from 0 to -1 V and the step is 50 mV.f) Experimental values for g m , r o , and A i of OSGTs as a function of V gs .g) Transfer characteristics of 100 OSGTs.h) Statistical bar graph of SS (over one decade of I ds ) (red bars) and g m /I ds (over one decade of I ds ) (blue bars) for OSGTs arrays.The dashed line is the ideal SS and g m /I ds limit of 60 mV per dec and 38.7 S A -1 , respectively.

Figure 3 .
Figure 3. Contact characteristics of OSGTs.a) Φ SB,0 values of OSGTs with different PMMA concentrations.The inset is the extracted Schottky barrier Φ SB as a function of V, and Φ SB,0 under zero bias obtained from a linear fit.b) ln(I/V 2 ) versus ln(1/V) curves for the Au/PMMA (0.1 wt%)/C 8 -BTBT contacts at different temperatures.The inset is the energy band diagram illustrating DT and TE dominating in the Au/PMMA (0.1 wt%)/C 8 -BTBT contacts.c) Transmission-line measurements to extract R c of the Au/PMMA (0.1 wt%)/C 8 -BTBT contact.The inset shows the output curves of different channel lengths.d) I-V curves of the back-to-back Schottky diodes in OSGTs.The inset is the energy band diagram of the source and gate with C 8 -BTBT layers (0.1 wt% PMMA) (the upper panel), and a schematic of the equivalent Schottky diode at the gate terminal in OSGTs (the lower panel).

Figure 4 .
Figure 4. Amplifier circuits and sequential logic circuits based on OSGTs.a) Equivalent circuit diagram (top) and optical microscope image (bottom) of a current-source loaded inverter.The scale bar is 75 μm.b) Voltage transfer characteristics and voltage gain (A v ) as a function of input voltage (V in ) under V dd = 1 V. c) Static power as a function of input voltage (V in ) under V dd = 1 d) Optical microscope of a flip-flop cell.The scale bar is 150 μm.e) Equivalent circuit diagram of a flip-flop cell.f) Output voltage of the flip-flop cell at V dd = 1 V. g) Equivalent circuit diagram (top) and optical microscope image (bottom) of a 7-stage ring oscillator.The scale bar is 400 μm.h) Measured output waveform of the ring oscillator operated at V dd = 1 V.

Figure 5 .
Figure 5. AND logic gate via a single OSGT with a double-gate design.a) Schematic and truth tables of the double-gate OSGTs-based AND logic.b) The optical image of the double-gate OSGTs.The scale bar is 70 μm.c) Compared to traditional AND logic, OSGTs-based AND logic can realize the same logic function within a single transistor.d) Current mapping of the AND logic function.e) Output of the AND logic function for different input logic states versus time.