High Performance and High Yield Solution Processed IGZO Thin Film Transistors Fabricated with Low‐Temperature Annealed Hafnium Dioxide Gate Dielectric

Solution‐processed microelectronics offer advantages, including cost‐effectiveness, higher energy efficiency, and compatibility with rapid prototyping compared to their counterparts fabricated through traditional semiconductor manufacturing processes. Unfortunately, solution‐processed transistors exhibit wide performance variability and low yield. In this work, a solution‐processed transparent indium gallium zinc oxide (IGZO) thin film transistor with a low temperature‐annealed hafnium oxide dielectric layer is described. Post‐annealing temperatures for the sol–gel hafnium dioxide thin film are reduced to below 200 °C, significantly expanding the range of substrates on which the metal oxide dielectric can be deposited. The fabricated devices exhibit excellent characteristics with high field‐effect mobilities of over 85 cm2 V−1 s−1, along with low subthreshold swing below 140 mV dec−1, high on/off ratios, and near‐zero threshold voltages when operating stably at low‐operating voltages of 2 V. The solution processed transparent hafnium dioxide gate dielectric IGZO transistors are shown to exhibit comparatively significantly lower device variation and high yield, allowing for the reproducible fabrication of large‐area and transparent solution processed microelectronics systems.


Introduction
Microelectronics circuits based on thin-film transistors (TFTs) have emerged as a favorable option in applications such as high-resolution displays, wearable electronics, and prosthetic DOI: 10.1002/aelm.202300415[9][10][11][12] Among the materials, amorphous metal oxides have been identified as a suitable candidate that is primarily used as high mobility transparent n-type semiconductor channel materials. [2,13]][16] The synthesis route of metal oxide sol-gel precursor inks is less complex compared to other carbonbased semiconducting materials that often require high purity sorting or substrate functionalization steps, [10,17] and has good shelf stability, making them suitable for large scale production.Incorporating suitable oxidizers and fuels into the precursor mixture can induce localized heating through exothermic, combustive reactions, [18,19] further reducing annealing temperatures and facilitate the deposition of thin films on less heat-resistive substrates used in flexible electronics.
In addition, solution processable high permittivity oxide dielectrics have been studied to further enhance thin film transistor performance.Amorphous Al 2 O 3 ( ≈ 6) has been reported to produce a stable thin film at annealing temperatures as low as 250 °C; [20] however, it exhibits poor wettability and is prone to pin hole formation which tends to cause gate shorting.23] Zirconium oxide can be derived through a wide range of precursor materials, including acetone acetates, [24] oxychlorides, [25] and nitrates, [26] however, the solution processed thin film morphology and relative permittivity can be significantly impacted by annealing temperature and postannealing UV-ozone treatments, which detrimentally affect device consistency. [24,27,28]This is particularly problematic in applications where large quantities of devices need to be fabricated over an extended area.31] While high performance metal oxide semiconductor and dielectric materials have been well established, few derived TFTs have achieved high field effect mobilities over 50 cm 2 V −1 s −1 .][34][35] Here, transparent, high yield, and device uniformity metal oxide TFTs are reported, in which high mobility IGZO channel and high permittivity HfO 2 dielectric layers were developed via a highly robust, efficient, and completely vacuum-free fabrication process involving spin-coating and low-temperature (<350 °C) annealing of sol-gel precursor solutions.Poly(3,4-ethylenedioxythiophene)poly(styrenesulfonate) (PEDOT:PSS) was used as the solution processable gate material that secured a high device yield by significantly reducing the likelihood of gate-source/drain shortcircuiting through defects in the dielectric layer of staggered device structures due to its polymeric property.Reduced annealing temperatures in constructing the IGZO-HfO 2 -PEDOT:PSS stack further prevented the potential issue of elevated temperatures affecting the properties of underlying layers.The solution processed TFTs exhibited remarkable performance, exhibiting saturation field effect mobilities of 86.4526 ± 9.5001 cm 2 V −1 s −1 , threshold voltages of − 0.3128 ± 0.0899 V, subthreshold swings of 140.4139 ± 31.7369 mV dec −1 .The well-defined channel region and proper control of film deposition conditions saw device yield exceeding 90%, while also acquiring excellent device uniformity, with key performance parameters having similar orders of precision and uniformity compared to ALD fabricated devices. [13,36]Furthermore, driving capabilities of the devices were demonstrated through the implementation of LED-driving circuits, making them ideal for AR or VR display applications.

Device Structure and Fabrication Procedures
Figure 1a illustrates the device structure for the solutionprocessed top gate bottom contact TFT.The physical appearance of the device is shown in Figure 1b.Bottom source and drain contacts were defined using laser ablation, achieving a W/L ratio of 300/30 μm on glass substrates coated with 100 nm of RFsputtered ITO.This was followed by subsequent deposition of IGZO, hafnia, and PEDOT:PSS as the semiconductor, dielectric, and gate layer, respectively, with each layer being annealed under their specific conditions before the next layer could be deposited.A single IGZO semiconductor layer was deposited on the prepatterned ITO electrodes followed by two consecutive layers of HfO 2 to minimize leakage current originating from surface profiles created during patterning and other possible defects.Kapton polyimide tape was used as a shadow mask to define the coverage area of each layer during spin coating.

Solution Processed Thin Films and Characterization
Indium-tin oxide (ITO) is a commonly utilized transparent conducting oxide known for its high optical transparency (over 80%) in the visible range and compatibility with various deposition techniques. [37,38]RF-sputtered ITO substrate pieces with sheet resistance less than 10 Ω sq −1 were acquired for this work.Through a controlled laser ablation process, the ITO coating could be completely removed to create a well-defined channel area.
Indium-gallium-zinc oxide (IGZO), as a typical high carrier mobility and transparent metal oxide semiconductor, was used as the channel material.[41] In addition, as a trimetallic compound, the chemical composition of IGZO can be varied to achieve a desired balance between high field effect mobility and near-zero threshold voltages in TFT devices. [36]n this work, an In:Ga:Zn molar ratio of 9:1:2 was used to achieve the documented performance.Hafnium(IV) oxide (HfO 2 , Hafnia) dielectric sol-gel precursor ink was formulated using hafnium isopropoxide isopropanol adduct and 2-methoxyethanol.As post-annealing temperatures used to thermally decompose the precursor compound and generate metal oxide bonds were still relatively high, often above 300 °C for hafnium-based precursors, the process can present a challenge for depositing thin films on materials susceptible to prolonged high temperatures.[42] Acetylacetone and ammonium hydroxide were added to the precursor solution as stabilizers and combustive agents that undergo an exothermic reaction during annealing, therefore providing a localized source for heating to facilitate a reduction in annealing temperature.[8,18] Hafnium isopropoxide isopropanol adduct can be readily hydrolyzed with the presence of hydroxide ions originating from the dissociation of the solvent and water in ammonium hydroxide solution, which then form a uniform thin HfO 2 film via the condensation and calcination reactions during annealing.[43] Low temperature sol-gel solution processed IGZO and HfO 2 films were prepared on glass substrates.The thickness of one layer of IGZO and that of two layers of HfO 2 was verified to be 52.3 and 103.5 nm, respectively, using a Stylus surface profiler (Figure 2a,b).Surface morphologies of prepared films were then imaged under an atomic force microscope.Results indi-cated both IGZO and HfO 2 films possessed a smooth surface, with RMS surface roughness of 559.8 and 345.1 pm, respectively.
X-ray photoemission spectroscopy was used to examine the chemical composition of the deposited films.Figures 3a,b illustrates the Hf 4f XPS spectra for HfO 2 thin films annealed at 200 and 350 °C, respectively.Both spectra exhibiting strong Hf 4f 7/2 peaks at 18.3 eV and Hf 4f 5/2 peaks at 19.9 eV suggested hafnium species were presented in metal oxide bonds.Deconvoluted XPS O 1s peaks were observed at 530.0, 531.4,and 532.6 eV in Figure 3c,d, with the dominant 530.0 eV peak corresponding to oxygen bonded to fully coordinated metal ions (M─O─M lattice).The latter weaker peaks were designated to M─O vac and residual hydroxyl species, respectively, where the small composition difference of <1% in hydroxyl species between the samples annealed at 200 and 350 °C indicated effective thermal decomposition of the original precursor compound, thereby confirming the chemical similarity of HfO 2 films annealed at different temperatures.A similar analysis was performed for 350 °C annealed IGZO thin film samples to verify their chemical composition (Figure S3, Supporting Information).
The crystallinity of deposited thin films was examined using X-ray diffraction (XRD).The observation in Figure 4a is consistent with IGZO adopting a largely amorphous structure due to trimetallic oxides frustrating crystallization. [14]A minor peak was observed at 30.8 ○ , corresponding to the (2,2,2) planes of indium oxide due to its high composition in the compound (ICDD Card 00-006-0416).The XRD spectra shown in Figure 4b confirm the similarity in morphology between HfO 2 thin films annealed at 200 and 350 °C.Both samples remain highly amorphous, not exhibiting monoclinic or cubic characteristic peaks attributed to spontaneously nucleated nanocrystal grains embedded in the amorphous matrix due to the relatively low annealing temperatures. [44]

Device Characterization and Performance
Electron microscopy images in Figure 5a illustrate the channel dimensions of the IGZO TFTs.The exact W/L ratio for the depicted device is 292.5/31.6 μm.Transfer and output characteristics curves are shown in Figure 5b,c.Figure S4, Supporting Information, illustrates the transfer characteristic curves of all 25 devices.Overall, the solution processed depletion type TFTs possessed excellent uniformity and yield, exhibiting high average saturated field effect mobilities of 86.4526 cm 2 V −1 s −1 with a standard deviation of 9.5001 cm 2 V −1 s −1 , an average threshold voltage of − 0.3128 ± 0.0899 V, and an average subthreshold swing of 140.4139 ± 31.7369 mV dec −1 , where the distribution of their performance is illustrated in Figure 4d.High calculated mobility values were reaffirmed via simultaneous voltage sweep measurements of both V gs and V ds with V dg fixed at a constant value and satisfying the condition of V dg > −V TH , eliminating any potential effect of leakage current in mobility calculation. [45]igh on/off ratios over four orders were recorded for devices, indicating sufficiently strong gate effect and proper gate insulation was achieved by the low-temperature processed Hafnia dielectric layer.Areal capacitance of the ITO-HfO 2 -PEDOT:PSS used to derive field effect mobilities were prepared on a separate piece of substrate concurrently with device fabrication.Figure S5, Supporting Information, depicts the areal capacitance of the three-layered structure over the frequency range of 20 Hz to 100 kHz.Transfer characteristic curves and gate current IV curves (Figure S7, Supporting Information) indicated when TFTs were biased into the cut off region, a small but noticeable gate current component was present.A high-resolution scanning electron microscopic image was taken across the device region to identify the cause.SEM analysis indicated that elevation edges generated during laser ablation attracted an accumulated volume of precursor solution, resulting in overly thick regions that were more likely to generate crevices under heat-induced mechanical stress during subsequent annealing processes (Figure 6).The defects were sufficient to provide a route for possible short circuits between the gate and bottom electrodes, which was supported by the observation of higher leakage currents in thermionic evaporated titanium gate TFTs and completely unfunctional devices that used sol-gel precursor derived ITO gates.In this work, 5 vol% DMSO doped PEDOT:PSS was used as the gate material.Compared to the dimensions of the crevices, PEDOT:PSS particles are in general 1-2 orders greater in dimension, therefore are significantly less likely to penetrate the dielectric crevices and create a path of electrical discharge. [46]This adjustment saw the effective reduction in the induced leakage current and significantly improved device yield and consistency.9][50] We also analyzed how ion impurity doping and carrier traps impacted the performance of the devices as hysteresis was observed for the devices (Figure S8, Supporting Information).The top-gate-bottom-contact architecture provides hafnia dielectric encapsulation for the IGZO layer, but also inherently places the semiconductor layer in direct contact with the ablated glass substrate.Ionic impurities, in particular Na ion from soda glass, can diffuse into the channel region during thermal annealing and introduce undesired hysteresis and reduce mobility of the device. [51]In addition, hysteresis can arise due to electron traps in HfO 2 dielectric thin films being filled by electrons originating from the underlying semiconductor layer. [52]The application of a positive gate voltage is reported to shift device characteristic curves toward enhancement mode operation, consistent with the results observed in this work. [36,52]ong-term time-dependent performance of the reported devices was further investigated to examine the resilience of fabricated devices operating in ambient environment.The device topology protected the IGZO semiconductor from ambient gas species and prolonged device lifetime such that clear observable transfer characteristics were still observable after 160 days left in ambient environments without further encapsulation using polymers.55] Water interacts with semiconductor materials in a more complex manner.With thinner IGZO film of <70 nm, H 2 O tends to show deep level acceptor like behavior, further introducing interface states that act as electron carrier trapping sites. [56]This analysis was supported by the results from the same devices reannealed at 120 °C for 30 min, where elevated temperatures aided in the partial removal of adsorbed species thus recovering trapped charges from localized states.
The devices exhibited superb current driving capabilities of over 1 mA at very low nominal operating voltages.Red and blue LEDs were successfully driven by the fabricated TFTs with gate signal and operating voltage supplied by a Digilent AD2 oscilloscope and instrumentation system (Figure S9, Supporting Information).

Conclusion
In summary, we have successfully demonstrated a fabrication process for high performance solution processed transparent thin film transistors.The fabricated devices possessed high saturation field effect mobilities of over 85 cm 2 V −1 s −1 and current driving capabilities, while exhibiting great uniformity and yield among devices.In addition, fuel additives and controlled processing conditions lowered the post annealing temperature of high-k hafnia dielectric films to below 200 °C.This significant reduction in processing temperature provides a solution for depositing high permittivity inorganic dielectrics on a wide range of transparent flexible substrates with thermal stability over 200 °C, which could possibly benefit the development of next-generation flexible AR/VR applications.Further improvement in device performance is believed to be possible with improved isolation of the semiconductor layer from possible exposure to performancehindering species.We anticipate the realization of low temperature, fully solution-based fabrication process toward high performance transparent microelectronics in the near future.

Experimental Section
Sol-Gel Precursor Ink Formulation: All reagents were purchased from Sigma-Aldrich as received.The IGZO precursor solution was prepared by dissolving every 28.3 mg of indium(III) nitrate hydrate (99.999% trace metal basis), 3.07 mg of gallium(III) nitrate hydrate (99.999% trace metal basis), and 4.9 mg of zinc nitrate hydrate (99.999% trace metal basis) in 1 mL of 2-methoxyethanol.10 μL of acetylacetone and 7 μL of ammonium hydroxide solution (28% NH 3 in H 2 O) were added to the solution additionally.The HfO 2 dielectric precursor ink was prepared similarly using 62.2 mg of hafnium isopropoxide isopropanol adduct, 15 μL of acetylacetone and 10.5 μL of NH 4 OH for every 1 mL of 2-methoxyethanol.The metal oxide precursor solutions were stirred vigorously under room temperature overnight.Before deposition, all precursor solutions were filtered using 0.21 μm PTFE syringe filters.
TFT Fabrication: The TFT devices were built on 25 mm × 25 mm 1.1 mm thick substrates.50 mm × 50 mm × 1.1 mm ITO glass pieces (Welljoin Green Technology China) were etched and scribed using a SUSS SLP300 laser ablation system to develop the desired source and drain electrode pattern.Before deposition, all substrates were sonicated in acetone, anhydrous ethanol, and deionized water sequentially followed by oven drying.Kapton polyimide tape masks were overlaid on top of the substrates to shield part of the ITO electrodes for probing.Then the substrates were treated by 5 min of Ar/O 2 plasma with 50 W RF power to improve surface wettability.IGZO and HfO 2 precursor solutions were spin coated at 1500 rpm for 35 s before annealing at 350 °C (200 °C for low temperature hafnium oxide thin films) for 90 min in ambient environment.Between subsequent depositions, 3 min of plasma treatment was required for better interfacing with the already deposited metal oxide thin films.One layer of IGZO and two layers of HfO 2 were required to achieve high device yield and consistency.PEDOT:PSS thin films were spin coated at 3000 rpm for 35 s and annealed at 120 °C for 15 min in air to form the gate electrode.The gate region was also defined by applying Kapton tape shadow masks.
Characterization: Deposited thin film thickness profiles were measured using a Bruker Dektak XTL stylus profiler.Thin film surface roughness measurements were obtained using MFP-3D atomic force microscopy.Scanning electron microscope images were taken using Hitachi FlexSEM1000 (MCFP) and FEI Nova NanoSEM 200 (RMMF).Device characteristic measurements were performed on a Cascade Microtech Summit semiautomatic probe system with an Agilent E5270B Precision IV analyzer for data acquisition.Samples for measuring areal capacitance were prepared separately by depositing ITO/ HfO 2 /PEDOT:PSS structures with overlapping areas of ≈300 × 425 μm using the same method as in device fabrication.Areal capacitance measurements of the solution-processed HfO 2 dielectric layer was then performed on a Keysight 4284A Precision LCR meter with a frequency range from 100 Hz to 50 kHz.The reference frequency was 1 kHz.XPS and XRD samples were prepared by spin coating precursor solutions onto of 1 × 1 cm 2 glass substrates.XPS characterization was performed using Thermo Scientific K-alpha XPS and XRD measurements were made using Bruker D4.

Figure 1 .
Figure 1.a) TFT Structure.b) Physical appearance of the fabricated TFTs.Scale bar is 5 mm.

Figure 2 .
Figure 2. Median-filtered surface profile of a) IGZO thin film; b) HfO 2 thin film.AFM surface morphology image of c) IGZO thin film; d) AFM image of HfO 2 thin film annealed at 200 °C.

Figure 5 .
Figure 5. a) SEM image of the TFT channel region.b) Representative transfer characteristic curve of solution processed TFTs.c) Representative output characteristic curve of solution processed TFTs.d) Statistical distribution of saturation field effect mobility, threshold voltage, and subthreshold swing of IGZO TFTs.

Figure 6 .
Figure 6.SEM image of HfO 2 dielectric thin film crevices at elevation edges.