Mixed‐Halide Perovskite Memristors with Gate‐Tunable Functions Operating at Low‐Switching Electric Fields

Crossbar circuits based on two terminal (2T) memristors typically require an additional unit such as a transistor for individual node selection. A memristive device with gate‐tunable synaptic functionalities will not only integrate selection functionality at the cell level but can also lead to enriched on‐demand learning schemes. Here, a three‐terminal (3T) mixed‐halide perovskite memristive device with gate‐tunable synaptic functions operating at low potentials is demonstrated. The device operation is controlled by both the drain (VD) and gate (VG) potentials, with an extended endurance of >2000 cycles and a state retention of >5000 s. Applying a voltage (Vset) of 20 V across the 50 µm channel switches its conductance from a high‐resistance state (HRS) to a low‐resistance state (LRS). A memristive switching mechanism is proposed that is supported by current injection models through a Schottky barrier and Kelvin probe force microscopy data. The simultaneous application of a VG potential is found to further modulate the channel conductance and reduce the operating Vset to 2 V, thus requiring a low electric field of 400 V cm−1, which is by a factor of 50× less compared to state‐of‐the‐art literature reports. Gate‐tunable retention, endurance, and synaptic functionalities are demonstrated, further highlighting the beneficial effect of VG on device operation.


Introduction
The goal of neuromorphics is to create systems that mimic elements of the brain, such as their capacity to accomplish complicated tasks in parallel with high energy efficiency, by adopting an inmemory-processing scheme. [1,2]5][6][7] This strategy will reduce the amount of energy and time spent communicating with the cloud, allowing these devices to be more autonomous, functional, and power efficient.Current state-of-the-art artificial intelligence (AI) systems such as DeepMind's AlphaGo target to simulate inference implemented within an artificial neural network of ≈10 12 neurons, requiring however thousands of parallel processing units that consume ≈10 MW compared to only 20 W of human brain operation. [6]14] Solution-based processing is compatible with reduced energy and material utilization for circuit manufacturing as well as provides better recyclability toward a lower carbon footprint. [15,16]rinted electronics can supplement conventional electronics in handling the rising volume of consumer products predicted in the IoT era.
Two terminal (2T) resistive memory devices termed memristors, have attracted great interest as single synaptic units with high scalability, 3D integration capability, and fast switching speed. [1,2,17,18]emristors have made significant advances in computation and security systems enabled by their inherent stochasticity, as well as in mobile communication because of their applicability as high-frequency switches with very low energy consumption. [4][21] The resistance of memristors is controlled by the migration of charge carriers, vacancies, or ions, which modulates their conductance through the formation/rupture of a filament or by modifying Schottky barriers at the contacts. [22]Soft switching is typically reported in memristors that are based on an interface-mediated process, whereas filament-based devices exhibit abrupt, hard switching.Some progress has been made in modifying the switching behavior of 2T memristors by controlling material stoichiometry or using multi-layered architectures. [19]The initial generation of synaptic devices was based on oxide memristors, which provided advantages in scalability, speed, and power consumption. [4,5,23,24]Multiple memristors could be integrated into a crossbar array geometry to perform vector-matrix multiplication directly utilizing Ohm's and Kirchhoff's law. [17]aterials that use both ionic and electronic fluxes have been successful in mimicking basic synaptic-level functions of biological neural networks, such as short-and long-term plasticity (STP and LTP), and system-level properties like spatiotemporal processing and homeostatic control. [10,11,25][14] OIHP's complex ionic character provides a massive playground for new dynamic phenomena such as the migration of ionic species and vacancies that are strongly coupled to electronic carriers, affecting channel doping or the formation of conducting filaments, making the underlying physics more complex than in conventional electronic devices. [25,26,28,36]Memristive behavior in OIHP is driven by the migration of I− vacancies that form conductive channels, thus exploiting what is usually a degrading ion migration effect in photovoltaic applications. [34,35,37,38]Light can used as an additional input while these devices typically display photoinduced carrier and ion migration. [39]Optoelectronic memristors, in particular, are intriguing candidates for optical sensing because they provide temporary memory and sensory data. [18,40]Some of the authors recently demonstrated in a multi-cation OIHP that is possible to use an efficient inverted solar cell structure based on a quadruple cation-based perovskite and implement parallel solar energy harvesting and memristive functionalities. [37,38]Stable resistance switching characteristics (with an high resistance state (HRS) to low resistance state (LRS) ratio of up to 10 5 and endurance of 3×10 3 ) were reported without affecting power conversion efficiency (PCE) performance even after multiple dc or thousands of ac switching cycles.Moreover, this hybrid 2T-structure emulated a wide variety of synaptic functions such as paired-pulse facilitation, long-term potentiation, long-term depression, spiking-ratedependent plasticity, and spike-timing-dependent plasticity. [37,38]emristive devices with three terminals (3T), known as memristive transistors (memtransistors), add a degree of flexibility by decoupling the write and read terminals while providing additional benefits compared to their 2T counterparts. [9,19,20,26]This provides synaptic circuits with concurrent inference and learning behavior toward more sophisticated neuromorphic functions at low voltages. [41]Schottky barrier tuning at metal-semiconductor interfaces using vacancy/ion transport, charge trapping, or ferroelectric domain switching are common operation mechanisms in memristive transistors. [22]As an example, Schottky barrier tuning based on hydrogen ion migration was used to generate gatetunable memristive activity in zinc oxide thin films. [19]Memristive transistors have also been studied in Ta 2 O 5 , TiO 2 , SrTiO 3 , and Ag/Cu atomic switches, often with the addition of an extra gate dielectric to reduce the leakage currents from the third terminal. [19]Aside from interface-mediated processes described above, filament-based hard-switching has also been investigated in memtransistor designs.Other switching processes have been investigated, such as those reported in phase transition materials or organic electrochemical transistors. [10,25,42]Overall, multiterminal device concepts such as 3T gate-tunable optoelectronic memristive transistors are necessary for more sophisticated biophysical realism which can offer further reconfigurability at individual nodes such as electrostatic gating and photoexcitation.
Very few studies on OIHP-based memtransistors or synaptic transistors were reported due to the inherent difficulties in achieving gate-tunable carrier conduction across perovskites. [43,44]In the majority of these studies, single cation, methylammonium lead iodide (MAPbI 3 ) or Cesium lead bromide (CsPbBr 3 ) perovskites (using a ferroelectric dielectric layer that induced the memristive switching effect) were used to fabricate memtransistors exhibiting moderate gate-tunable output characteristics. [39,45,46]It has been recently shown, however, that multiple cation incorporation, which employs strain-relieving cations like Cs and cations like Rubidium (Rb) as passivation/crystallization modifying agents, is an effective technique for lowering the vacancy concentration and ion migration in efficient perovskite field effect transistors (FETs). [43,44]igh carriers' mobility and enhanced gate tunability have been recently reported in OIHP-based transistors by controlling active layers phase stability through optimizing interface defects. [30,47,48]Moreover, this defect engineering strategy resulted in extended operational stability under specific bias tests in inorganic perovskite transistors. [47]Flexible MAPbI 3 -based transistors fabricated at low temperatures (150 °C) demonstrated mobility values of up to ≈11.5 cm 2 V −1 s −1 . [30]Stable ambient air processing and operation of MAPbI 3 -based transistors were demonstrated using a solvent engineering method, where oxygen was shown to passivate grain boundary defects improving the overall transistor performance. [49]A hybrid material stack comprising Tin oxide (SnO) and a perovskite overlayer was also reported to operate as an efficient channel in a phototransistor. [48]A perovskite-mediated photogating effect was shown to result in a favorable band alignment and interfacial charge transfer thus improving the device performance in terms of I on /I off ratio and photoresponsivity.
Herein, we report the development of solution-processed memristive transistors based on four-cation OIHP as the channel material that exhibits soft memristive switching controlled by drain (V D ) and gate (V G ) potentials.Under zero V G potential, programmable channel conductance between high resistance state (HRS) and low resistance state (LRS) is demonstrated, with a ratio of >300.The switching set voltage (V set ) depends on the maximum V D applied, while the memristive transistors exhibit an extended endurance of >2000 cycles and a state retention of >5000 s.Further memristive functionality onset and control is achieved by concurrently applying V G of up to ±12 V. Optimized devices exhibit gate-tunable resistance switching behavior with a V set as low as 2 V, namely an applied electric field (E a ) of ≈400V cm −1 that is a factor of 50× less compared to state-of-theart devices. [39,45]A memristive switching mechanism is proposed that is supported by current injection models through a Schottky barrier and Kelvin probe force microscopy data.A complete set of synaptic functionalities is recorded in both low and high V D regimes tunable by both light illumination and applied V G .

Perovskite Film Characterization and Device Fabrication
Top-gated memtransistors were fabricated on Ossila substrates with pre-patterned interdigitated Indium Tin Oxide (ITO) electrodes, used as source-drain (S-D) pads, with channel width (W) and length (L) of 30 mm and 50 μm, respectively.A four cation perovskite solution of anhydrous dimethylformamide: dimethylsulfoxide (DMF:DMSO) 4:1 (v:v) was deposited atop the S-D via spin coating (Figure 1a) at 6000 rpm for 45 s. 20 s prior to the end of the spinning process, a 200 μL volume of Chlorobenzene (CB) was drop cast as the antisolvent followed by annealing of the device at 100 °C for 45 min.The detailed fabrication process is reported in the experimental methods.The work function of ITO electrodes is ≈ −4.8 eV, while the conduction and valence band energy levels of the four-cation perovskite are −3.99 and −5.58 eV, respectively, as extracted by ambient photoemission spectroscopy (APS) (shown in Figure S1, Supporting Information). [35,37]This difference in energy levels between the S-D and perovskite channel indicate the potential formation of a Schottky barrier at the interfaces. [50]A 3D schematic and a cross-section scanning electron microscopy (SEM) image of the complete device is shown in Figure 1a,b, respectively.Further perovskite material characterization through UV-vis absorption and APS data, as well as SEM, Atomic Force Microscopy (AFM), X-ray diffraction analysis, and Photo-luminescence (PL), are depicted in Figures S1  and S2 (Supporting Information).The average perovskite grain size is reported to be ≈300 nm thus much lower than the channel length indicating that grain boundaries are expected to affect ions' and carriers' conduction.Regarding XRD data, the asperovskite does not show a preferred orientation of the crystallites (Figure S2, Supporting Information).The full width at half maximum (FWHM) of the (100) diffraction was estimated at 0.38°.The average crystallite size D was calculated at 24.2 nm according to the Scherrer equation: where K = 0.94,  = 0.154 nm,  = FWHM and  = peak position.Next, a poly(methyl methacrylate) (PMMA) solution in Ethyl Acetate was spin-coated as a gate dielectric on top of the perovskite layer at an angular speed of 1800 rpm for 60 s, followed by annealing at 50 ˚C for 1 h.The thickness of the PMMA film was measured to be ≈650 nm (Figure S3, Supporting Information).PMMA was selected because it is known to act as a good gate dielectric [51] and because it can be solution processed at low temperatures from solvents orthogonal to the perovskite layer.The device fabrication is completed by the thermal evaporation of a silver gate electrode with a thickness of 100 nm.No encapsulation was implemented on the samples, while measurements were performed during a period of more than six months without any significant device degradation noticed indicating the good lifetime stability of the devices (the thick PMMA layer that covers the perovskite has a passivation role as reported in the literature [51] ).

Gate Tunable I D -V D Characteristics Before Formation Process
We first investigated the gate effect on perovskite conduction prior to the memristive state formation.Like many different memristive systems, the device switching behavior should be activated through a high-bias formation step. [5,8,37]Therefore, aiming at avoiding the formation process in a fresh sample, the gatedependent output characteristics (I D -V D ) were initially measured at low V D bias (Figure S4a, Supporting Information).The behavior suggests n-channel formation for the fresh devices since a positive V G leads to a current enhancement (i.e., electron accumulation), while a negative V G to depletion of the majority carriers.This is in agreement with previous reports on samples where no degradation and water adsorption occurred. [43]A typical measurement process of activating ion immigration associated with Schottky barrier onset and filament formation at the interfaces between perovskite and S-D contacts is depicted in Figure S4b (Supporting Information).At least 10 V is required across the channel before any change in the resistance can be observed.The device is initially at a HRS (channel current in the nA regime).As the V D increases gradually to 15 V, the onset of a LRS is observed.Few cycles at high V D are usually required for the stabilization of the memristive switching loop.

Figure 2a
,b shows the output characteristics at high V D of ±40 V in linear and logarithmic scale, respectively, for a typical perovskite memristive transistor.A high positive V D of 40 V is applied for 5s before the measurement starts.The V D is then swept to −40 V and back again to +40 V having a 100 mV step and a scanning rate of 100 mV s −1 , unless otherwise stated.The initial high V D bias sets the device to the HRS, while a slightly negative V D switches the device to the LRS.A reset voltage of −8 V is required to set the device back to HRS.During the last part of the memristive loop (from 0 to +40 V), the device jumps to LRS at low positive V D , while at V D equal to 8 V the device returns to its initial HRS state.This type of bipolar I D -V D hysteresis with current humps as shown in Figure 2a,b, has been attributed to the existence of deep-level traps inducing a switchable Schottky barrier at S-D contacts and/or the polarization-switching effects in oxide devices. [19,22,50]The strong impact on the current conduction mechanism of the cation stoichiometry and Schottky barrier formed at S-D interfaces is reported in the literature of oxidebased perovskites while the overall rotation directions of the I D -V D switching characteristics have been discussed. [22]Specifically, excess of Bi in BiFeO 3 results in devices with clockwiseclockwise current humps while bismuth deficiency promotes devices with counterclockwise -counterclockwise rotation directions in the I D -V D curves.The almost symmetric I D -V D characteristics of Figure 2 agree with the fact that both S-D contacts are based on the same material (ITO).
The ratio between HRS and LRS versus V D is plotted in Figure 2c, indicating a value in excess of >300 at V set = ±8 V. To our knowledge, this is the highest value reported in perovskitebased memtransistors (10× higher when compared to Ref. [44]).The E a value at V set of 8 V is equal to 1.6 kV cm −1 that is by a factor of 12.5× less compared to state-of-the-art literature reports (i.e., memtransistors based on perovskite in Ref. [44] require a V D > 60 V applied across a channel of 30 μm thus an E a equal to 20 kV cm −1 ). Figure S5a (Supporting Information) shows the dependence of V set and V reset values on maximum V D , while multiple curves measured at the same conditions (Figure S5b, Supporting Information) indicate good switching stability.Corresponding measurements performed at different scanning rates (50-200 mV s −1 ) are shown in Figure S5c (Supporting Information) indicating a minor shift to higher V set values while the scan rate increases in agreement with previous results in 2T memristors based on the same OIHP active layer. [37,38] with bipolar memristive function at lower V D values (by sweeping V D from +25 V to −25 V) are also shown in Figure S6 (Supporting Information), achieving an HRS/LRS ratio of ≈200 at V set = 7 V.The gate bias effect on I D -V D characteristics measured at high V D is depicted in Figure S7 (Supporting Information) indicating that V G is mainly enhancing the current at the LRS with a weak concurrent enhancement of the HRS/LRS ratio.

Memristive Switching and Current Injection Mechanism
The origin of the memristive switching in perovskites is related to the ion migration that takes place via ion vacancy sites, which are prevalent at the grain boundaries.By applying a bias voltage, volatile ions within the perovskite, such as Iodine vacancies (I ̶ ) and methylammonium (MA) ions, and free carriers, drift toward S-D contacts, depending on their charge polarity, modulating thus the effective Schottky barrier at ITO/perovskite interface.In Figure 3a, a schematic describing the switching mechanism based on ions and carriers' migration is depicted.The redistribution of the ionic species and free carriers is modifying in a non-volatile way various interfacial parameters (e.g., the density of states, local barrier height, barrier thickness, etc.) at S-D interfaces. [39,45,46,50,52]The concentration of I within the per-ovskite layer was reported higher in regions close to the electrode using grazing-incidence wide-angle X-ray scattering adding this way an ion conduction pathway supporting the argument that I ̶ is the dominant ion in perovskite films due to its lower formation energy and higher mobility. [39]y applying an opposite bias, a reversed ion/carrier distribution is obtained by modifying the corresponding potential barrier profile along the surface of the channel (Figure 3b) leading to the HRS to LRS transition and the memristive-like I D -V D characteristics.The low-bias memristive switching effect reported here should be attributed to the multi-cation composition of the OIHP that assists the Schottky barrier formed at the channel and S-D contacts interfaces. [37,38,43]Notably, it has been shown in 2T memristors that MA and I − have the smallest activation energy for vacancy-mediated ion migration, and furthermore, the multi-cation structure of OIHP enhances the memristive switching effects and their stability. [37,38]Possibly contribution of a filament-based mechanism that is mainly induced by iodine vacancies, I ̶ , or subsequent trapping of charges within the grain boundaries [52] cannot be excluded.For an overview of reported switching mechanisms in perovskite-based memristors and the potential contribution of halides migration, bulk perovskite defects, MA or Ag migration, the reader is redirected to Ref. [37] and references therein, and specifically Table S2 (Supporting Information), where a detailed comparison of different memristor technologies in terms of switching characteristics and mechanisms are reported involving various types of halides vacancies, perovskite defects, metal electrodes migration contribution, as well as Schottky barriers modification.
To further support this switching mechanism, AFM topography and Kelvin probe force microscopy (KPFM) measurements have been implemented.An optical image showing the spot between the electrodes where the AFM and KPFM data were recorded is shown in Figure S8 (Supporting Information).
For these measurements, devices without PMMA were prepared in order to have direct contact with the perovskite surface.Figure 4a-d shows the AFM topography and KPFM images of the perovskite surface at device HRS and LRS, respectively.Corresponding topography and potential profiles for HRS and LRS are extracted along the vertical lines shown in Figure 4, while accordingly depicted in Figure 5.The comparison of Figure 4a,c indicates that the topography of the perovskite surface does not change with the application of the external bias (30 V).However, a significant change in the Contact Potential Difference (CPD) profile measured along the channel direction is reported when the device is switched from HRS to LRS (comparison between Figure 4b,d).As shown in Figure 4b, the device when set at HRS shows a uniform CPD profile across the device channel.On the other hand, in LRS, the sample exhibits a gradually increasing CPD profile, while a potential step of ≈100 mV appears toward the electrode.This behavior is in agreement with the qualitative mechanism proposed in Figure 3.The detailed calculation of the perovskite W F difference (Δ) between HRS and LRS based on the KPFM data is reported in Methods.Overall, we observe a suppression of perovskite surface W F when the device is switched from HRS to LRS because of the ion's migration.
High-resolution AFM topography and KPFM profiles were also recorded in regions of 2 × 2 μm 2 (Figure S9, Supporting Information) while the device was switched from HRS to LRS, aiming at investigating possible modifications at the grain boundaries level.Figure S9b (Supporting Information) shows a high potential contrast around the grain boundaries of the perovskite, which indicates a local, high charge concentration.Measurements in devices set in LRS on the other hand (Figure S9d, Supporting Information), show a more uniform potential distribution across the channel thus not limited to the grain boundaries.
In Figure 6a, we use the current injection theory through a metal/ semiconductor/metal structure in order to fit the experimental curves of the devices operating in either HRS or LRS state.It is well-known that the I D -V D characteristics of a reverse-biased Schottky diode are mainly controlled by the barrier height.The current density under reverse bias defined by the blocking Schottky diode is given by [22] where  = q/k B T,  b is the Schottky barrier height, A is the channel area, A* is Richardson's constant, V is the applied voltage, d s is the effective switching thickness, ɛ i is equal to ɛ op ɛ o where ɛ op ɛ op is the dynamic high-frequency dielectric constant of the per-ovskite film equal to ≈6, [53] ɛ 0 is the permittivity of vacuum (ɛ 0 = 8.85 × 10 −12 F m −1 ), q is the electron charge (q = 1.6 × 10 −19 C), k B is the Boltzmann constant, and T is the temperature.The energy barrier height ( b ) and the d s are obtained from the slope and intercept of the plot of , respectively.The slope reads kT .The factor lnA • A* can be ignored because it is much smaller than q b kT .Using this method, the  b of the device in HRS can be obtained and is equal to ≈0.41 eV.

Gate Tunable I D -V D Characteristics at Low V D Regime
The I D -V D characteristics measured at a low V D regime, as shown in Figure 7a (black curve), reveal a much stronger effect of V G on the drain current.A very weak memristive switching is observed while sweeping V D in the ±7 V range at V G = 0 V.Under these conditions, V set is equal to ≈2 V resulting in a switching E a of ≈400V/cm that is a factor of 50× less compared to state-ofthe-art devices. [39]A strong gate-induced switching is observed upon V G increase, achieving an HRS/LRS ratio of ≈30 with a concurrent slight shift on V set toward higher bias (Figure 7).I D -V D measurements obtained under negative V G are also shown in Figure S10a (Supporting Information).The transfer characteristics (I D -V G plot) at constant V D while sweeping V G bias from −12 to 12 V are depicted in Figure 7b.Stronger gate-induced current modulation is reported at the region close to V set (V D = 1.5 V) in agreement with the output characteristics under different V G biases shown in Figure 7a.In order to exclude the possible contribution from gate leakage current, plots of gate current versus gate voltage were measured and shown in Figure 7b (right axis).A maximum leakage current of a few hundred nA is reported at V G = ±12 V, which is a typical leakage current for PMMA-based transistors. [51]It should be noted that both V D and V G can control the charges (carriers and ions) accumulated at the channel/contacts interfaces and the filament formed across the channel.Therefore, a direct correspondence between output and transfer characteristics is not straightforward, and a simple superposition of the effect of the V D and V G biases on channel conduction should not be expected like in a conventional transistor device. [45]Moreover, traps-to-trap hopping across the perovskite bulk as well as at the PMMA/perovskite interface could be the sources of the slight asymmetries reported by comparing negative and positive scans of V D and V G .Lastly, a screening effect between V D and V G as well as a competitive mechanism between the filament and interface-mediated switching should be also taken into account. [45]

Light and Gate Effect on State Retention and Endurance Performance
State retention and cyclic endurance of the memtransistors were measured by either applying high (Figure 8a,b) or low V D values (Figure 9a,b), initially performed at dark conditions and zero V G .Specifically, Figure 8a shows the LRS and HRS retention when a setting pulse with an amplitude of ±25 V (thus at a high V D regime) and a duration of 500 ms is used.For resistance reading, a pulse with an amplitude of −1.5 V was used while reading was performed every 20 ms for a total period of 5000s (−25 V sets the sample at HRS while +25 V at LRS).Overall, excellent retention performance of more than 5000s is observed with an average resistance of 10 m and 1 kΩ, for HRS and LRS (thus ratio of ≈10 4 ), respectively.A very weak increase in LRS is observed in agreement with previous reports on perovskite-based memristors. [37,38]Endurance cycles between HRS and LRS under dark and zero V G conditions were also measured at high V D values as depicted in Figure 8b.For this measurement protocol, a pulse with amplitude of ±20 V and duration of 50 ms was used.
For resistance reading, a pulse with an amplitude of −2 V was used while reading was performed every 10 ms for a total period of 50 ms in each resistance cycle (averaged resistance values are extracted from 5 points per cycle).LRS is found to be stable even after 2000 cycles with a mean value of ≈5 kΩ, while HRS exhibits a stable, average resistance value of ≈1 m.
To investigate the LRS retention at a low V D regime, the following pulse settings were used: a pulse amplitude of 8 V and a pulse duration of 200 ms.For the resistance reading process, a pulse with an amplitude of −1.5 V was used while reading was performed every 20 ms for a total period of 100s (black curve in Figure 9a).Compared to the LRS retention measured at a high V D regime under dark and zero V G conditions (Figure 8a), a weak V D pulse excitation leads to higher initial LRS (≈3 kΩ) that also exhibits much lower retention (after 100s the LRS has increased to >20 kΩ).Notably, by switching on gate bias to 8 V (while still under dark conditions) the LRS retention performance is significantly increased with no apparent LRS increase within the first 100s (red curve in Figure 8a).This behavior is in agreement with gate-dependent output characteristics of Figure 7, where a strong memristive switching was reported under V G bias despite the low V D regime.Gate action is therefore shown to also enhance the state stability during retention protocols.To test the light illumination effect on LRS retention characteristics under gate bias (8 V), the measurement was repeated (after resetting the sample) while applying an illumination of 40 mW cm −2 (while LED lamp).Representative measurements shown in Figure 9a (green curve) reveal that light illumination suppresses the LRS retention counteracting the effect of the applied V G bias.The LRS amplitude after 100s reads ≈7 kΩ thus lower than the case of V G = 0 V but still higher than the case for V G = 8 V under dark conditions.This behavior agrees with literature where light illumination was shown to enhance the I ̶ recombination rate of iodine ions with corresponding vacancies that lead to resistance increase. [37,38]he gate effect on the endurance cycles was also investigated using moderate V D pulses with an amplitude of ±5 V and a duration of 200 ms (thus in a low V D regime).Corresponding data for 50 cycles under zero V G and V G = 6 V are presented in Figure 9b,c, respectively.The measurements under V G bias The following pulse settings were used: amplitude ±25 V and pulse duration 500 ms.For resistance reading, a pulse with an amplitude of −1.5 V was used while reading resistance values every 20 ms for a total period of 5000s.B) Endurance cycles between HRS and LRS.The following pulse settings were used: amplitude ±20 V and pulse duration 50 ms.For resistance reading, a pulse with an amplitude of −2 V was used while reading every 10 ms for a total period of 50 ms.C) Potentiation and depression pulse protocols using 50 pulses of amplitude of ±10 V and duration of 500 ms each.D) Short-term (STP) and long-term (LTP) plasticity measurements.For the LTP protocol, 10 pulses were used with an amplitude of 10 V and duration of 200 ms each, while for STP 5 pulses were applied with amplitude of 5 V and duration 100 ms each.Reading was implemented at −1 V with data taken every 20 ms.depict a higher LRS/HRS ratio (ratio equals after 50 cycles compared to only 6 in the case of zero V G ) and a more stable and constant LRS and HRS as the number of endurance cycles increases.Overall, V G also enhances the endurance stability of the memristive switching effect in agreement with retention and output characteristics data previously presented.Data of gate tunable endurance characteristics at high V D values are presented in Figure S11a,b (Supporting Information).Specifically, endurance cycles were measured using a V D pulse of ±40 V with a duration of 200 ms for V G = 0 V (Figure S11a, Supporting Information) and V G = 6 V (Figure S11b, Supporting Information).For the resistance reading, a pulse with an amplitude of −1.5 V was used while the resistance reading was performed every 10 ms for a total period of 50 ms per cycle.It is noted that in contrast to the low V D measurements, the improvement upon V G = 6 V application was moderate both in terms of enhancing the HRS/LRS ratio and resistance state stability in time.

Light-and Gate-Tunable Synaptic Functionalities
Basic synaptic functionalities were also implemented under dark light illumination and zero V G .In Figure 8c, long-term potentiation and depression pulse protocols are presented using a train of 50 pulses with an amplitude of ±10 V and a duration of 500 ms each, respectively.An extended synaptic current modulation is achieved under the application of 50 positive-amplitude pulses, while a sharp current depression is shown upon the application of 50 negative-amplitude pulses.STP and LTP plasticity measurements are shown in Figure 8d.For the LTP, 10 pulses with an amplitude of 10 V and a duration of 200 ms were initially applied, while the resistance was recorded for a period of 1000s (read at −1 V every 20 ms).For STP, 5 pulses with a lower amplitude of 5 V and a duration of 100 ms were applied, while the resistance was measured under identical conditions of LTP measurement.Gate and light tuneable functionalities are presented also in Figure 9d.Specifically, long-term potentiation processes under light and gate bias were implemented by applying a protocol of 20 pulses with an amplitude of 5 V and a duration of 100 ms each.Initially, zero V G and dark conditions were applied to the sample (black curve).Despite the low V D amplitude and short pulse duration, a long-term potentiation process is demonstrated leading to a 6× synaptic current enhancement at the end of the 20-pulse train.The measurement was then repeated by applying a V G = 3 V (red curve) and V G = 6 V (green curve).The beneficial role of the gate bias is also apparent during these potentiation measurements leading to a 15× enhancement of the postsynaptic current under V G = 6 V. Corresponding measurement under light illumination was also demonstrated by switching on the light source to 8 mW cm −2 while setting V G = 0 V (blue curve).Light activation led to the suppression of the device resistance in agreement with retention data under illumination (Figure 9a).

Conclusion
A mixed-halide perovskite memristive device with gate-tunable synaptic functions was demonstrated.The device exhibits robust operation at low switching electric fields.Channel resistance modulation is achieved by either V D or V G application.Notably, at low V D where the in-plane electric field is not sufficient to induce a strong memristive switching, V G can control the onset of the HRS to LRS transition reducing thus the required switching lateral potential (i.e., V S -V D ) down to E a values of ≈400V cm −1 that is a factor of 50× less compared to state-of-the-art devices.A memristive switching mechanism is proposed that is supported by current injection models through a Schottky barrier applied to fit the experimental curves and KPFM data.Memtransistors with gate tunable endurance (>2000 cycles) and state retention (>5000 s) were demonstrated.A complete set of synaptic functionalities was recorded for both low and high V D regimes which were found to be tunable by light illumination and V G extended the available functions and controls of the system.was prepared from an 80 mg mL −1 PMMA in Ethyl Acetate solution by spin-coating 60 μL on the perovskite layer at an angular speed of 1800 rpm for 60 s and 1000 rpm s −1 acceleration.The layers were subsequently annealed at 50 C for 1 h.The contact parts of the ITO substrate were exposed by scratching away the residual materials using a razor blade.Afterward, the substrates were transferred in a high vacuum chamber for the thermal evaporation of 100 nm Ag gate contact under a high vacuum of 10-6 mbar using an Ossila Gate Deposition Mask.
The highest occupied molecular orbital (HOMO) level and the work function (W F ) were estimated by ambient photoemission spectroscopy (APS) using an APS04 N2-RH system (KP Technology).More specifically, the contact potential difference (CPD) was measured using a vibrating gold alloy probe (2 mm in diameter).The W F of the tip was estimated to be 4.54 eV, which was calibrated by measuring a freshly polished silver reference and calculating its absolute W F by APS.The valance band was determined using a UV light excitation source (D2) with excitation energy in the range of 3.8-6 eV and by extrapolating to zero the cube root of the photoemission signal.The lowest unoccupied molecular orbital (conduction band) level was calculated in conjunction with UV-vis measurements using the following formula.
where E g is the optical bandgap estimated from the Tauc plot.Optoelectronic Characterization of Memristive Transistors: Optoelectrical characterization was performed using a customized measurement platform developed by ARKEO (Cicci Research s.r.l.).For the dc I-V switching loops, the dc voltage was swept between −40 and 40 V (or lower values) while measuring the current flowing through the structure at various gate biases (maximum gate voltage applied is 12 V that is the limitation of the setup) and, light illumination, scanning rate, and the compliance current (I cc ) conditions.For the pulsed switching measurements, a specific pulsed memristor module was developed in collaboration with Cicci Research s.r.l, offering the option to define completely custom waveforms to be applied to the device using the convenient Arkeo waveform generator tool.In specific, arbitrarily customizable voltage pulses (either single or train of pulses) with the desired number of pulses, pulse amplitude, and duration were generated and applied while monitoring the device resistance.Specific pulse protocols were defined for performing endurance and retention measurements as well as for STP, LTP, and potentiation and depression behavior as detailed in the corresponding plots.
AFM Topography and Kelvin Probe Force Microscopy (KPFM): The perovskite channel surface topography and KPFM images were acquired in the amplitude-modulated mode (AM-KPFM) under a single pass scan, by using two different lock-in amplifiers.The probe has a tip coated with Cr/Pt (Multi75-G), a resonant frequency of 75 kHz, and a force constant of 3 N m −1 .For acquiring the topography images, the probe oscillates near its resonant frequency at an amplitude of 16 nm.For the acquisition of the KPFM signal, an AC voltage of 17 kHz and 0.7 V amplitude was applied to the tip via a second lock-in amplifier.The sample-to-tip distance was minimized by controlling the set point.The tip was brought close to the sample surface to increase the sensitivity and spatial resolution.The AFM and KPFM images were recorded using Parks XE7 AFM system and the images were processed with the Gwyddion software.
Work Function Calculation Based on KPFM Data: The work function of the sample  sample can be determined by the following equation: where  tip is the work function of the tip and q is the electron charge.Assuming the work function of the tip did not change during the measurements, then the work function change Δ upon the application of external bias is given by: Δ =  HRS −  LRS = q ( V CPD,HRS − V CPD,LRS ) where the subscript HRS and LRS refer to the sample set to HRS and LRS, respectively.Following the values extracted by KPFM, thus a CPD value of −570 and +400 mV at HRS and LRS, respectively, the Δ is estimated at ≈0.9 eV at the channel central part, while ≈1 eV at the perovskite/electrode interface.Therefore, the work function of the perovskite is considerably reduced by ≈1 eV after setting the device to LRS.

Figure 1 .
Figure 1.a) 3D schematic of the device.Glass substrates were used with prepatterned ITO-based Interdigitated electrodes (IDEs) serving as the source and drain contacts.The channel based on the perovskite layer has a fixed length of 50 μm and a total width of 30 mm.Spin-coated PMMA, and thermally evaporated silver, were used as gate dielectric and gate electrode, respectively.The inset shows a top view of the ITO-based IDE.b) Cross-section SEM image of a complete device indicating a perovskite film thickness of ≈380 nm and a PMMA thickness of ≈600 nm (silver metal pad thickness is ≈100 nm).

Figure 2 .
Figure 2. Typical drain current-voltage (I D -V D ) characteristics in (a) linear and (b) in logarithmic scale indicating a bipolar memristive switching by sweeping V D from +40 to −40 V and back to+40 V. c) Low resistance to high resistance ratio (LRS/HRS) versus V D plot.All measurements performed at a scanning rate of 100 mV s −1 with steps of 100 mV.

Figure 3 .
Figure 3. Schematic of the charge and ions transport-based switching mechanism.a) Corresponding variations of the potential barrier profiles along the surface of the channel (from S to D) in the LRS and HRS.b) Schematic showing the net distribution of iodine ions (I−/I) and I vacancies (V I ) in the LRS.I− drift toward the drain (D), leaving behind a high concentration of VI at the source (S).Reversing the bias will cause the I− to drift in the opposite direction (toward the S), their recombination with the VI, and switching from LRS to HRS.

Figure 4 .
Figure 4. Topography and KPFM images of perovskite surface (a),(b) at HRS and (c),(d) at LRS, respectively.The profiles shown in Figure 5 are extracted along the vertical lines shown here.The images for the HRS and LRS were acquired close to the same position.

Figure 6 .
Figure 6.Fitting of the experimental I D -V D at LRS and HRS.a) Fitted data using Equation (3) of I D -V D characteristics indicating a Schottky emission and ohmic conduction in HRS and LRS respectively.b) Ln-ln plot of I D -V D in LRS where a linear function can fit the experimental data.c) Plot of ln( 1 T 2 ) versus √ V where from the intercept of the plot (≈ −13.84) the  b can be extracted equal to ≈0.41 eV.

Figure 7 .
Figure 7. a) Gate effect on I D -V D characteristics measured by sweeping V D from +7 to −7 V while stepping V G from 0 to 8 V. Measurements performed at a scanning rate of 50 mV s −1 .b) Drain current-gate voltage (I D -V G ) characteristics measured at constant V D = −1.5 V and V D = −3.5 V. Typical gate leakage current for a device with a PMMA thickness of ≈650 nm is shown in blue data.

Figure 8 .
Figure 8. A) Low and High Resistance state retention at high V D regime.The following pulse settings were used: amplitude ±25 V and pulse duration 500 ms.For resistance reading, a pulse with an amplitude of −1.5 V was used while reading resistance values every 20 ms for a total period of 5000s.B) Endurance cycles between HRS and LRS.The following pulse settings were used: amplitude ±20 V and pulse duration 50 ms.For resistance reading, a pulse with an amplitude of −2 V was used while reading every 10 ms for a total period of 50 ms.C) Potentiation and depression pulse protocols using 50 pulses of amplitude of ±10 V and duration of 500 ms each.D) Short-term (STP) and long-term (LTP) plasticity measurements.For the LTP protocol, 10 pulses were used with an amplitude of 10 V and duration of 200 ms each, while for STP 5 pulses were applied with amplitude of 5 V and duration 100 ms each.Reading was implemented at −1 V with data taken every 20 ms.

Figure 9 .
Figure 9. Gate and light tunable retention, endurance, and synaptic functionalities under a low V D regime.a) Low Resistance state retention at low V D regime.The following pulse settings were used: pulse amplitude of 8 V and duration of 200 ms.For the resistance reading, a pulse with an amplitude of −1.5 V was used while reading every 20 ms for a total period of 100s.b,c) Endurance cycles using V D pulses with an amplitude of ±5 V and duration of 200 ms for (b) V G = 0 and (c) V G = 6 V.For the resistance reading, a pulse with an amplitude of −1 V was used while reading every 10 ms for a total period of 50 ms per cycle.d) Long-term Potentiation process under light and gate bias.Protocols using 20 pulses of amplitude of 5 V and duration of 100 ms each.