BLAST: A Wafer-scale Transfer Process for Heterogeneous Integration of Optics and Electronics

We present a general transfer method for the heterogeneous integration of different photonic and electronic materials systems and devices onto a single substrate. Called BLAST, for Bond, Lift, Align, and Slide Transfer, the process works at wafer scale and offers precision alignment, high yield, varying topographies, and suitability for subsequent lithographic processing. We demonstrate BLAST's capabilities by integrating both GaAs and GaN microLEDs with silicon photovoltaics to fabricate optical wireless integrated circuits that up-convert photons from the red to the blue. We also show that BLAST can be applied to a variety of other devices and substrates, including CMOS electronics, vertical cavity surface emitting lasers (VCSELs), and 2D materials. BLAST further enables the modularization of optoelectronic microsystems, where optical devices fabricated on one material substrate can be lithographically integrated with electronic devices on a different substrate in a scalable process.


MAIN TEXT
Heterogeneous integration of dissimilar materials-combining devices or circuits made from two or more functional materials in a single integrated platform, push technology advances in ways that single material systems cannot [1][2][3].One of the most compelling examples is the integration of III-V photonic devices with silicon electronics, with applications ranging from on-chip high bandwidth communication [4,5] to wearable/implantable devices for diagnostics and therapeutics [6][7][8].One approach to heterogeneous integration of dissimilar materials is heteroepitaxy, but it is a major challenge to grow different high-quality crystalline materials on a single substrate.
While some notable successes have been shown [9], in general lattice mismatch and different thermal expansion coefficients prevent monolithic growth of defect-free material [10].
An alternative is transfer-based heterogeneous integration-the separate fabrication of devices on two or more substrates, followed by a transfer step to combine them.This allows growth and fabrication processes associated with each substrate to be independently optimized [11] and the two parts combined only at a later step.An ideal transfer method would provide: 1) high alignment accuracy, 2) high transfer yield, 3) wafer-scale transfer, 4) applicability to structures of varied dimensions and geometries, and 5) be amenable to subsequent lithographic processing.Within the past decade, a wide variety of transfer methods have been developed, such as elastomer stamp transfer [12][13][14], flip-chip bonding [15,16], pick-and-place [17] and fluidic assembly [18].However, none of them fully meet the requirements above.For example, flip-chip bonding does not allow for subsequent processing, pick-and-place is a serial, slow process, and fluidic assembly does not work for small samples.Elastomer stamp transfer comes the closest and is currently being incorporated into commercial foundry process flows [19].However, it requires suspending the devices to be transferred, is difficult for materials grown on chemically inert substrates such as GaN on sapphire [20,21], and it typically operates at less than full wafer scale.
In this letter, we present BLAST, a robust, wafer-scale transfer technique for heterogeneous integration that meets all of the requirements listed above.Figure 1 illustrates the process, showing the heterogeneous integration of silicon electronic devices (Fig. 1A) and optical III-V μLEDs (Fig. 1B).We demonstrate transfer both GaAs-based and GaN-based μLEDs from their native substrates (GaAs and sapphire) onto a target Si substrate with precision alignment (~1μm) and high yield (~99.9%).
We use this process combined with subsequent lithographic processing to fabricate broadband optical upconverters (Fig. 1C-F) that absorb low-energy photons (Si PVs) and emit higher-energy ones (GaN µLEDs).We finally show that this transfer technique can be used for a wide variety of materials/substrate combinations including the integration of VCSELs and foundry CMOS as well as for the layer-by-layer aligned assembly of 2D van der Waals materials.
BLAST consists of four steps: (i) Bonding of the µLED native substrate to a transparent sapphire carrier wafer, then (ii) Lifting of the µLEDs from the native substrate, then (iii) the Alignment of the µLEDs to features on the target substrate, and finally (iv) Slide Transfer of the µLEDs from the carrier wafer to the target substrate using a thermal slide technique.This is shown for the case of µLEDs in Fig. 2. The µLEDs are first fabricated on their native substrate using standard lithographic processes (see Materials and Methods), along with precision alignment marks.For GaN µLEDs, a metal layer is added for laser shielding during the removal process, as discussed in Materials and Methods.Separate, complementary alignments marks are also patterned on the target substrate for precision alignment.In most cases, a 500nm layer of SU8, a standard epoxy-based adhesion layer, is spun onto the target substrate.
For Bonding of the native substrate to the carrier wafer, two different polymer layers are applied, each playing a different role.Poly (methyl methacrylate) (PMMA) is spincoated onto the native substrate as a protection layer to prevent damage to the μLEDs during etching and transfer.Separately, a layer of polypropylene carbonate (PPC), a thermoplastic polymer, is spin-coated onto the sapphire carrier wafer.PPC's role is to temporarily bond the carrier wafer to the μLED substrate.This is accomplished using a hot press at p = 1.5 bar and T = 135° C. Both PMMA and the PPC are highly transparent (as is the sapphire carrier wafer) and not light sensitive, facilitating optical alignment.Both can be subsequently easily removed by standard processes.
The μLEDs are then Lifted from the native substrate, leaving behind only the μLEDs and alignment marks attached to the carrier wafer by the PPC (Fig. 2A).Removal of the devices from the native substrate can be accomplished by a variety of means.Here we use selective wet etching of the substrate in the case of GaAs µLEDs [22], stopping on an AlGaAs release layer.For GaN µLEDs, we use excimer laser lift-off [23] (Fig. 2A) that decomposes a thin layer of GaN to metallic gallium and nitrogen gas to release the devices.
For Alignment, the μLEDs on the carrier substrate are spatially (x, y) and rotationally (θ) aligned to pre-patterned alignment marks on the target Si substrate using a standard contact (ABM) mask aligner, as shown in Figs.2A, 2B.They are brought into contact and heated to 100°C using a custom heater stage to promote adhesion.They are then removed from the aligner.
For Slide Transfer, the stack is further bonded using a hot press at p = 0.7 bar and T = 155°C, above the melting temperature of the PPC (~100-120°C), but below that of the PMMA(~190°C) [24,25].Finally, they are separated by placing on a hot plate at T = 160°C and using the lateral thermal slide technique [26] to remove the sapphire carrier substrate, as shown in Fig. 2B.Any residual PMMA and PPC are cleaned in acetone.
BLAST is now complete and standard lithographic processing can now continue.
Figure 3 shows two examples of wafer-scale BLAST transfer of GaAs (Fig. 3A) and GaN (Fig. 3D) μLEDs from their native substrates to target Si substrates.The transfer process is performed across the entire 4"(GaAs) or 2"(GaN) wafer with high yield.The   Figure 4B illustrates the high yield of BLAST for a variety of μLED geometries.We quantify the transfer yield by counting the missing μLEDs in a randomly selected 1 mm by 1 mm region.For both GaAs and GaN we obtain yields > 99.9% (Fig. 4B left and Fig. S5).If needed, the SU8 adhesion layer can also be left out of the process.For μLEDs transferred onto a bare silicon substrate, the yield is approximately 95% (Fig. 4B, right).In Figs.4C, D, we show high yields for transferring μLEDs of varying sizes and heights.In Fig. 4C, μLEDs with lateral dimensions ranging from 10μm to 100μm are transferred with high alignment accuracy and nearly 100% yield. Figure 4D and Figure S7 show the transfer of μLEDs with heights ranging from 2-9μm.Overall, we show that both thin and relatively thick μLEDs of a variety of lateral dimensions are transferred with high alignment accuracy and yield.
To demonstrate the full capabilities of BLAST and its ability to integrate into an overall process flow, we fabricate a broadband optical upconverter (Figs. 1 and 5) that requires both materials integration and additional processing after transfer.Optoelectronic devices that convert low-frequency incident photons into higher frequency luminescent emission have gained broad interest in fields ranging from bio-sensing and infrared imaging [27][28][29][30][31]. Previous efforts mainly employed two approaches, both relying on the absorption of two photons to create a single photon of higher energy.The first, upconversion nanoparticles [28][29][30], work by nonlinear anti-Stokes emission [32] of two photons through a midgap state associated with a dopant.The second combines two GaAs photodiode junctions and AlGaInP light emitting diode junction [31] in a single vertical GaAs heterostructure stack.
Our micro-upconverter, by contrast, is made by integrating Si photovoltaic cells (PVs) in series with a GaN μLED (Figs.1E, F, and 5).This approach allows separate tuning of the absorber and emitter and an arbitrarily large amount of upconversion to be realized by simply adding more PVs in series.For the devices shown, combining [6][7][8][9][10][11][12] Si PVs in series, each PV generates approximately 0.6 V, and generating 3.6-7.2V, depending on the device.This is sufficient to drive the ~ 4 V threshold voltage GaN μLED (Figs.3B,C) to emit blue light.The process produces thousands of microupconverters per wafer (Fig. 5A) and can explore many different device layouts on a single fab run.This upconverter works for a broad range of excitation energies, from near-infrared to the visible, as shown in Fig. 5B, with the minimum incident photon energy set by the bandgap of the Si (~ 1.1 eV, or 1100 nm).This is in contrast to upconversion nanoparticles, which have relatively narrow absorption spectrum.Furthermore, the output light can reach to the blue.In contrast, tandem upconversion devices have limited emission wavelength because of the narrowly tunable bandgap of AlGaInP material.Overall, the heterogeneous integration approach used here allows us to independently tune the absorption and emission properties without materials constraints.
The BLAST transfer process can be used for a wide variety of complex systems and materials, as shown in Fig. 6 and Fig. S10.Shown in Fig. 6A is the heterogeneous integration of GaAs vertical-cavity surface-emitting lasers (VCSELs) with foundry CMOS circuits.The VCSELs are fabricated on a GaAs heterostructure substrate, and then precisely integrated with CMOS circuits fabricated by a commercial vendor (XFAB-180 nm process).The resulting optical wireless integrated circuits (OWiCs) are powered by light (through the Si PVs).Once activated, each OWiC has programmability (through the integrated circuits) and can communicate to an external reader by VCSEL emitting digital optical signals (Fig. 6C).OWiCs have broad applications in sensing and identification [7,43,44], and their mass-fabrication is made possible by BLAST.
A second example is the aligned transfer 2D van der Waals materials shown in Fig. 6B.
Stacked 2D materials have attracted major interest in the past few years for their unique electronic, thermal, and optical properties [45].Here we show large-scale mass production of stacked graphene with precise spatial control (Fig. S13A).Graphene is grown on a copper host substrate by CVD.It is patterned on copper and then transferred onto a SiO 2 /Si target substrate.This process is then repeated to form the stacked bilayer graphene devices shown in Figs.6B, D. This process should be compatible with any van der Waals material, and makes possible mass manufacture with precise spatial and rotational control.We also show in Fig. S10 the transfer of Si PV devices onto a target glass substrate, relevant for applications in see-through circuitry [18].
We have demonstrated BLAST, a wafer scale transfer technique that can integrate photonic and electronic devices/circuits from different substrates onto a single platform suitable for additional lithographic processing.We showed its use with a variety of native substrates (GaAs, sapphire, SOI, Cu), target substrates (Si, SiO 2 /Si, fused silica, and CMOS circuits on SOI) and optical devices transferred (GaN μLEDs, GaAs μLEDs, Si PVs, VCSELs, and graphene).BLAST is simple and scalable and has the potential to be applied on a vast range of materials systems, helping to make heterogeneous integration a standard fabrication tool in optoelectronic systems.

GaAs μLED fabrication:
The GaAs heterostructure (AlGaAs/GaAs multiple quantum wells, cladding layers, contact layers and AlGaAs sacrificial release layer) used for producing LEDs was epitaxially grown on a 4inch GaAs wafer by a commercial vendor (Matrix Opto.Co., Ltd).Citric acid:H 2 O 2 (20:1) is used to wet etch the heterostructure to expose the n-type GaAs layer.2nm Ti and 9nm Pt are deposited with DC sputtering to form the p-contacts.Ni/Ge/Au (3nm/6.4nm/50nm)are deposited via e-beam evaporation and then annealed at 425℃ for 1min under 20 sccm Ar flow to form the ncontacts.μLEDs' lateral geometry is defined by etching down to the AlGaAs release layer with citric acid:H 2 O 2 (10:1).
GaAs μLED transfer: Prior to transfer, 2μm PMMA (495 PMMA A11, MicroChem) is spin-coated on the μLEDs as the protection layer.10μm PPC (30 wt% in anisole) is spin-coated on a sapphire carrier wafer.Bonding the μLEDs coated by PMMA with the sapphire carrier wafer coated by PPC is carried out by a hot press under the temperature and pressure of 135°C and 1.5bar.The GaAs wafer and sapphire wafer stack is placed into citric acid and hydrogen peroxide mixture (4:1) to each away the GaAs bulk substrate followed by dipping into 100:1 H 2 O:HF to etch away the AlGaAs release layer.
By using an alignment system, the μLEDs are aligned with the target substrate and they are brought into contact, heating up the stack to 100℃.Afterward, we bring the stack to a hot press, keeping pressing at 0.7 bar pressure and 155℃ for 15-30min.We then melt the PPC on a hotplate at 160℃ allowing the removal of the sapphire carrier substrate.In the end, we remove the PPC and PMMA residual in acetone.

GaN μLED fabrication:
The GaN heterostructure used for producing LEDs was either epitaxially grown on a 2inch non-patterned sapphire wafer (for demonstrating 2inch wafer-scale GaN μLED transfer, by University Wafer) or a 4inch patterned sapphire wafer (for fabricating all the other GaN μLEDs in the paper, by Xiamen Powerway Advanced Material Co., Ltd.).Cl 2 based inductively coupled plasma (ICP) etching is employed to expose the n-type GaN layer.The deposition of Pd/Au (50nm/50nm) ncontacts and Ti/Au (25nm/100nm) p-contacts is carried by e-beam evaporation.The contacts are annealed at 660℃ for 1min under Ar environment.μLEDs' geometry is defined by etching down to the sapphire substrate through Cl 2 based ICP etch.Even though PMMA and PPC are not light-sensitive, intense excimer laser light can still burn the polymer layer.To prevent that, we deposit a layer of Cr/Au (50nm/150nm) surrounding the μLEDs as the laser shielding layer.
GaN μLED transfer: We spin ~5μm PMMA (950 PMMA A11, MicroChem) and attach the μLED to a sapphire wafer coated with ~10μm PPC (30 wt% in anisole) using a hot press under the temperature and pressure at 135°C and 1.5bar.Laser lift-off is employed to delaminate the sapphire substrate (193nm ArF excimer laser, beam size: 220μm*220μm; beam energy density: 2000mJ/cm 2 ).The stack is then placed on a 45℃ hotplate to melt the gallium and the sapphire native substrate is thus removed.
Following that, the Ga residual is etched away in HCl:H 2 O(5:1).By using an alignment system, the μLEDs are aligned with the target substrate and they are brought into contact, heating up the stack to 100℃.Afterward, we bring the stack to a hot press, keeping pressing at 0.7 bar pressure and 155℃ for 15-30min.We then melt the PPC on a hotplate at 160℃ allowing the removal of the sapphire carrier substrate.In the end, we remove the PPC and PMMA residual in acetone.

Si PVs fabrication and transfer:
We utilize spin-on glass to dope the SOI substrate's device layer to form PN junction layer.N-contact layer is exposed by HBr based ICP dry etch.PV mesa is outlined by HBr based ICP dry etch.The contacts and interconnects are deposited via DC sputtering of Ti/Pt.The Si PV chip is then coated with 2μm PMMA and bonded to a sapphire carrier wafer.Instead of wet etch and laser lift-off we applied to the μLED substrate removal, we employ Bosch deep reactive-ion etching to remove the bulk silicon substrate, and the etch stops at the SiO 2 BOX layer.
The SiO 2 layer is etched in BOE (6:1).Following that, fused silica substrate is prepared as the target substrate with 500nm SU8 coating.The Si PVs are then attached to the fused silica substrate by hoptree at 155℃.The carrier wafer, PPC and PMMA are subsequently removed as the μLED transfer process.

Graphene patterning and transfer:
Monolayer graphene is grown on copper via a commercial vendor (Grolltex).Ti/Pt alignment marks are deposited on graphene/copper via sputtering.Following that, we pattern the graphene via RIE O 2 plasma etch.The bilayer graphene is formed by aligned transfer with the assistance of the pre-deposited Ti/Pt alignment marks (Fig. S12).
current and light emission as a function of voltage of the μLEDs before and after transfer are shown in Fig 3B(E) for GaAs (GaN), and the spectral characteristics are shown in Fig.3C(F).These characteristics are nearly identical before and after transfer, demonstrating that BLAST does not damage the devices.

Figure
Figure 4A demonstrates the alignment accuracy of BLAST.Complementary alignment marks consisting of crosses and vernier structures were pre-fabricated on the native and target substrates before transfer; every alignment mark on the μLED substrate has a corresponding acceptor alignment mark fabricated on the target Si wafer (Fig. 4A, left).These marks both guide alignment and are used to quantify alignment accuracy (see Materials and Methods).Figure4A(right) shows one such set of alignment marks; Figure 4A (right) shows one such set of alignment marks; examples at multiple locations are shown in Fig. S6.The alignment accuracy is found to be approximately 1μm across the entire chip.

Alignment marks :
There are fine alignment marks to indicate the displacement.Bottom bar array represents the alignment in the x-direction.Left side bar array represents the alignment in the y-direction.When x-direction is perfectly aligned, the donor's and acceptor's central bar pair should be aligned.If the first bar pair on the left (right) is alignment, that means there is +0.5μm (-0.5μm) shift.If the second bar pair on the left (right) is alignment, that means there is +1μm (-1μm) shift, and so on.Based on the same idea, we can tell the alignment in the y direction.