Large-scale on-chip integration of gate-voltage addressable hybrid superconductor-semiconductor quantum wells field effect nano-switch arrays

Stable, reproducible, scalable, addressable, and controllable hybrid superconductor-semiconductor (S-Sm) junctions and switches are key circuit elements and building blocks of gate-based quantum processors. The electrostatic field effect produced by the split gate voltages facilitates the realisation of nano-switches that can control the conductance or current in the hybrid S-Sm circuits based on 2D semiconducting electron systems. Here, we experimentally demonstrate a novel realisation of large-scale scalable, and gate voltage controllable hybrid field effect quantum chips. Each chip contains arrays of split gate field effect hybrid junctions, that work as conductance switches, and are made from In0.75Ga0.25As quantum wells integrated with Nb superconducting electronic circuits. Each hybrid junction in the chip can be controlled and addressed through its corresponding source-drain and two global split gate contact pads that allow switching between their (super)conducting and insulating states. We fabricate a total of 18 quantum chips with 144 field effect hybrid Nb- In0.75Ga0.25As 2DEG-Nb quantum wires and investigate the electrical response, switching voltage (on/off) statistics, quantum yield, and reproducibility of several devices at cryogenic temperatures. The proposed integrated quantum device architecture allows control of individual junctions in a large array on a chip useful for the development of emerging cryogenic nanoelectronics circuits and systems for their potential applications in fault-tolerant quantum technologies.


Introduction:
Split-gate field effect transistors (FETs) consisting of source, drain, and split-gate electrodes are vital in integrated circuits, especially in facilitating energy-efficient high-speed switching in quantum hardware [1,2].Semiconductors such as InGaAs commonly form the channel of a FET and separate the source and drain metal electrodes.A gate dielectric electrically isolates the channel from the split gate electrodes.Therefore, the efficient operation of FETs depends on effective electrostatic coupling between the electric field caused by the split gate voltage and the semiconducting channel [3].A FET function as a conductance switch and operates in three regions.
Replacing the source-drain metal electrodes in conventional FETs with superconducting materials, such as niobium (Nb), will realise efficient and low-power consumption cryogenic logic devices such as field effect controlled superconducting quantum point contacts (SQPCs) and gate-voltage controlled Josephson junctions (Josephson junction transistors or Josephson FETs) [4][5][6][7].Gate-controlled hybrid electronic devices have recently received considerable interest in quantum technology due to their unique technical advantages, e.g., they can work as conductance or current switches in cryogenic quantum circuits [8][9][10] or can be used as an artificial material platform for investigation of Andreev reflection, induced unconventional and topological superconductivity [11][12][13][14][15][16][17][18].Such devices can therefore be engineered and integrated with wafer-scale semiconductor chips to form the building blocks of robust quantum computing systems.For these purposes, (i) high yields, such as the reliability of hybrid junction and quantum device fabrication processes, (ii) reproducibility of quantum phenomena from junction to junction and chip to chip, and (iii) manufacturability of the complex hybrid quantum circuits must be systematically investigated.Such evaluation of hybrid junctions and coherent quantum circuits will inform us if they can be integrated into a scalable architecture for their use in real superconducting quantum hardware.
Here, for the first time, we report successful micro and nanofabrication of large-scale arrays of field-effect hybrid devices on an In0.75Ga0.25As/GaAssemiconducting heterostructure chip.
Our design and fabrication technique bring several advances to the scalable hybrid superconducting-semiconducting quantum circuits for the realisation of cryogenic quantum hardware with complex structures: (i) Our approach in using In0.75Ga0.25Astwo-dimensional electron gases (2DEG), which is located 120 nm below the wafer surface, while is challenging for circuit fabrication, opens up new opportunities for the integration of hybrid quantum circuits with InGaAs based advanced semiconducting electronic integrated circuits (IC).Therefore, the presented work is a considerable step towards realising advanced voltagetunable, low-power cryogenic quantum hardware based on hybrid superconductorsemiconductor electronic circuits.

Hybrid Quantum Chip Micro and Nanofabrication:
The proposed quantum chip is based on In0.75Ga0.25As/GaAsheterostructure as shown in Fig. 1.The In0.75Ga0.25As2DEG with a 30nm thickness is buried 120 nm under the surface.The wafer is first chemically cleaned with Acetone, and IPA, respectively.Usually, an 30s of oxygen plasma ashing is included in the cleaning processes.The fabrication of split-gate hybrid junctions starts with the mesa section in which the 2DEG is isolated with respect to electrodes that are defined later.The PMMA is spin-coated on the wafer as shown in Fig. 1

(e)-(h).
Finally, the gate is defined via Au/Ti thermal evaporation followed by lift-off and a gated junction is fabricated as shown in Figs. 1 (i)-(j).The ohmic contact area is made of gold/germanium/nickel (AuGeNi) to form a low resistance and good chemical bond (adhesion) to the semiconductor substrate.These pads are placed 100 µm away from the junctions to reduce the impact of the normal electrons on the superconducting electrons.The ohmic is etched down to the 2DEG region to perform tunnelling spectroscopy measurements between Nb and 2DEG.For ease of demonstration, only the fabrication process of a single hybrid junction is shown in Fig. 1, however, the design allows wafer-scale nanofabrication.
A total of 144 gate-controllable hybrid S-Sm-S junctions are engineered and patterned on the surface of a semiconducting In0.75Ga0.25As/GaAsheterostructure wafer.Every 72 hybrid junctions are designed to fit across 9 smaller chips of 1 × 1 cm 2 , each small chip containing an array of 8 hybrid double (16 single) interface junctions embedded in superconducting circuits.
The 8 hybrid junctions in each small chip are individually controlled by two global gate pads; one pad is designed to control the left side and the other pad to control the right side of each split gate in the superconducting integrated circuits.Some junctions failed during the fabrication or wire bonding process, and their data are excluded from this study.Figure 2 1.The junction parameters are chosen to be large enough to investigate topological superconductivity in 2D systems [20][21][22] in the future generation of such devices.The geometrical parameters may vary from device to device after nanofabrication, especially for the length and width of the junctions, as the wet etch technique was used to take the unwanted semiconducting heterostructure areas and form source-drain leads and the active 2DEG region in between them.The fabricated junction parameters are commonly shorter than their designed dimensions [13][14][15][16][17][18][19].A depletion layer will form around the gate electrodes by applying a negative gate voltage to the split gates which defines a constriction in the quantum wells between two superconducting leads [23,24].The constriction works as an electron waveguide (conducting quantum channel) in such a 2D electron system in our chips [25].The split gate structure allows modulation of carrier density and mobility of the quantum wells beneath the gate electrodes and in the constriction area of the hybrid junction through the application of gate voltages.When the gate voltage is swept to negative values, the constriction length Lc will reduce from its initial value Lc= 400 nm to Lc= 0 in perfect conditions.Therefore, the split gate is a knob to control the hybrid switches' electronic response.The carrier density and mobility of the In0.75Ga0.25As2DEG in semiconducting heterostructure are defined by Shubnikov-de Haas measurement (see method section).The electron mass of the 2DEG is determined to be m*= 0.039 me, where me is the free electron mass [26].From In0.75Ga0.25As2DEG properties, the coherence length ξN= ћvF/2πkBT≅ 200 nm, and mean free path le=e -1 ћμe (2πns) 1/2 ≅ 2 μm are calculated.Here, vF is the Fermi velocity.Consequently, the hybrid junctions fit into the clean limit regime (le > ξN) with ballistic transports (le >> L) [13].
Figure 3 plots the switching response of eight field effect devices (J1-J8) fabricated in a single chip, with the dimensions given in Table 1.All junctions are measured twice: We observe a relatively good reproducibility for two split gate voltage sweep directions (L and R) for all junctions in this and almost all measured chips.We observe conductance switching with very small hysteresis except for J8 which was purposely designed and fabricated larger than other junctions.This suggests that the quality and uniformity of the hybrid circuit gates, gate pads, and CVD-grown SiO2 dielectric layer under gates used in the chips are of high fabrication qualities.Moreover, the gate voltage leakage and Joule heating in most junctions are negligible or small, so the conductance curves for both sweep directions almost overlap.
Since the distance between the Nb leads (LJ= 3.2 m) is long in J8, hot electrons seem to lead to Joule heating and hysteresis in the junction so the left and right conductance sweeps do not fully overlap, nevertheless, the switching voltage is not affected.The orange and blue areas in Fig. 3 show the hybrid switch ON and OFF states, respectively.Only a small dc switching voltage of Vg= -0.55 V is required to change the hybrid junction from conducting to isolating state.The ON state conductance GON of the junctions varied by the junction's parameters, suggesting that the junctions' dimensions are altered during the fabrication process.
In Fig. 4, the green colour boxes are the data for left (0 to -1 V), and the orange boxes are the data for right (-1 V to 0) gate voltage sweep directions, respectively, with 25-75% data distribution in the boxes.1.5IQR is that 95% of the data points are distributed in the range.
The Median is the middle value of the data distribution.The mean is the average of the data points.Outliers are the data points outside the 1.5IQR.The pinch-off (switching) voltages Vp, and ON (GON) and OFF (GOFF) state conductance values are studied for a large number of chips, and junctions as summarised in Fig. 4.
As shown in Figs. 4 (a) and (b), the average pinch-off voltage Vp for both L and R sweep directions is around -0.56 V for more than 75% of all measured junctions in a large number of chips (note that some junctions are not measured due to failure reasons such as wire-bonding issues or broken contact pads).We observe relatively reproducible and consistent switching response to the electric field induced by the split gates for several measured devices.
This suggests that the next-generation hybrid nano-switches with improved design and performance could be used to control the cryogenic electronic hardware by the application of only -0.56 V or fewer dc voltages.
We also investigated the OFF-sate conductance GOFF of the hybrid junctions in measured chips and plotted them in Fig. 4 (c), and (d).The OFF-state conductance values for the majority of devices are almost zero soon after the application of ~ -0.56 V confirming the uniformity of large scale CVD-grown SiO2 dielectrics on the wafer before dicing and forming the packaged quantum chips.Figure 4 suggests that the majority of the fabricated and measured field effect devices work as an ideal low dissipation switch under the application of split gate electric field in both voltage sweep directions.To analyse the manufacturability of the hybrid junctions we plot the ON state conductance GON for a number of chips as shown in Fig. 4 (e), and (f).We find that GON varies from chip to chip suggesting that the geometrical and interfacial parameters of the hybrid junctions may change during the fabrication process.In order to have a more uniform response attention should be paid to etch process optimisation to improve the hybrid junction interfaces.To be used in quantum circuits and processors, the large-scale manufacturability of hybrid conductance switches depends strongly on their reproducible and identical operational parameters.Here, we further investigate the reproducibility of switching voltage and ON-OFF state conductance parameters for several hybrid devices, both from the same and different chips, under multiple voltage sweeps (more than three times) as shown in Fig. 5.We find that despite slight variation due to fabrication errors, the devices show many repeatable behaviours.
For example, although J1 of chip 2 does not completely pitch off even by the application of a large negative voltage, the conductance traces for six sweeps show slight deviation which could come from Joule heating due to the application of large voltages.The conductance switching failure of this device may be attributed to the formation of a different thickness of SiO2 oxide layer compared to that of other junctions that show very good reproducibility and identical switching parameters (for instance see D8-J3, and D8-J4 & J6 for several sweeps).This nonuniformity may be due to forming of a thicker oxide layer, which prevents the hybrid junction from being completely pinched off and switching off from a conductive to an insulator state.
We further investigate the relationship between the dimensions of gated hybrid junctions and their pinch-off voltages and show the results in Fig. 6.Specifically, the junction length LJ is found to have a slight positive correlation with the pinch-off voltage, with longer junctions requiring a lower voltage to pinch off the channel.
As shown in Fig. 6 (a), this positive correlation may be due to weaker proximity effects in the middle of the longer junctions under the gate, resulting from the extended junction length.
Consequently, less gate perturbation may disturb the induced superconductivity, leading to an earlier pinch off of the channel.However, more data is needed to draw definitive conclusions about this relationship.In contrast, no obvious correlation is observed for constriction width Wc.In theory, the width determines the length of the quasi-1D/1D channel, and if this length is much smaller than the scattering length/mean free path, the channel remains in the ballistic regime.Further theoretical analysis and simulations are needed to confirm this hypothesis.
This will also motivate us to study these devices at lower temperatures to properly form the 1D channels.As these studies are not the focus of the present work will be discussed elsewhere.
In Table 2, we summarise the yield with respect to the junction and constriction dimensions.Most of the non-switching junction with small Wc shows negligible conductance at zero gate bias, which may be due to the surface charge accumulation under the split gates that are enough to pinch off the channel without extra gate bias or due to the electron leak into the gate rather than transport from source to drain.We observe a total yield of 74.24%, which counts for the working switches divided by the total number of measured devices, for a large array of hybrid devices as shown in Table 3.This includes yield for reproducibility of the conductance of individual hybrid switches when their split gates voltage is swept from 0 to -1V and then reversed from -1V to 0.

Conclusion:
We reported the first successful micro and nanofabrication of a large array of chip-integrated hybrid field effect quantum nanoelectronics devices and demonstrated a systematic experimental investigation of their conductance switching performance under the application of gate electric fields.We demonstrated techniques for the successful fabrication of novel cryogenic gate voltage addressable nanoelectronics chips with negligible gate voltage leakage and with high switching response statistics, reproducibility rate, and quantum yields.We found that to make efficient cryogenic switches, the attention should especially be on the quality junction geometrical and interfacial parameters as the former influence the uniform switching voltages and the latter have a direct effect on the ON-OFF state conductance.The OFF state conductance is also a function of the quality oxide layers isolating the source-drain electrodes of hybrid junctions from split gate electrodes.The techniques and experimental data presented here show that our field effect nano-switch devices, with modified designs and fabrication strategy, may help the development of novel cryogenic electronic switches for various classical or quantum cryogenic applications.
Moreover, the ability to tune the indium composition permits the formation of highly transmissive metal-semiconductor interfaces.(ii) Our superconducting materials have not been sputtered in the same chamber as the semiconducting wafers making the quantum circuit fabrication accessible, and user friendly as in situ deposition of superconducting and semiconducting films are expensive and out of the capability and affordability of most research groups.(iii) Using Nb, as a type II superconductor with a larger superconducting gap and higher transition temperature compared to commonly used in-situ fabricated Al-based circuits, allows the operation of hybrid quantum circuits at relatively high magnetic fields and high frequency making them compatible which most emerging quantum circuit platforms based on superconducting microwave coplanar waveguide resonators and circuit quantum electrodynamic systems.In fact, making high-quality Nb-2DEG interfaces, especially in large arrays, are much more challenging than Al-based hybrid interfaces, because of the nature of Nb-based hybrid interfaces, which we successfully overcome here.Our advanced techniques used in this work will help open up a new route towards the development of Nb-based hybrid quantum circuits.(iv) For the first time, we fabricated a hybrid quantum IC on a large scale that is addressable and controllable with voltage signals, that is robust again noise compared to current biased circuits, in a compound material platform with a complex design and fabrication process compatible with the most advanced semiconducting ICs.(v) The interesting properties of InxGa1−xAs 2DEG, such as low electron effective mass, large g-factor, and strong Rashba spin-orbit coupling, make them a very attractive material platform for applications in electronics, spintronics, and photonics topological quantum computing.

Figure 1 .
Figure 1.Hybrid superconductor-semiconductor quantum chip fabrication process: The schematic demonstration of a semiconducting wafer based on InGaAs/GaAs heterostructure is shown in the centre.The 2DEG is a 30 nm thick In0.75Ga0.25Asquantum well located 120nm beneath the surface.(a) PMMA spin-coated on the wafer.(b) Ebeam patterning is performed, and PMMA is developed to form the pattern.(c) Chemical wet etching to remove the layers above the 2DEG.(d) Nb is sputtered on the etched area of the wafer.(e) The Nb is lift-off, and the junction is formed.(f) A 50 nm thick SiO2 oxide layer grown by chemical vapour deposition (CVD).(g) PMMA spin-coated.(h) Ebeam patterning and developing.(i) Au/Ti is thermally evaporated on the PMMA pattern.(j) The final step for a gated device fabrication after the lift-off of Au/Ti.
(a), and e-beam patterning is performed to define the superconducting electrode pads which are Nb in this work as shown in Fig 1(b).A chemical wet etching (see Fig. 1 (c)) followed by the formation of the 2DEG channel is performed before the Nb sputtering (Fig. 1 (d)), to form the hybrid Nb-2DEG-Nb junction as shown in Fig. 1 (e).The chemical wet etchant is H2SO4:H2O2:H2O= 1:8:1000 with a typical etching rate of 1nm/s.Afterwards, a 50nm SiOx oxide layer grown via Chemical Vapour Deposition (CVD) is used to isolate the junction as shown as a transparent blue layer in Fig. 1 (f).Extra Buffered Hydrofluoric acid will open the window for electrodes.Then another PMMA e-beam pattern is performed to define the split gate as shown in Figs. 1

Fig. 2
Fig. 2 Gate voltage addressable hybrid quantum chip: (a) The false-coloured optical image of a chip containing large-scale integration of hybrid semiconductor-superconductor junctions, before the final fabrication stages.The chip contains a total of 72 double interfaces (Nb-2DEG-Nb) and 144 single interfaces (Nb-2DEG or 2DEG-Nb) junctions.(b) A packaged addressable field effect quantum chip containing the chip shown in (c) after wirebonding to a leadless chip carrier (LCC).The chip is mounted in the cold finger of a cryostat or dilution refrigerator for the sub-Kelvin cryogenic test.(c) The false-coloured optical image of the addressable hybrid quantum chip containing an array of hybrid junctions made from superconducting Nb and high-quality In0.75Ga0.25Astwo-dimensional electron gas (2DEG) in In0.75Al0.25As/GaAsheterostructure.Each junction in the chip can be addressed by applying voltages through two universal gate pads which are coloured yellow and orange.The ohmic contacts, shown with cyan pads, are etched down to the 2DEG region, for the purpose of tunnelling measurements between Nb and 2DEG (the data is not shown here).The area between Nb and ohmic pads is all etched away except the active area where hybrid junctions are formed (mesa area).(d) The false-coloured SEM image of one gate-voltage controlled hybrid symmetric and planar 2D junction on the quantum chip.(e) The dashed-red rectangle area in (d) is enlarged showing the splitgates area with a constriction width Wc and length Lc made from Au.A 50 nm thick SiO2 dielectric was deposited to isolate the gates from the source-drain electrodes of the junctions.(f) Schematic illustration of a field effect hybrid switch from the side view with detailed semiconducting heterostructure nanolayers.The 30 nm In0.75Ga0.25As2DEG is shown in red.
(a)    shows the false-coloured optical image of a large-scale hybrid quantum chip before the final fabrication stages and dicing.The chip contains a total of 72 double interfaces (Nb-2DEG-Nb) junctions or 144 single interfaces (Nb-2DEG or 2DEG-Nb) junctions in a 1 × 1 cm 2 dimension.

Figure 2 (
Figure 2 (b) shows a packaged addressable quantum chip containing the structure shown in (i) the split gate voltage Vg is swept from Vg= 0 to -1V (shown in black solid lines), and (ii) Vg is returned from Vg= -1V to 0 (shown in red solid lines).This measurement aims (i) to study the reproducibility of the conductance switching of each junction for two different sweep directions.(ii) to investigate the reproducibility of conductance switching in junctions of various dimensions (but similar geometry) in a single chip.

Figure 3 .
Figure 3.The conductance as a function of the electric field on the gates for eight (all) junctions in a single chip, measured at T= 4K.(a) J1, (b) J2, (c) J3, (d) J4, (e) J5, (f) J6, (g) J7, and (h) J8.There are two sweep directions from 0 to -1 V (black) and then from -1 V to 0 (red).Relatively good reproducibility of both effects are observed for all junctions in this chip.

Figure 4 .
Figure 4. Switching (pinch-off) voltage of all measured chips (a), each with eight junctions (b) for different sweeping directions measured at T= 4K. Green colour boxes are the data for left sweeping gate voltage (0 to -1 V) and the orange boxes are the data for right sweeping gate voltage (-1 V to 0).(c) On-state conductance Gon for all the measured chips, shown as C or D, each with eight junctions (d) measured at T= 4K.On-state refers to the height of the conductance at zero gate voltage.(e) Off-state conductance Goff for all the measured chips, each with eight junctions (f) measured at T= 4K.

Figure 5 .
Figure 5.The conductance as a function of the electric field on the gates for devices with multiple sweeps to examine the reproducibility of the switching voltage, ON and OFF states conductance.

Figure 6 .
Figure 6.Pinch-off voltage Vp as a function of junction length LJ. Green colour is the data for left sweeping gate voltage (0 to -1V), and the orange boxes are the data for right sweeping gate voltage (-1 to 0V).The data for chip 5 and chip 6 is absent.1.5IQR is that 95% of the data points are distributed in the range.25%-75% means 25-75% of data are in the box.The median is the middle value of the data distribution.Mean is the average of the data points.Outliers are the data points outside the 1.5IQR.(b) Pinch-off (switching) voltage Vp as a function of constriction width Wc.

Table 1 .
The designed geometrical parameters of eight hybrid field effect switches integrated into a single quantum chip.
WJ (m) The constriction width Wc varies from 400 nm to 100 nm with fixed junction length LJ= 1.4 μm.As another control knob, junctions with Wc= 100 nm and LJ= 3.2 μm are fabricated to study the effects of the longer junctions.Such devices are found to show the minimum ON state conductance as discussed above and therefore offer the lowest yield.A slight reduction in quantum yield is observed with decreasing constriction width Wc.

Table 2 .
Junction length LJ and constriction width Wc correlated quantum yield.The yield is subdivided into different junction lengths and constriction sizes.The table sorts total switching devices versus measured devices with the specific size.

Table 3 .
Two sets of measured devices are labelled with 'C' and 'D'.The quantum yield counts for the working hybrid switch devices (showing switching response when the split gate voltage is swept to negative values) are divided by the total number of measured hybrid devices.