Omega‐Gate Silicon Nanowire Geometric Diodes with Reconfigurable Self‐Switching Operation and THz Rectification

Geometric diodes (GDs) represent a relatively unconventional class of diode that produces an asymmetric current response through carrier transport in an asymmetric geometry. Synthesized from the bottom up, Si nanowire‐based GDs are three‐dimensional, cylindrically symmetric nanoscale versions capable of room‐temperature rectification at GHz‐THz frequencies with near zero‐bias turn‐on voltages. Here, by fabricating three‐terminal n‐type Si nanowire GDs with axial contacts and an omega‐gate electrode, a distinct class of reconfigurable self‐switching geometric diodes (SSGDs) is reported. Single‐nanowire SSGD device measurements demonstrate a significant dependence of diode current and polarity on gate potential, where the diode polarity reverses at a gate potential of ≈−1 V under specific grounding conditions. Finite‐element modeling reproduces the experimental results and reveals that the gate potential—in combination with the morphology and dopant profile—produces an asymmetric potential along the nanowire axis that changes asymmetrically with axial bias, altering the effective conductive channel within the nanowire to yield diode behavior. The self‐switching effect is retained in two‐terminal SSGD devices, and modeling demonstrates that both three‐terminal and two‐terminal devices support rectification through THz frequencies. The results reveal a new mechanism of operation for nanowire‐based GDs and characterize a new type of self‐switching diode with reconfigurable polarity.


Introduction
Geometric diodes (GDs) use noncentrosymmetric structures to induce an asymmetric, nonlinear current response to an applied potential. [1,2]They can be realized in the form of ballistic rectifiers that rely on specular reflection of ballistic or quasi-ballistic Semiconductor nanowires (NWs) have also been explored as a platform for the development of nanoscale diodes.Si NWs, which can be synthesized with precise dopant and morphological control using a vapor-liquid-solid (VLS) bottom-up growth process, [33,34] have been developed as p-n junctions, [35][36][37][38] Schottky diodes, [39,40] and quasi-ballistic GDs. [2,41]As illustrated in Figure 1B, Si NW GDs are cylindrical single-crystal nanostructures encoded with asymmetric dopant profiles (e.g., Figure S1, Supporting Information) that are used to fabricate a "sawtooth" morphology via dopant-dependent wet-chemical etching.By fabricating Ohmic axial contacts to degenerately doped regions surrounding the sawtooth segment of single NWs, GD performance can be evaluated by measuring the two-terminal direct current (DC) current-voltage (I-V) characteristics under an applied potential (V app ).The devices demonstrate an asymmetric current response at room temperature with a well-defined diode polarity, as shown by the exemplary I-V characteristic in Figure 1C.Prior work showed rectification at frequencies through at least 40 GHz; however, based on a quasi-ballistic operational mechanism, Si NW GDs can theoretically rectify up to THz frequencies. [2]ere, as illustrated in Figure 1D, we fabricate a 3D omegagate on Si NW GDs to examine their diode performance as a function of an applied gate potential (V g ).Omega-gate electrodes are relatively typical for field-effect transistors (FETs), [42,43] and NW GDs with gate electrodes resemble an FET device except for the asymmetric dopant profile and morphology.However, we find that the operation of the device is distinct from the operation of a typical FET because the I-V characteristics show strong nonlinear diode behavior with an effective diode polarity that depends on the magnitude, sign, and grounding configuration of the electrodes.[46][47][48] Moreover, the operation is distinct from two-terminal NW GD devices without the gate electrode, because the diode effect originates from changes in the conduc-tive channel through the NW due to depletion caused by the gate electrode.
We show that the gated NW GD devices are best classified as reconfigurable self-switching geometric diodes (SSGDs).Although the geometry of these Si NW-based SSGDs is distinct from the planar devices shown in Figure 1A, we demonstrate through a combination of experiment and finite-element (FE) modeling that the operational mechanism is the same.In addition, we show the conditions under which the diode polarity reverses, allowing reconfiguration of the device via a change to the gate potential.Reconfigurable electronic elements, including NW-based devices, [39,40] have received attention for their capacity to enable dynamic circuits that can adapt to provide the needed logic functions for a given application. [49]Thus, the report herein of Si NW SSGDs represents an alternative design for compact self-switching devices with the potential THz applications that can be reconfigured as needed for targeted applications.

NW SSGD Fabrication and Transport Measurements
As shown by the scanning electron microscopy (SEM) image in Figure 2A, single-NW devices with four axial contacts (two cathodic, two anodic) and one gate electrode were fabricated to test the performance of the devices.In brief, after transfer to device substrates, Si NWs were wet-chemically etched to reveal the asymmetric geometry, and a first step of lithography was performed to define axial contacts.Subsequently, an ≈15 nm AlO x film was deposited by atomic layer deposition (ALD) to serve as a gate dielectric, and the gate electrode was fabricated by a second lithographic step.Through this process, NW GDs with omega-gate and gate-all-around structures can be fabricated.Given the cylindrical sawtooth geometry of the NW GD, the NW constriction is typically suspended over the device substrate by 20-60 nm.Therefore, with the deposition of the gate dielectric with ALD and the gate contact metal with electron-beam evaporation, the gate dielectric consistently wraps around the NW constriction, and we expect the gate contact metal either full wraps around the NW constriction or forms an omega shape based on the size of the NW constriction.Although only two axial contacts were needed for diode measurements, the additional contacts were used to verify that all contacts were Ohmic.
Diode I-V characteristics were typically obtained by sweeping V app across the diode from −1 to 1 V at a constant V g .As shown in Figure 2B, two electrical grounding configurations, denoted 1 and 2, were used in which either the "short" side of the sawtooth or "long" side of the sawtooth, respectively, were connected to electrical ground, with V app applied against the opposite side.These configurations led to four biasing conditions, denoted 1 + , 1 − , 2 + , and 2 − , at which the current is evaluated, where the + and -refer to V app >0 and V app <0, respectively.To interpret diode performance and polarity, we define the DC asymmetry, , as where I is the measured current, m = 1 or 2 corresponds to the grounding configuration of the measurement, and  is calculated for |V app | = 1 V unless noted otherwise.As displayed in Figure 2C, I-V characteristics were measured before and after fabrication of the gate dielectric and electrode.Measured in grounding configuration 1, I increase by two orders of magnitude after gate fabrication (with an electrically floating gate), while  stays roughly constant.The change in I after gate fabrication likely results from the interface states that form at the Si/AlO x interface and the effective work function difference between the Si NW and the Pd used for the metal contact.NW devices were characterized with V g ranging from −3 to 3 V, and changes to the magnitude of the current, |I(V app )|, at V app = ±1 V and the magnitude of  are shown in Figure 2D,E, respectively, for each biasing condition.Note that we do not observe clear, systematic hysteresis in these measurements.The results in Figure 2D are analogous to FET transfer characteristics, yet the results exhibit significant diode behavior.The value of V g has a significant impact on both |I(V app )| and .Increasingly negative V g decreases |I(V app )| by two to four orders of magnitude, which is a general trend that would be expected from n-type devices under negative gate bias.However, both the gate configuration and the sign of V app substantially affect the exact values of the current, and three regimes are apparent: a maximum current plateau at positive V g (green region), a transition regime where current changes by orders of magnitude (yellow region), and a minimum current plateau at negative V g (gray region).Figure S2 (Supporting Information) illustrates this current response as a function of V g and V app , analogous to FET output characteristics, for the three regimes.
The maximum current plateau regime spans from V g ≈ 1.7-3.0V, exhibiting similar and constant maximum measured values of |I(V app )| for all biasing conditions.In the minimum current plateau regime spanning from V g = −3 to −1.7 V, all biasing conditions result in constant minimum measured values of |I(V app )|; however, the pairs 1 − /2 + and 1 + /2 − plateau to different minimum values of ≈2.3 × 10 −8 A and ≈1.5 × 10 −9 A, respectively.In the current transition regime from V g = −1.7 to 1.7 V, each biasing condition has a distinct trend as the current changes from its maximum to minimum value.As shown in Figure 2E, the changes in |I(V app )| with V g also lead to substantial changes in magnitude and sign of  with substantial differences between grounding configurations 1 and 2. In the maximum current regime, both grounding configurations approach  = 1.In the minimum current regime, configurations 1 and 2 converge to  values of 0.062 and 16, values which are approximate reciprocals of one another.In the current transition regime, as V g decreases,  decreases from ≈1 to a minimum value at V g ≈ −0.5 V, where 1 and 2 produce values of 0.0025 and 0.042, respectively.At even more negative V g , the  for both 1 and 2 increases.Interestingly, the value for  of configuration 2 passes through  = 1 at V g ≈ −1 V, reflecting a reversal of the diode polarity.For all measurements, configuration 2 with V g < -1 V was the only condition under which |I(+1 V)| > |I(−1 V)|, yielding  >1. Figure 2F shows I-V curves for configuration 2 at V g values above, at, and below the point of reversal, highlighting the switching of the diode polarity.

FE Modeling of NW SSGDs
To reveal the origin of the trends in current and , as well as the general mechanism of asymmetric response in these gated devices, we used FE modeling to probe the electrical characteristics of the Si NW GDs.For computational efficiency, we have modeled the gated Si NW GD devices using cylindrical symmetry, which corresponds to a gate-all-around structure.By applying the geometry and dopant profile of the Si NW device reported in Figure 2, the model reproduces the general behavior and polarity reversal observed in experimental measurements.Figure 3A,B display |I(V app )| and , respectively, for the four biasing conditions, qualitatively reproducing the three regimes of current response observed in the experimental data.Quantitatively, compared to experiment, the simulations show higher current in the maximum current plateau regime and greater asymmetry in the current transition regime but reproduce the minimum current plateau reasonably well.We also observe a difference in the slope of the current within the current transition regime, as FE simulations predict comparable slopes for all bias conditions yet the experimental results demonstrate steeper slopes for the 1 + and 2 − bias conditions.This difference, where more current is measured in the 1 − and 2 + bias conditions, is consistent with ballistic transport serving to enhance the current under these bias conditions, as expected from our prior reports on Si NW GDs without a gate electrode. [2,50]Figure S3 (Supporting Information) shows the simulated current response as a function of V g and V app for these three regimes.
To better understand the origin of the behavior, we examine the electron concentration (n) in Figure 3C and electrostatic potential () in Figure 3D at select potentials, V g = 5, −0.7, and 5 V, chosen to coincide with the current maximum, transition, and minimum regimes, respectively.As apparent from Figure 3C, the mechanism of current asymmetry arises from electron depletion close to the NW constriction, an effect caused by the smaller diameter and lower dopant concentration that cause this region to be highly sensitive to changes in V g .At the current maximum (V g = 5 V), there is no depletion, and all bias conditions have the same high n throughout the sawtooth.In the transition regime at the V g = −0.7 V, depletion is evident for all bias conditions, with maximum electron depletion around the NW constriction.However, bias conditions 1 + and 2 + have greater electron depletion than bias conditions 1 − and 2 − , with more dramatic changes between positive and negative biases for grounding configuration 1 than grounding configuration 2. At the current minimum (V g = −5 V), the depletion effect has plateaued, and bias conditions 1 − and 2 + and bias conditions 2 − and 1 + display approximately the same results.For V g = −0.7 and −5 V, there is one bias condition for each grounding configuration that produces the largest conductive channel, thereby defining the effective forward bias condition of the diode with the highest current for that configuration.For configuration 1, the forward bias for both V g = −0.7 and −5 V is produced with V app < 0 V (denoted 1 − ).For 2, however, forward bias at V g = −0.7 is produced with V app < 0 V (denoted 2 − ) whereas forward bias at V g = −5 V is produced with V app > 0 V (denoted 2 + ).This change in the forward bias condition reflects the reversal of the diode polarity.
The origin of the diode behavior can also be interpreted in terms of the potential (Figure 3D) and barrier in the energetic potential (E = −e, where e is elementary charge) that forms along the NW axis.As illustrated in Figure 3E, the energetic potential barrier tends to have a maximum around the constriction, consistent with depletion in this region.The barrier varies with V app , exhibiting lower values under forward bias versus reverse bias conditions, consistent with an asymmetric biasinduced barrier-lowering mechanism. [48]As shown in Figure 3F, the potential barrier also varies with V g .There is no potential barrier at V g = 5 V for all bias conditions.At V g = −0.7 V, there is an energetic potential barrier along the NW axis in all bias conditions, with a maximum barrier height around the NW constriction.Notably, bias conditions 1 + and 2 + have greater potential barrier heights than bias conditions 1 − and 2 − , with more asymmetry in grounding configuration 1 than in grounding configuration 2. At V g = −5 V, bias conditions 1 − and 2 + and bias conditions 2 − and 1 + reach the same maximum potential barriers.Just as there is an asymmetric depletion response to applied bias, there is a corresponding asymmetric barrier response, causing the diode effect.The value of V g at which the barrier heights are equal in bias conditions 2 − and 2 + is the same value at which the currents are equal for bias conditions 2 − and 2 + in Figure 3A.V app = ±1 V; background shading corresponds to ≈V g ranges corresponding to a maximum current plateau (green), current transition (yellow), and minimum current plateau (gray).B)  as a function of V g for grounding configurations 1 (purple) and 2 (orange) at V app = ±1 V with a dashed line at  = 1.C) Electron concentration, n, in the NW for V g = −5, −0.7, and 5 V for grounding configurations 1 and 2, scale bar, 150 nm.D) Electrostatic potential, , for V g = −5, −0.7, and 5 V for grounding configurations 1 and 2 with V app = ±1 V, scale bar, 150 nm; the black outlines define the interface between the NW and AlO x layer.E) Energetic potential, E, as a function of axial position (bottommost z-axis) for V g = −0.7 and V app = 1 V (blue), 0 V (gray, labeled 1 0 ), and −1 V (red) for grounding configuration 1. Axial positions of the NW constriction and end points of the short and long side tapers are denoted 0, l, and L, respectively.Inset illustrations show Fermi-Dirac distributions, f(E), partially colored green and red for electrons with and without, respectively, sufficient energy to transmit over the potential barrier within the sawtooth geometry.F) Potential barrier height as a function of V g for grounding configurations 1 and 2 with V app = ±1 V.

Comparison Between Planar and NW Self-Switching Devices
The asymmetric current response originating from the asymmetric depletion of a channel and changes in barrier height under different applied bias conditions is a characteristic mechanism of SSDs.While omega-gate NW GDs are not fabricated with etched channels like traditional SSDs (Figure 1A), they still provide an asymmetric channel for carrier transport with asymmetric depletion and potential barrier lowering in response to applied bias.Figure 4A compares FE simulation results of n for an n-type traditional geometry SSD device based on a SOI SSD device [10] and our n-type Si NW SSGD device, highlighting the characteristic SSD mechanism in both devices under zero, forward, and reverse biases.In both devices, there is an asymmetric channel that has a greater effective width under forward bias than reverse bias.One difference is that maximum depletion is observed under reverse bias for the planar SSD and under zero bias for the SSGD, although the SSGD trend is consistent with "V-shaped" SSDs [25] and planar barrier diodes. [51,52]In addition, the magnitude of depletion between the two devices differs by ≈4 orders of magnitude, as apparent by a comparison of the color bar axis limits in Figure 4A.This difference originates from the modulated dopant profile in the SSGD compared to the uniform dopant profile in the planar SSD, causing the NW SSGD to have a greater A) Electron concentration, n, under zero (V app = 0 V), forward (V app = −1 V), and reverse (V app = 1 V) biases applied to the righthand side of an n-type Si SOI SSD device [10] (left; scale bar, 1 μm) and an n-type Si NW SSGD device (right; scale bar, 150 nm) in grounding configuration 1 at V g = −0.7 V. B) Semi-logarithmic I-V curves for the NW SSGD device (yellow) corresponding to the structures in panel A and planar SSD device (black) assuming a Si thickness of 205 nm.C) Electron concentration, n, for NW SSGD devices with uniform physical geometry but asymmetric dopant profile (left) and asymmetric physical geometry but uniform dopant concentration of 10 17 cm −3 (right).On left, V g = 1.4 V whereas on the right, V g = 0.9 V; scale bars, 150 nm.magnitude of n within the channel for carrier transport under forward bias.I-V characteristics in Figure 4B demonstrate a significantly greater forward bias current and current asymmetry for the SSGD device, highlighting a potential advantage over a planar SSD.
To better understand the importance of asymmetry in geometry versus asymmetry in dopant profile, FE simulations were performed for SSGD devices in which, first, the NW dopant profile is asymmetric while the physical geometry is uniform (diam-eter 50 nm), and second, the physical geometry is asymmetric and the dopant concentration is uniform (10 17 cm −3 ).We note that the former structure (with a smaller NW diameter than used in experiments herein) could be synthesized by the VLS process while the latter could not.Interestingly, both structures exhibit an SSGD effect.Figure 4C displays plots of electron concentration for both structures in both grounding configurations for values of V g that produce  = 30 at V app = ±1 V, and it is apparent that there is still an asymmetric channel that has a greater effective width under forward bias (1 − and 2 − ) than reverse bias (1 + and 2 + ).However, for a given , the uniform physical geometry and uniform dopant profile structures produce, respectively, 2.0 and 6.5 times less forward bias current than the analogous NWs with asymmetric physical geometry and asymmetric dopant profile.Thus, the combination of asymmetric physical geometry and dopant profile serves to maximize the diode performance, where the constriction with a small diameter and low dopant concentration influences diode behavior while the degenerately doped sections with a larger diameter primarily influence the net current flow.

Two-Terminal SSGD Devices
To simplify Si NW SSGD devices, we discuss two strategies to configure the devices to function with only two terminals.Our first approach considers the gating effect arising from the surface charge density of surface trap states in an ungated Si NW GD device.Previously, an alternate Si NW GD operational mechanism was proposed in which a high surface charge density on the NW produces a significant potential barrier through the sawtooth geometry that is asymmetrically lowered in response to source-drain bias, producing an asymmetric current response. [48]he effect was described as asymmetric bias-induced barrier lowering, [48] consistent with the mechanism in operation for the omega-gate devices.The Si/SiO 2 interface of typical NW GDs is a site for a variety of structural, chemical, and electrostatic phenomena including surface roughness scattering, fixed charge densities, band bending from Fermi level pinning, and surface trap recombination. [53]Thus, we also consider an ungated Si NW GD where the effect of surface trap states is modeled as a constant surface charge density calculated from a given trap density (N T ). Figure 5A compares the n spatial distributions for the gated simulations and ungated simulations at different N T .For select N T values ranging from 10 11 to 10 13 cm −2 in the ungated simulations, we find that across all biasing conditions, the depletion effects observed in the n distribution are analogous to the results for V g ranging from −3.0 to 1.5 V from gated simulations.
Figure 5B,C display |I(V app )| and , respectively, as a function of N T for the four biasing conditions.Analogous to V g , the value of N T has a significant impact on both quantities.Notably, bias conditions 1 − and 2 − produce the same |I(V app )| results as bias conditions 2 + and 1 + , respectively, leading to an inverse relationship between  for grounding configurations 1 and 2. This equivalence is expected because, in the absence of a gate electrode, only the potential difference between the axial contacts determines the device response.Compared to gated experiments and simulation results, ungated simulations show a sharper peak in  in the current transition regime and lesser asymmetry in the minimum current plateau regime, but they qualitatively reproduce the three current response regimes.As illustrated in Figure 5D, the potential barrier height also varies with N T and displays a similar relationship to |I(V app )| as observed in gated simulations.Thus, in ungated Si NW GDs with sufficiently large surface trap densities, the self-switching effect can produce significant diode behavior in two-terminal SSGDs, directly analogous to the gated NWs.
An additional method to create a two-terminal device involves reconfiguring the three-terminal omega-gate Si NW SSGD by electrically shorting the gate electrode with one of the two axial contacts, as illustrated in Figure 6A.In this two-terminal, gated configuration, one electrode serves as a contact to both the gated sawtooth segment and an adjacent degenerately doped ntype region.This configuration was tested experimentally, and Figure 6B,C compare the results for |I(V app )| and , respectively, from two-terminal gate configurations 1 and 2. Both configurations demonstrate large |I(V app )| values and  values that increase from ≈1 to ≈10 with increasing |V app |.Plots of the spatial distribution of n (Figure 6D) confirm that the same self-switching effect, causing depletion around the sawtooth geometry, is retained in the two-terminal gated SSGD.The plots for V app = ±0.1 V show minimal difference in n depletion between the biasing conditions of grounding configurations 1 and 2, which is consistent with  values close to 1.However, at V app = ±1 V, there is a clear asymmetry in electron depletion between 1 − and 1 + and an even greater difference between 2 − and 2 + , also consistent with larger  val-ues for both grounding configurations at larger V app and consistent with more current asymmetry for grounding configuration 2. The FE simulations for |I(V app )| and  in Figure 6E,F, respectively, qualitatively reproduce the behavior observed experimentally.The results demonstrate that configuration 2 is more ideal in terms of maximizing both DC asymmetry and forward bias current.

THz Rectification
Using FE simulations, we consider the frequency response of the omega-gate NW-based SSGDs.Previous simulations support THz rectification in ungated NW GDs based on the asymmetric bias-induced barrier-lowering mechanism. [48]Figure 7A shows the alternating current (AC) sinusoidal input voltage signal (amplitude of 1 V at 1 THz) and the corresponding current response of the SSGD, demonstrating rectification with an AC asymmetry value ( AC ) value of ≈15, as calculated by dividing the maximum positive by the minimum negative current magnitudes during a cycle.Figure 7B displays  AC for three-terminal SSGD devices with gate potentials of V g = −0.6,−0.2, and 0.2 V, and input AC frequencies of 0.1 GHz to 10 THz.These results demonstrate the tunability of  AC and cutoff frequency (f c ) with V g , with f c increasing and  AC decreasing with increasing V g .The plateau value of  AC at lower f exhibits behavior similar to the dependency of  on V g as shown in Figure 2E.In addition, Figure 7C shows that two-terminal gated SSGDs are also capable of rectification through THz frequencies.

Conclusion
In this work, we report omega-gate electrodes on Si NW GDs, elucidating the effects of surface potential and band bending on diode behavior.We observe that surface gate potential significantly impacts the magnitude of current flowing through the device and the magnitude and direction of current asymmetry, permitting the identification of three regimes of diode response with respect to gate potential.Through FE modeling, we reproduce these regimes, revealing that the devices function via a selfswitching effect and are best classified as SSGDs.Interestingly, the asymmetric current response is tunable via gate potential and grounding configuration, allowing the diode polarity to be reconfigured simply with the gate potential.We find the SSGD effect is maximized by having both an asymmetric NW physical geometry and an asymmetric dopant profile.Although fabrication of asymmetric gate contacts might be able to achieve similar effects, [47] the bottom-up VLS growth process that encodes the requisite asymmetry during NW synthesis facilitates a simple fabrication process and device structure.Moreover, we demonstrate a twoterminal SSGD device and use simulations to demonstrate a capacity for rectification through THz frequencies.The NW-based SSGDs developed in this work thus represent a new type of SSD with diverse potential applications for both reconfigurable electronics and THz applications.

Experimental Section
NW Synthesis and Etching: Si NWs were synthesized by a VLS mechanism in a home-built, hot-wall chemical vapor deposition (CVD) system. [33]Au nanoparticles were used as catalysts, silane (SiH 4 ; Air Liquide) as the source of Si, phosphine (PH 3 ; 1000 ppm PH 3 in H 2 ; Air Liquide) as the source of P for n-type doping, and hydrogen (H 2 ; Matheson TriGas 5 N semiconductor grade) as the carrier gas.Growth substrates were prepared by distributing citrate-stabilized 150 nm diameter Au catalysts (Ted Pella) on 1 × 2 cm Si wafers (NOVA Electronic Materials, (100) p-type Si with 600 nm thermal oxide) that had been functionalized with poly-L-lysine (Sigma-Aldrich).These growth substrates were then inserted into the center of a single-zone 1-inch tube furnace (Lindberg BlueM).NWs were nucleated at 440-450 °C for 15 min with 200 standard cubic centimeters per minute (sccm) H 2 and 2.00 sccm SiH 4 at 40 torr total reactor pressure.Following nucleation, the PH 3 flow was set to 20 sccm, the temperature was ramped to 420 °C over 15 min, the total reactor pressure was ramped to 20 torr and the H 2 flow was ramped to 100 sccm over 1 min.The PH 3 flow of 20 sccm was then maintained for 60 min to grow a degenerately doped n-type section.The sawtooth geometry was encoded in the NW by controllably ramping the PH 3 flow from 20 to 0 sccm in steps with a duration of 3 s or more each after which the flow rate was held at 0 sccm for 15 s to create the long side of the sawtooth; next, the PH 3 flow rate was abruptly returned to 20 sccm to create the short side of the sawtooth.The PH 3 flow was again maintained at 20 sccm for 60 min to encode a second degenerately doped n-type section.The minimum doping level in the sawtooth section, near the constriction, is likely below 10 18 cm −3 due to suppression of the reservoir effect. [34,54,55]To achieve the desired NW morphology, NWs were mechanically dry transferred to device substrates after growth and were etched in buffered hydrofluoric acid (BHF, ≈5% by volume) for ≈10 s to remove the surface oxide and room-temperature aqueous KOH solution (20% by weight) for 120-240 s.
Device Fabrication: Device substrates (NOVA Electronic Materials, (100) p-type Si with 100 nm of thermal oxide, 200 nm Si 3 N 4 ) were prepared by defining a marker pattern using electron-beam lithography (EBL) with an electron-beam resist consisting of three layers of methyl methacrylate (MMA; MicroChem (8.5) EL9) and one layer of poly(methyl methacrylate) (PMMA; MicroChem 950PMMA.A7) and deep reactive ion etching (DRIE; Alcatel AMS 100) to etch the patterns into the substrate dielectric layers.After NW transfer onto substrates and NW etching, metal contacts were defined using EBL with a similar electron-beam resist stack (two layers of MMA, one layer of PMMA).After EBL development, device substrates were etched in BHF for 10 s, and axial metal contacts were deposited by electron-beam evaporation (Kurt Lesker PRO Line PVD75) of 3 nm of Ti and 150-200 nm of Pd.Alumina deposition was then performed by using EBL with the same resist as used for contacts to define a large deposition window for ALD of alumina using a Veeco/Cambride Nanotech Savannah S200 ALD system.The ALD parameters included 190 °C chamber temperature, 20 sccm nitrogen (N 2 ) carrier gas flow, 0.015 s pulse times for water and trimethylaluminum (Al 2 (CH 3 ) 3 ), and wait times of 8 s. 100 cycles were performed to produce a thickness of ≈15 nm.Metal gate contacts were then fabricated following the same procedure used for axial contacts.
Device Measurements: Single-NW device measurements were performed using a probe station (Lakeshore TTPX Cryogenic Probe Station) under vacuum (<5 mTorr) at room temperature in the dark connected to a source measure unit (SMU, Keithley 2636B) with triax cable connections (Belden 9222 50 Ω).Each device was fabricated with two metal contacts on either side of the sawtooth section of the NW.
Electron Microscopy and EBL: SEM imaging and EBL were performed with a FEI Helios 600 Nanolab Dual Beam System.This system has an imaging resolution of less than 5 nm, and lithography was performed using the Nanometer Pattern Generation System (NPGS) software.
FE Simulation: COMSOL Multiphysics FE simulations have been previously utilized to model the electrostatic nature of NW GDs [2] with a 2D simulation domain and cylindrical symmetry.The FE model developed here includes Poisson's equation, drift-diffusion with density-dependent electrical mobilities and diffusion constants, bandgap renormalization, and Shockley-Read-Hall, Auger, and surface recombination, as described previously. [33]The simulated NW geometry consisted of two uniformlydoped n-type sections (4 × 10 19 cm −3 donor density), on either side of the GD sawtooth geometry.Within this model, we analytically define the donor dopant distribution profile as the gas phase ratio of Si:P during NW growth, which has been confirmed by scanning transmission electron microscopy mapping. [2]The NW is defined with a diameter of 175 nm, degenerately doped sections 1000 nm in length, a sawtooth constriction diameter of 110 nm, a long side taper length of 250 nm with an angle of 7.4°, and a short side taper length of 25 nm with an angle of 52.4°.For gated Si NW GD simulations, the NW is surrounded by a 15 nm alumina dielectric layer.The gate terminal was defined over the dielectric layer with a work function of 5.1 V, and two ideal source-drain contacts were positioned at either end of the NW.For asymmetric dopant profiles and uniform physical geometry simulations, the NW has a diameter of 50 nm.For asymmetric physical geometry and uniform dopant profile simulations, the NW has a 1 × 10 17 cm −3 donor density.For ungated simulations, the NW is surrounded by a 2 nm SiO 2 layer and vacuum.The surface charge density is calculated by multiplying N T by the charge of an electron.For planar SOI SSD simulations, the Si is uniformly n-type doped with a 2.45 × 10 16 cm −3 donor density and a thickness of 205 nm.The device has a channel length of 1300 nm, a channel width of 230 nm, a trench width of 200 nm, and a surface trap density of 1.5 ×10 11 cm −2 .

Figure 1 .
Figure 1.SSDs.A) Planar SSD devices, including (I) monolayer graphene on SiC; scale bar, 200 nm, (II) InAs/AlGaSb heterostructure containing a 2DEG; scale bar, 300 nm, (III) monolayer indium tin oxide; scale bar, 300 nm, and (IV) p-type SOI; scale bar, 400 nm.Images I, II, III, and IV are reprinted with permission from references 13, 12, 11, and 10, respectively.B) Illustration of a single-NW GD device with a single "sawtooth" segment and four Ohmic contacts.The n-type dopant gradient within the NW is represented by the color gradient from blue (high doping) to white (no encoded doping).C) Representative I-V characteristic for a single Si NW GD device.Inset: Si NW GD schematic with diode symbol to indicate polarity for an n-type device.D) Illustration of gated single-NW SSGD device with Si NW (blue), gate dielectric (teal), and metal contacts (gold).Inset: cross-section of the NW at the sawtooth constriction.

Figure 2 .
Figure 2. I-V characteristics of omega-gate Si NW GDs.A) SEM image of a single-NW device with axial contacts labeled a-d, gate contact over the sawtooth region labeled g, and a measurement configuration shown schematically for grounding configuration 1; scale bar, 2 μm.Inset: magnified SEM image of the sawtooth region of the Si NW.B) Schematic of grounding configurations 1 (left) and 2 (right) showing positive V app (1 + and 2 + , red) and negative V app (1 − and 2 − , blue) values.C) Semi-logarithmic I-V curves for a Si NW GD device before (light purple, lower curve) and after (dark purple, upper curve) gate fabrication measured with configuration 1 but with an electrically floating V g .(D) |I| as a function of V g for V app = ±1 V with grounding configurations 1 and 2. Background shading corresponds to ≈V g ranges corresponding to a maximum current plateau (green), current transition (yellow), and minimum current plateau (gray).(E)  as a function of V g for grounding configurations 1 (purple) and 2 (orange) for V app = ±1 V. Dashed line denotes  = 1.(F) Semi-logarithmic I-V curves for grounding configuration 2 at V g = −1.75V (square), −1 V (circle), and −0.5 V (diamond).Data correspond to the same points labeled in panel E.

Figure 3 .
Figure3.FE simulated electrostatic characteristics of omega-gate Si NW GDs.A) |I| as a function of V g for grounding configurations 1 and 2 for V app = ±1 V; background shading corresponds to ≈V g ranges corresponding to a maximum current plateau (green), current transition (yellow), and minimum current plateau (gray).B)  as a function of V g for grounding configurations 1 (purple) and 2 (orange) at V app = ±1 V with a dashed line at  = 1.C) Electron concentration, n, in the NW for V g = −5, −0.7, and 5 V for grounding configurations 1 and 2, scale bar, 150 nm.D) Electrostatic potential, , for V g = −5, −0.7, and 5 V for grounding configurations 1 and 2 with V app = ±1 V, scale bar, 150 nm; the black outlines define the interface between the NW and AlO x layer.E) Energetic potential, E, as a function of axial position (bottommost z-axis) for V g = −0.7 and V app = 1 V (blue), 0 V (gray, labeled 1 0 ), and −1 V (red) for grounding configuration 1. Axial positions of the NW constriction and end points of the short and long side tapers are denoted 0, l, and L, respectively.Inset illustrations show Fermi-Dirac distributions, f(E), partially colored green and red for electrons with and without, respectively, sufficient energy to transmit over the potential barrier within the sawtooth geometry.F) Potential barrier height as a function of V g for grounding configurations 1 and 2 with V app = ±1 V.

Figure 4 .
Figure 4. Comparison of NW-based SSGDs with planar SSDs and alternate NW geometries.A) Electron concentration, n, under zero (V app = 0 V), forward (V app = −1 V), and reverse (V app = 1 V) biases applied to the righthand side of an n-type Si SOI SSD device[10] (left; scale bar, 1 μm) and an n-type Si NW SSGD device (right; scale bar, 150 nm) in grounding configuration 1 at V g = −0.7 V. B) Semi-logarithmic I-V curves for the NW SSGD device (yellow) corresponding to the structures in panel A and planar SSD device (black) assuming a Si thickness of 205 nm.C) Electron concentration, n, for NW SSGD devices with uniform physical geometry but asymmetric dopant profile (left) and asymmetric physical geometry but uniform dopant concentration of 10 17 cm −3 (right).On left, V g = 1.4 V whereas on the right, V g = 0.9 V; scale bars, 150 nm.

Figure 5 .
Figure 5. Simulations of two-terminal ungated Si NW SSGDs with various surface trap densities.A) Electron concentration, n, in the ungated NW for V app = 0 V with N T = 1 × 10 11 cm −2 to 1 × 10 13 cm −2 for biasing conditions 1 − , 2 + (left) and 1 + , 2 − (right), and V g values that give the most comparable n results in the gated NW in grounding configuration 1; scale bars, 150 nm.B) |I| as a function of N T for grounding configurations 1 and 2 at V app = ±1 V; background shading corresponding to ≈V g ranges corresponding to a maximum current plateau (green), current transition (yellow), and minimum current plateau (gray).C)  as a function of N T for grounding configurations 1 (purple) and 2 (orange) at V app = ±1 V with a dashed line at  = 1.D) Potential barrier height along the NW axis as a function of N T for grounding configurations 1 and 2 at V app = ±1 V.

Figure 6 .
Figure 6.Two-terminal gated Si NW SSGDs.A) Schematic of a single-NW device showing the Si NW (blue), gate dielectric (teal), and metal contacts (gold) and measurement configurations for the two-terminal grounding configurations 1 (dark pink) and 2 (light pink).B) Experimental semi-logarithmic I-V curves for grounding configurations 1 (dark pink) and 2 (light pink).C) Experimental  as a function of V app for grounding configurations 1 (purple) and 2 (orange).D) FE simulation results for electron concentration, n, in the two-terminal gated NW for V app = ±0.1 and ±1 V; scale bar, 150 nm.E) Simulated semi-logarithmic I-V curves for grounding configurations 1 (dark pink) and 2 (light pink).F) Simulated  as a function of V app for grounding configurations 1 (purple) and 2 (orange).

Figure 7 .
Figure 7. THz rectification by Si NW SSGDs.A) Input voltage V app (black curve and left-hand axis) and current response, I (green curve and right-hand axis) as a function of time, t, for three-terminal gated Si NW GD devices with V g = −0.2V in grounding configuration 1. B)  AC as a function of f for V g = −0.6V (orange), −0.2 V (blue), and 0.2 V (yellow) in grounding configuration 2. (C)  as a function of f for two-terminal gated Si NW GD devices in grounding configurations 1 (dark pink) and 2 (light pink).