Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi‐Wire Channels

In this work, bottom‐up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top‐down fabricated nanosheet (NS) and multi‐wire (MW) reconfigurable field‐effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on‐ and off‐currents as well as threshold voltages for n‐ and p‐type operation exhibit a high degree of symmetry. Most notably also a low device‐to‐device variability is achieved. In this respect, the investigated Al–Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired‐AND gate obtained from a multi‐gate RFET. Additionally, up‐scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al–Si–Al platform has substantial potential to enable complex adaptive and self‐learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits.


Introduction
Reconfigurable logic has attracted considerable attention in recent years as a promising approach to effectively increase the functional density of integrated circuits.Different from conventional complementary metal oxide semiconductor (CMOS) electronics, the functional density is increased not only by the steady DOI: 10.1002/aelm.202300483miniaturization of the components, but by the functional diversification at the device level and the alteration of the operation of circuits built thereof. [1,2]rom a structural point of view the commonly used field-effect transistor (FET) architecture can be adapted by adding additional independent gate electrodes and replacing the highly doped source and drain regions with abrupt metalsemiconductor junctions in order to deliver the envisioned RFETs.Such transistors embrace the functional enhancement of FETs by being capable of dynamic runtime switching between n-and p-type FET operations.This is in contrast to the static nature of CMOS technology, where the n-and p-type FET polarity is fixed physically by the choice of dopants employed at the source/drain and channel regions.Moreover, the logic circuit topology built from these is predefined lithographically by the interconnection of the n-and p-type FETs.A key technological advantage of RFETs as based on Schottky barrier (SB) FETs (SBFET) is that the devices are universally applicable for n-and p-type operability.[5] In this respect, metal-semiconductor-metal heterostructures deliver a convenient platform for the integration of such SBFET devices. [6,7]Independently gating the metalsemiconductor junctions allows electrostatic control of the injection capabilities for electrons and holes, and thus the selection of n-or p-type operation. [2,8]In order to unfold the full potential of RFETs for runtime reconfigurable and hardware-secure logic circuits, a high degree of symmetry regarding on-and offcurrents, threshold voltages and subthreshold slopes for n-and p-type operation is essential.Remarkably, the Al-Si material system is particularly promising for reconfigurable electronics, due to its relatively symmetric barrier heights for both electrons and holes [9] as compared to concurrent CoSi, PtSi, and NiSi 2 junction technologies. [10,11]In contrast to other approaches that target symmetric RFET properties, no additional measures, such as, e.g., strain engineering or doping are necessary for the Al-Si material system. [12,13]Notably, using Al as source/drain contacts, the Fermi level pins close to the middle of the Si bandgap and thus exhibit similar SBs for electrons and holes. [14]Contrary to the bulk Al-Si material system, abrupt and void-free metal-semiconductor interfaces are formed within the nanostructure providing well-defined and reproducible Schottky junctions.Additionally, no intermetallic phases are formed, overcoming the often encountered difficulty of multi-phase formation in state-of-the-art metal-silicides, [15][16][17] reducing process variability and yield issues.At a device level and at first glance, RFETs suffer from smaller drive currents and typically higher supply voltages compared to conventional MOSFETs.Nevertheless, recent studies have shown that the exploitation of the enhanced fine-grain functionality of RFETs at the circuit level provide competitive advantages over conventional CMOS in terms of area. [18,19]Combining the functionality of reconfigurable transistors into a logic cell enables the efficient realization of intrinsic XOR gates, [6,20] wired-ANDs [21,13] or multifunctional logic gates with the capability of dynamically switching between NAND and NOR operation. [22,23]oreover, due to reconfiguration capabilities, self-learning algorithms allow the realization of intelligent self-adaptable logic devices down to the device level.Thus, the integration of RFETs offers a wide variety of applications in functional diverse adaptive computing, [24] beyond computing purposes as well as new approaches for hardware security solutions. [25,26]

Nanowire-Based RFET
First, bottom-up RFET devices from vapor-liquid-solid (VLS) grown NWs are realized as this implementation constitutes a simple prototyping vehicle without utilizing nanolithography to define the NW diameter and is used here to discuss the general properties of the realized RFET architecture.Another crucial advantage of NWs is the capability to decouple high-temperature processing, i.e., NW oxidation at the growth substrate from the final device substrate limiting temperatures to the contact anneal temperatures.In this context, contact printing of parallel arrays of Si NWs [27] as well as a low-cost and flexible platform for printed circuits were demonstrated. [28]The used NWs with a predominant ⟨112⟩ growth direction have typical diameters of d NW = 80 nm and are nominally intrinsic.Thermal oxidation at 1174 K for 3 min leads to the formation of a high-quality SiO 2 gate oxide shell of nominally d ox = 9 nm.After drop-casting the suspended NWs in solution on a p-doped Si substrate covered with a dry thermal SiO 2 of 100 nm thickness, Al source/drain contacts are fabricated.Using rapid thermal annealing (RTA) at a temperature of 774 K in forming-gas atmosphere, the thermally induced Al-Si exchange is initiated to achieve well-controllable Si channels defined by single-crystalline Al contacts with abrupt Al-Si interfaces. [9]Finally, Ω-shaped Ti/Au top-gates are fabricated.Figure 1a shows a false-color SEM image of the thereof obtained Al-Si-Al NW-based RFET, with "CG" being the control gate to turn the transistor on and off and "PG" being the program gates, which allow dedicated selection between n-and p-type operation by applying a positive or negative voltage, respectively.Note that the PG top-gate electrodes are electrically connected and hence are on the same potential for symmetric tunability. [7,29]Importantly, the PG electrodes need to be accurately aligned above the Al-Si interface for sufficient tunability of the injection barrier between the metal and semiconductor. [30]n terms of top-gate scaling, TCAD simulations have shown that a spacing between the CG and PG electrodes of only 10 nm is feasible. [30]Figure 1b shows the energy dispersive X-ray (EDX) map of the obtained Al-Si interface, indicating no intermetallic phases and an abrupt transition between Al and Si.Additionally, the evidence of the SiO 2 -shell covering the metal and semiconductor channel is clearly visible in particular on the intruded Al region.A high-angle annular dark field (HAADF) scanning transmission electron microscopy (STEM) image of the Al-Si interface is shown in Figure 1c, which further shows the high-quality and abrupt metal-semiconductor interface of the proposed material system.Note that, in the STEM (cf. Figure 1c), the crystalline nature of the intruded Al is also visible directly at the Al-Si junction.
Investigating relevant transistor parameters as depicted in Figure 2, allows for characterization of the RFET performance.One of the most important parameters considering the symmetry of RFETs are the on-and off-currents both in n-and p-type operation, denoted as I n∕p on∕off in the following.Especially for highly integrated logic circuits, realized with RFETs, this is of particular interest due to the necessity of appropriate driving capabilities and the realization of inverters and other complementary circuits. [6,13,31]Another important aspect in this context is the symmetry of the threshold voltage for n-and p-type operation, denoted as V n∕p th .For the extraction of the threshold voltage, the transconductance method is used, [32] where the transconductance is obtained from the transfer characteristic (dI D /dV CG ).Finally, the subthreshold slope S n/p is of high relevance in the context of logic gates, as it qualitatively describes the transition between the on-and off-state.

Top-Down Integration
As a wafer-scale integration of bottom-up grown NWs still faces significant challenges, i.e., precise placement of single NWs or difficulties in high integration of NW circuits, RFETs based on top-down technology are of utmost importance.Moreover, for NWs, oxide formation, and Al-Si reaction rates heavily depend on the initial NW diameter and orientation, whereas in top-down technology, an enhanced controllability of the Si channel shape and surface results in higher reproducibility.In this respect, NS RFETs were implemented using top-down fabrication techniques.Thereto, Si mesa structures were patterned out of a silicon on insulator (SOI) substrate with a 20 nm device layer using laser lithography and dry etching techniques.Thus, using commercially available SOI substrates, the compatibility and potential integration capability with modern fully depleted SOI (FD-SOI) CMOS technology is guaranteed. [33]These Si NSs range from 320 to 450 nm in width and are covered in 12 nm thick thermally grown SiO 2 gate oxide, with a remaining Si device layer of 15 nm after oxidation.Afterwards, annealing at 774 K for 60 s was performed, where a mean Al-Si exchange rate of (57.9 ± 3.0) nm s −1 was evaluated. [9]To derive the optimal operating parameters of the RFETs and thereof created logic circuits, conduction maps are shown in Figure 3, showing the drain current |I D | of the device in logarithmic scale.Tuning the injection barriers of the Al-Si junctions with V PG , the RFET can be efficiently switched between electron (V PG = 7 V) and hole conduction (V PG = −7 V), resulting in two distinct operation windows, marked in Figure 3a.Note that reducing the oxide and/or using high- oxides would significantly reduce the required gate voltages. [34]Furthermore, the on-currents for both modes are highly symmetric, with up to I n on = 1.6 μA (I n on = 3.7 μA μm −1 ) and I p on = 4 μA (I p on = 11.6 μA μm −1 ) for V D = 1 V.Note that the values in brackets are the respective current values normalized to the width of the Si channel.It needs to be considered that the limiting factor for the maximum oncurrents is the tunneling contribution through the Schottky bar- rier and its band bending capabilities. [11]Moreover, using sufficiently high PG voltages, the undesired charge carrier type is efficiently suppressed, resulting in off-currents below the resolution limit of the measurement setup (250 fA). Figure 3b,c shows the unipolar n-and p-type operation of the RFET for V PG = 7 V and −7 V, respectively.Increasing the bias voltage V D leads to further tuning of the on-states and thus to higher currents and a higher level of symmetry.From the conduction maps, it is evident that the proposed RFET devices can be well integrated into reconfigurable logic circuits, since their operation is stable even over a wide voltage range.
Furthermore, evaluating the device-to-device variability and transistor stability in terms of the previously mentioned parameters, twenty NS-based RFET devices were systematically analyzed evaluated.As the and off-currents and the threshold voltages in n-and p-type operation are the most important parameters of transistors, especially for logic circuits, these parameters are visualized in Figure 4.Note that for the transfer characteristics, a bias voltage of V D = 1 V was used.The mean on-current normalized to the width of the NSs results in I n on = 6.24 μA μm −1 and I p on = 11.81 μA μm −1 (see Figure 4a), whereas the off-currents I n,p off remain below the resolution limit of the measurement equipment.The corresponding mean current densities are J n on = 41.6 kA cm −2 and J p on = 78.7 kA cm −2 for n-and p-mode operation, respectively, resulting in a mean on-current symmetry of a factor of 1.9.In comparison, a different contact technology based on Ni-silicide NW RFETs shows a symmetry factor of the on-currents of 17.6. [35]In this regard, further symmetry adjustment might be possible by fine-tuning the compressive strain to the Si cross-section.As the threshold voltage V th is another important parameter in driving logic circuits, Figure 4b shows the extracted values in n-(red square points) and p-type (blue square points) operation mode.For the extraction of the threshold voltage, the transconductance method was used. [32]Remarkably, also the extracted mean V th values exhibit a high degree of symmetry with V n th = 1.8 V and V p th = −2.8V.For the NS-based RFETs a mean hysteresis of 71 mV in n-mode and 110 mV in pmode operation was extracted, calculating the difference of the threshold voltages V th of backward and forward sweeps (≈5 s per sweep direction).Moreover, evaluating the transfer characteristics, the subthreshold slopes were extracted with S n = 480 mV dec −1 and S p = 340 mV dec −1 , which again depict well the symmetry of the top-down fabricated Al-Si RFETs.In already published works on single-gated SBFETs [36] and dually gated RFETs, [37] the subthreshold region can be controlled by program gate coupling.This is given by the change of thickness and transmissibility of the Schottky barrier with V CG .However, in a threetop-gate RFET device architecture, the potential at the Schottky junctions is fixed by V PG .Therefore, the ultimate thermal limit of 64 mV dec −1 can only be reached, if an efficient gate coupling in terms of thin Si layers, thin gate oxides with a low equivalent oxide thickness (EOT), and ideally gate-all-around (GAA) gating geometries are applied. [6,38]

Multi-Control Gate RFET
To show a further significant advantage in terms of flexibility of top-down fabricated RFETs, Figure 5a depicts a false color SEM image of a multi-CG RFET implementation of a three-input wired-AND gate based on the proposed Al-Si-Al NS RFETs.Such devices are of high importance as they feature the advantage of suppressing parasitic charge-sharing effects in dynamic logic gates. [21,39]Further, this type of device enables the realization of logical gates with dedicated pull-up and pull-down networks, with the advantage of replacing the entire lower branch of a NAND gate by a single transistor with multiple inputs (see inset of Figure 5a).Importantly, using this concept, the number of inputs can be increased for the realization of multi-input logic cells, which is only limited by the higher resistance of long-channel RFETs, reducing the drive current.The investigated wired-AND gate is realized by splitting the CG into three independent gate electrodes enabling additional energy barriers to turn the RFET on only when a logic high is applied to all gates.In the actual case the supply voltages V DD = V PG and V SS were chosen to be 3 and −3 V, respectively.Toggling the input signals A, B, and C between ±3 V, we have realized a logic gate only needing one voltage domain, which simplifies the circuit layout.Figure 5b shows the transient operation of the proposed three input wired-AND for driving the inputs A, B, and C with 0.1, 0.2, and 0.4 Hz, respectively.This relatively low operation speed of the wired-AND gate was chosen due to limitations of the measurement setup and our lab-based design of the structures, with large planar contact pads on top of the SOI substrate for contacting the probes, inducing extremely high parasitic capacitances.Nevertheless, the obtained results verify its function.Note that mixed-mode TCAD simulations have already shown the operability of scaled and optimized Si-based RFETs with back-end-of-line interconnect technology in the GHz regime. [30]Analyzing the transient trace of the output current I DD reveals its capability of properly suppressing the current in the off-state, which is below the noise floor of our measurement system (<250 fA), while maintaining oncurrents of ≈40 nA, giving an on/off ratio of more than five orders of magnitude.Importantly, applying V PG = −3 V, thus operating the RFET in p-mode, current through the device would only be driven for applying −3 V to all inputs.This allows a high degree of flexibility for circuit and layout designers and is therefore a further advantage of the proposed RFET based wired-AND.

Multi-Wire RFET
To provide an effective strategy for current up-scaling a MW RFET is presented next.Importantly, the advantage of flexibility in the patterning of SOI is a crucial enabler for this type of device.A false-color SEM image of the actual device is shown in Figure 6a.The device consists of ten parallel Al-Si-Al NS heterostructures, which enable a tenfold current increase compared to a single-NS device, enhancing logic gates for, e.g., driving stages of wired gates and power-demanding electronics.The realization of such a parallel array of metal-semiconductor heterostructures is possible due to the stable crystal phase of the intruded Al leads, resulting in less process variations compared to silicidation rates of common Ni x Si 1−x -Si heterostructures. [17]his is of significant importance, as it is crucial to align the PGs atop all metal-semiconductor junctions in order to efficiently tune the barriers of the whole device.The transfer characteristic of the fabricated device in Figure 6b shows the significantly increased on-current, with I n on = 14.7 μA (I n on = 4.2 μA μm −1 ) and I p on = 172 μA (I p on = 48.9μA μm −1 ) at V D = 2 V, while the offcurrents and hysteresis remain low.The accumulated width of the individual NSs was used for normalization.Other transistor parameters, such as the threshold voltages V n th = 0.84 V and V p th = −0.7 V as well as subthreshold slopes S n = 310 mV dec −1 and S p = 230 mV dec −1 remain similar to the single NS transistor.Compared to parallel arrays of bottom-up grown NWs, [28] the top-down fabrication approach is much more controllable and scalable for highly integrated devices and depicts a high potential toward wafer-scale integration. [40]Moreover, the capability to fabricate parallel NSs demonstrates the possibility for further enhancements in realizing logic circuits.

Conclusion
In conclusion, we have used bottom-up NWs to demonstrate RFETs and evaluated as well as exploited top-down SOI-based NS RFETs.The thereof fabricated three top-gate RFETs were analyzed from a transistor's perspective, where different highly rele-vant parameters, such as I on , I off , V th , and the sub-threshold slope S for both n-and p-type operation modes were investigated and discussed.Importantly, due to the combination of symmetric activation energies of electrons and holes for the Al-Si material system and sophisticated top-down fabrication, RFETs with an oncurrent symmetry between the n-and p-type operation modes of 1.9 are achieved without the need of stress leavers.To exemplary show the flexibility of the presented Al-Si-Al RFET platform, we have demonstrated a multi-CG RFET resembling a three-input wired-AND capable of reducing the overall transistor count by a factor of two.In particular, we have shown that with ten parallel NSs the on-current I on can be significantly increased, whereas the off-current I off remains at an acceptably low value, which is relevant for power-intensive electronics as well as for logic circuits.Thus, the monolithic Al-Si heterostructure RFET technology is promising towards the realization of high-performance and even self-learning reconfigurable electronics.

Figure 1 .
Figure 1.a) Colored SEM image of a NW-based Al-Si-Al heterostructure integrated as a three top-gate RFET.b) EDX map revealing the abrupt Al-Si interface without any intermetallic phases.The 9 nm thick SiO 2 oxide shell is visible as well.c) HAADF STEM image of the Al-Si interface with the Si part oriented along the [110] direction of observation.

Figure 2 .
Figure 2. Transfer characteristic for applying V D = 1 V of an NW-based Al-Si-Al RFET with characteristic transistor parameters.The inset shows the band diagrams and the underlying electrostatic gating mechanism for nand p-type operation.

Figure 3 .
Figure 3. Semi-logarithmic conductance maps of a top-down fabricated Al-Si RFET.Panel (a) showing the transition from p-to n-type operation by increasing V PG from negative to positive voltages.b) p-type operation at V PG = −7 V and c) n-type operation at V PG = 7 V in dependence of the bias voltage V D , revealing distinct and symmetric on-and off-states for both modes.The insets show the respective transfer characteristic at V D = 1 V.

Figure 4 .
Figure 4. Extraction of the most relevant parameters of 20 NS (SOI) RFETs: a) I n,p on,off , where the solid square points indicate the on-current and the empty square points the off-current.b) V n,p th where the red and blue square points mark n-and p-type operation, respectively.

Figure 5 .
Figure 5. a) Colored SEM image of a multi-CG Al-Si-Al NS RFET resembling a three-input wired-AND gate capable of replacing the lower branch of a NAND gate (see inset).b) Transient operation for driving the inputs A, B, and C with 0.1, 0.2, and 0.3 Hz, respectively.V DD = V PG = 3 V and V SS = −3 V were set.

Figure 6 .
Figure 6.a) Colored SEM image of a top-down fabricated MW RFET based on ten parallel Al-Si-Al NS heterostructures.b) The transfer characteristic reveals an increase of the on-current, enhancing the drivability of logic gates compared to single NW/NS RFETs.