A Dual‐Mode Programing Nonvolatile Floating‐Gate Memory with Convertible Ohmic and Schottky Contacts

Research on van der Waals heterostructures based on stacked two‐dimensional atomic thickness crystals has received considerable attention because of their unique characters and great potential applications in flexible transparent electronics and optoelectronics. In this study, a nonvolatile memory device with a few‐layer bipolar material WS2 as channel and charge‐trapping layers is designed with a floating‐gate structure in which charges (electrons and holes) can be stored in the charge‐trapping layer using a dual‐mode processing program by changing the metal–semiconductor contact type. The device exhibits different programming currents during programming, in particular, the device has a low programming current for programming voltages ˂20 V. Moreover, the heterostructure exhibits a remarkable long retention time (≈10,000 s), with no apparent degradation and a strong endurance, retaining its original performance even after 1,000 programming/erasing cycles. This study proposes a novel method for reducing power consumption while programming to facilitate artificial synapse applications.


Introduction
Since the mechanical exfoliation of graphene from bulk graphite in 2004, [1] 2D materials with atomic thickness and high carrier mobility have been used in various applications, including highperformance electronics, [2,3] optoelectronics, [4][5] , and flexible and transparent wearable devices. [6,7]Due to their wide bandgap, DOI: 10.1002/aelm.202300503various 2D atomic materials, including graphene (conductors, zero bandgap), transition metal dichalcogenides (TMDCs; narrow bandgap, semiconductors), and hexagonal boron nitride (h-BN; ultrawide bandgap, insulators), have been investigated and have demonstrated excellent performance. [8,9]lexible and multitudinous heterostructures can be constructed by vertical stacking 2D materials layer by layer, that can provide an effective means of designing a novel combination of 2D materials with desirable performance via taking advantage of the different capabilities of each component. [8,10,11]Hence, the emergence of such heterostructures provides a platform for achieving high performance in applications. [12]Ambipolar semiconductors, a different part of 2D materials, which can transport both types of charged carriers, electrons, and holes, have received considerable attention.This unique feature makes it more adaptable to a wide range of applications. [13]owadays, the technology of silicon (Si) flash memory that is widespreadly used has hit a bottleneck.To replace the widespread Si flash memory, novel device architectures, such as floating-gate field-effect transistors (FGFETs), and semi-floating gate FETs (SFGFETs) based on 2D materials, should be improving many performances of future nonvolatile memory devices in these aspects, including scaling down the device size, increasing the write/erase speed and storage capacity, and reducing the data access time.In FGFET-based devices can be served as nonvolatile memory with control gate (CG)/ gate dielectric layer/ floating gate (FG)/ potential barrier layer/ channel layers structure that can store charges in FG. [14][15][16][17] Related studies previously reported showed that graphene or MoS 2 can be incorporated into structures as a FG layer to trap charges and h-BN as a barrier layer to produce nonvolatile memory devices. [17,18]In order to obtain higher-performance nonvolatile memory devices, the FET channels with ambipolar 2D semiconductors should be explored that can provide two types of charges (electrons and holes).Ambipolar semiconductors, a different part of 2D materials, which can transport both types of charged carriers, electrons, and holes, have received considerable attention.This unique feature makes it more adaptable to a wide range of applications.Lately, FETs with an ambipolar semiconducting material, tungsten disulfide (WS 2 ) flakes, showed a typical ambipolar performance with a high on/off ratio reaching up to 10 6 . [19][22][23] On account of the ambipolar FET behavior of the 2D heterostructure, graphene can also be applied in ambipolar devices, such as inverter logic circuits and type switching memory devices.Nevertheless, graphene limits device performance because of its zero bandgap. [24]In this study, using WS 2 flakes as a FET channel and floating gate, we designed a WS 2 /h-BN/WS 2 -stacked heterostructure and found that they could be applied for high-performance nonvolatile memory devices with a dual-mode program state.

Discussion
Figure 1a demonstrates the construction of the designed WS 2 /h-BN/WS 2 heterostructure-based FGFET device with dual-mode programming, which can be used as nonvolatile memory, where a heavily doped n-type Si substrate is used as the CG electrode.WS 2 and h-BN nanosheets were obtained through multiple mechanical exfoliation processing with blue adhesive tape.To construct the designed device structure, the first piece of WS 2 nanosheet was first transferred to a 300 nm-thick thermal oxide film on the n-type Si, which served as the FG, i.e., the charge-trapping layer.Further, h-BN and WS 2 (another piece) nanosheets are aligned on the previous WS 2 nanosheet, which acts as a potential barrier layer and a FET channel layer, respectively.The dry transfer-align processes and the standard lithography method were used in device fabrication that is explained in detail in the Experimental Section. Figure 1b exhibits an optical microscope image of the designed WS 2 /h-BN/WS 2 heterostructure nonvolatile memory device; the regions of WS 2 and h-BN nanosheets are looped by yellow and blue, respectively.The thickness of the heterostructure was measured using atomic force microscopy (AFM), and Figure 1c shows the results.As shown in Figure 1d, the detailed thickness variations of the profile line in Figure 1c was extracted, i.e., the WS 2 charge-trapping, h-BN barrier, and WS 2 channel layers with thicknesses of 12, 14, and 6 nm, respectively.The presence of different components was confirmed using Raman spectroscopy.The Raman mapping image of the heterostructure with the peak position at 354 cm −1 , which demonstrates the location of WS 2 clearly, is shown in Figure 1e, and the Raman intensity of the WS 2 channel layer was higher than that of the WS 2 barrier layer because the former was at the top layer.Besides, the Raman signatures of WS 2 (E 2g 1 and A 1g peaks located at 354 and 419 cm −1 , respectively) and h-BN (E 2g peak located at 1366 cm −1 ) were obviously observed in the WS 2 /h-BN/WS 2 heterostructure device (Figure S1, Supporting Information).As exhibited in Figure 1f, the transfer curve of a traditional SiO 2 back-gate FET with WS 2 channel displayed two threshold voltages, −8 and 4 V, indicating that WS 2 is an ambipolar material.
In the aforementioned traditional back-gate structure, the contact between the semiconductor and metal is Ohmic both at positive and negative gate voltages.However, in the device structure displayed in Figure 1a, the type of contact can be changed by the gate voltage because of the insert layers, namely the WS 2 FG and h-BN barrier layers.Few-layer WS 2 has a bandgap of ≈2.0 eV and an electron affinity of ≈3.93 eV, indicating that it can be an effective charge storage layered material.In contrast, the h-BN has an ultrawide bandgap (≈5.9 eV) with a small electron affinity (2 eV), indicating that it can act as an effective potential barrier to hold charges in the bottom WS 2 layer.When a positive voltage was applied to the CG (SiO 2 layer), electrons were induced in the WS 2 channel and tunneled through the h-BN barrier layer to the WS 2 FG layer due to the electrical field effect; the electron transfer reduced the Fermi energy level (E F ) of the WS 2 channel, and the Ohmic metalsemiconductor contact was maintained (Figure2a,b).As shown in Figure 2b, the IV curve of the metal-semiconductor contact has strong symmetry.Notably, WS 2 has a unique property: its dominant charge carrier type can be modulated by an external electrical field, also known as ambipolar material.In contrast, when a negative voltage is applied to the CG, holes tunnel into the bottom WS 2 FG layer, thereby increasing the E F of the upward WS 2 channel layer, and the metal-semiconductor contact transfers from Ohmic to Schottky contact, forming a high conductivity region (Figure 2c,d).With an increase in the negative voltage applied to the CG, the E F of the WS 2 channel layer increases and the Schottky contact is more prominent in the metal-semiconductor contact, forming a high resistance region (Figure 2d).
Moreover, owing to the presence of the h-BN barrier layer, the injected electrons and holes stored in the WS 2 FG layer by CG voltage cannot return to the WS 2 channel layer on their own unless an opposite voltage is applied to the CG.Therefore, the het-erostructure is suitable for application in nonvolatile memory devices.Figure 2b,d recorded the I ds -V ds curves when the CG applied different positive and negative voltages, respectively.The curves demonstrate that a linear correlation between current and voltage when applied positive CG bias, indicating that the contact formed Ti/Au electrodes and the few-layer WS 2 nanosheet is Ohmic contact; however, the I ds -V ds curve shows diode characteristics when V ds is between −5 and + 5 V, current singleguided characteristics, indicating that the electrodes and WS 2 flakes form Schottky contact.As shown in Figure 2e,f, a clockwise hysteresis was appeared in the transfer characteristic curve because of the interfacial charge-trapping states.When a positive voltage is applied on the Si CG, a more obvious hysteresis and larger memory window occur with a greater positive voltage, and when a negative voltage is applied to the CG, there is hysteresis until−4 V.The large voltage hysteresis revealed in the WS 2 /h-BN/WS 2 -stacked heterostructure device strongly determines the memory window in nonvolatile memory devices.The larger memory window signifies the device will be more reliable.In this work, the memory window of the device can reach ≈40 V when the CG voltage swept a full loop between −20 and + 40 V.
The amount of charges stored in the WS 2 FG layer can be calculated as follows: where e is the electron charge, ΔV is the threshold voltage shift,  SiO 2 is the relative dielectric constant (≈3.9) with  0 is the vacuum permittivity, and d SiO 2 is thickness of the SiO 2 (300 nm in this work), respectively. [8]Calculated from the above equation, the density of the stored charges was obtained whose approximate value is in the order of 10 12 cm −2 , the result is close to previous reported results by employing SiO 2 as a CG dielectric but smaller than that of high-k dielectric materials.Therefore, nonvolatile memory devices should demonstrate a better electrical performance if high-k dielectric material is used in CG layer.Different from other nonvolatile memory devices, our designed FGFET has two different programming states (highcurrent mode and low-current mode).As shown in Figure 3, two different modes to achieve a programming state using different CG voltage biases ( + 20 and −20 V).In Figure 3a, the device achieves a programming state with high programming current using a positive CG like other traditional memory devices.When + 20 V is applied to the CG, electrons can tunnel through the h-BN barrier layer from WS 2 channel layer to WS 2 FG layer.Although the large positive CG voltage was removed, the electrons tunneling into the FG layer were trapped in the WS 2 FG layer because of h-BN barrier layer, so, the WS 2 channel became hole conductive, and the metal-semiconductor contact between WS 2 channel and metal electrode remains Ohmic contact.Therefore, the programming processing current and the read current after programming processing are larger than the erase state.In another case, when a −20 V is applied to the Si CG, holes of the WS 2 channel layer can tunnel through the h-BN barrier layer to the WS 2 FG layer, and the metal-semiconductor contact turns into a Schottky contact.Hence, the current of the programming state has a small value under a voltage difference between source and drain terminal.After the gate bias was reset (0 V), a part of the holes accumulated on the WS 2 FG layer before would be drawn back to channel layer to reduce the Schottky barrier; therefore, the read current after programming processing is larger than the erase and programming states.When + 1 V is applied to the CG, the electrons return to the WS 2 FG layer to erase the information.The only difference between the two programming modes is the current level of programming processing.The ultralow current level of programming processing can further reduce operating power consumption.
The dynamic performance of the device in the condition of V ds is + 3 V was shown in Figure 4a, the results indicating the memory can be rapidly switched between programming and erase states through changing the voltage pulse that applied on the CG.Initially, a −10 V voltage pulse with a pulse width is 1.5 μs was applied on CG, the device is in the programming ("ON") state.After removing the voltage pulse, the device remains the low-current mode programming state due to the holes stored in WS 2 FG layer and the metal-semiconductor contact is Schottky contact.When a 2 V voltage pulse with 1.5 μs pulse width, the device can switch to the erase ("OFF") state.Although the CG voltage reset to 0 V, the device can remain in the current state.The endurance performance was demonstrated in Figure 4a, the performance of the device is still the same as it was at the beginning after 1000 switching cycles.
After a negative voltage pulse (−20 V, 1 s) is applied to the CG, holes are accumulated in the WS 2 FG layer, and the WS 2 and Ti/Au form a Schottky contact.When the CG voltage is reset to 0 V, the programming state of the device remains and the current is nearly unweakened from 4.66 × 10 −11 to 4.63 × 10 −11 A in 10 000 s.For the erase state, the current is reduced from b) Retention performance; the current is measured at V cg = 0 V with a pulse voltage of + 1/−20 V, a pulse width of 1 s, and a V ds of 3 V.The high-and low-current levels correspond to the programming ("ON") state and erase ("OFF") state, respectively.
3.55 × 10 −13 to 3.51 × 10 −13 A after removing the pulse 10 000 s.That means the erase/programming ratio keeps ≈100 in 10 000 s, in other words, the device has a well retention characterize.

Conclusion
In this study, we developed a nonvolatile memory device of WS 2 /h-BN/WS 2 -stacked heterostructure using SiO 2 dielectric.The device can change the metal-semiconductor contact type between electrodes and WS 2 channel through storing electrons and holes in WS 2 ambipolar FG layer.Notably, the WS 2 /h-BN/WS 2 -stacked FGFET nonvolatile memory device has two programming voltage modes and a low programming current when the programming voltage is below −20 V.The proposed method is promising for designing flexible and transparent high-performance memory devices with excellent charge storage, strong endurance and retention, and ultralow current of programming state, that can be applied in low-consumption artificial synapses based on 2D layered materials.

Experimental Section
Fabrication of the Device: Few-layer WS 2 and h-BN nanosheets were obtained through mechanical exfoliation from the corresponding bulk materials.In the order and location of the design, these nanosheets were aligned on heavily n-type Si substrate with a 300 nm thick oxide dielectric layer through a dry transfer procedure as reported.Detailed, the first WS 2 layer was first transferred to the oxide layer using 3 m Scotch tape.After that, the h-BN nanosheets were transferred on PDMS film and then aligned on the first piece WS 2 using optical microscope and transfer alignment platform.Because of the affinity difference between PDMS and substrate, the h-BN nanosheet can transferred to the desired position after a slight press.Last, the second WS 2 nanosheet was transferred to the top of the obtained h-BN/WS 2 heterostructure through the same method.Therefore, the designed WS 2 /h-BN/WS 2 heterostructure was prepared successfully.Further, typical lithography and metal evaporation were used to fabricate the device with Ti/Au (5/50 nm) electrodes based on the prepared WS 2 /h-BN/WS 2 heterostructure.
Characterization and Electrical Measurements: The electrical characterization of the fabricated device was measured by A Keithley 4200 semiconductor analyzer.AFM (Bruker Dimension ICON) measured the thickness of each component under a tapping mode.Raman measurement was performed with a WETIC alpha300 apyron Raman system.The laser wavelength is 532 nm and the intensity is 5 mW.

Figure 1 .
Figure 1.a) Structure diagram of the FGFET based on stacked WS 2 /h-BN/WS 2 heterostructure.The substrate is a heavily n-doped Si wafer (as CG) with 300 nm SiO 2 (as gate dielectric).Top WS 2 , h-BN, and bottom WS 2 are served as the FET channel, tunnel barrier, and FG layers, respectively.b) Optical microscope image of the fabricated device.c) AFM image of the heterostructure, and d) detailed thickness variations of the profile line in 1c), i.e., the WS 2 charge-trapping, h-BN potential barrier, and WS 2 channel layers with the thicknesses of 12, 14, and 6 nm, respectively.e) Raman mapping image of the heterostructure at 54 cm −1 .f) The transfer curve of a traditional WS 2 back-gate FET.

Figure 2 .
Figure 2. a) Schematic energy band of the FGFET at the programming state (V g >0 V) and b) the I ds -V ds curves at different positive voltages.c) Schematic energy band of the FGFET at the programming state (V g < 0 V) and d) the I ds -V ds curves at different negative voltages.e) A typical I ds -V cg curve measured at different drain voltages of −5-0 V and f) 0-+ 5 V with the CG voltage swept from −20 to + 40 V and back to −20 V.

Figure 3 .
Figure 3.The program state with a) a high current level when V g > 0 V and b) a low-current level when V g < 0 V and V ds = 1 V.

Figure 4 .
Figure 4. a) Endurance of the memory device for 100 cycles with V ds of 3 V, erase/program voltage pulse of −10 V/ + 2 V, and pulse width of 1.5 μs.b) Retention performance; the current is measured at V cg = 0 V with a pulse voltage of + 1/−20 V, a pulse width of 1 s, and a V ds of 3 V.The high-and low-current levels correspond to the programming ("ON") state and erase ("OFF") state, respectively.