Lifetime Improvement of 28 nm Resistive Random Access Memory Chip by Machine Learning‐Assisted Prediction Model Collaborated with Resurrection Algorithm

In this work, a machine learning‐assisted prediction model is proposed to analyze the reliability issues in the 28 nm resistive random access memory (RRAM) chip with raw data measured from RRAM test chip. The neural network of long‐short time memory (LSTM) is trained by the voltages and resistance during the endurance test (input vectors) and generates the output of the dichotomy states with a satisfied testing result >83.08%. According to the prediction results, the “real fail” state or “fake fail” state of the devices can get in the future. By collaborating with a well‐designed resurrection algorithm (RA), the percentage of real and fake failed cells dropped by 35% and 29%, respectively. Besides, the tail bits in retention significantly reduced from 33% to 14.6% due to the reduction of oxygen vacancies in the gaps of conducting filaments by applying ten consecutive cycles of RA. This intelligent prediction and repair module can prolong the lifetime of RRAM chips effectively in practical applications.


Introduction
In advanced 28 nm technology nodes and beyond, the application of embedded RRAM (eRRAM) can significantly save power consumption in the system-on-a-chip (SoC) scenario. [1,2]As an embedded module, the reliability of RRAM chips is affected by system noise, fabrication process, and other factors, which generally lead to problems of write dislocation, read interference, thermal DOI: 10.1002/aelm.202300504stability, and increasing difficulty in mass production.Therefore, how to improve the reliability of Non-volatile embedded memory (NVM) is still worth studying.At present, most of the reliability analyses focus on the device's level, [3] such as using an atomic force microscope (AFM) or TEM to observe the filament structure of the device, [4,5] fitting the IV curve with a physical model to obtain the filament shape, [6] and using random telegraph noise (RTN) to obtain the position information of the defect. [7]However, these schemes are not ideal approaches for chip reliability analysis.Microscope characterization is destructive to devices, so it is not suitable for practical applications; conventional regression can only fit a few variables at a time and a comprehensive model that incorporates all of RRAM's relevant factors has not yet been developed; Process fluctuations will cause device-to-device (D2D) variation.It is impossible to extract effective microphysical parameters for every device in real-time during the chip testing.Therefore, the devicelevel physical model does not have universal applicability.
10][11][12] As shown in Figure S1 (Supporting Information), there are differences between single devices and RRAM chips regarding reliability modeling, optimization strategy, and application.Due to the lack of system noise and process variability, the device-level physical models and optimization strategies are unsuitable for actual practical use in chips.Since the single physical model fails to accurately characterize the chip reliability and offers optimization guidance, the optimization strategy based on a single device model is also ineffective for the application of RRAM chips.In this case, there is a pressing need for the data-driven reliability model based on statistical data to be put in use, which involves the inevitable noise and variation.The data-driven reliability model grounded in statistical data collected from chips including system noise and variation can accurately predict the reliability of each unit in chips in real-time.According to this model, we propose an optimized programming algorithm and improve the chip's longevity.This optimization scheme of the chip level is effectively applicable to the product (Figure S1, Supporting Information).
It is difficult to find out a certain mapping relationship manually.Therefore, it is necessary to use machine learning (ML) to assist the analysis.ML has obvious advantages over humans in analyzing many test data. [13]Modeling complex behavior with ML is fast and convenient, especially compared to traditional approaches of equation fitting and calibration.[16][17] However, at present, most of the studies concentrate on the prediction model of retention characteristics and error rate of Flash. [18,19]There are few prediction models and corresponding solutions for the endurance and retention of RRAM chips.Iwasaki.T et.al has proposed a model to predict the endurance capability, which shows a large prediction span and a prediction accuracy rate of only 64%. [20]Wu et.al proposed a selective refresh strategy to reduce the updating cost by predicting the devices' retention behavior. [21]A convolutional neural network (CNN) based retention prediction framework is developed.However, this prediction model only could predict the devices' state in one hour.So, a comprehensive and accurate prediction model is urgently needed.
In our work, we established a prediction model by LSTM neural network with raw data from 28 nm RRAM chip to predict the states of memory cells.Based on the physical model of the device, we collect the device data directly from the chip to construct the training set and test set of the neural network model, in order to ensure that the model is scientific and universal.
In this model, nine-dimensional input data are trained, and the output is defined as a dichotomy of "real fail" and "fake fail."By training the model with the data selected from the memory array, the model accuracy rate is 86.75%.This model can be used to predict the states of the memory units in the future, with the highest accuracy rate of 83.08%.Based on the predicted results, a resurrection algorithm (RA) is utilized to recover the fake failed devices.By collaborating the prediction model of ML with RA, the lifetime of RRAM chips is significantly extended.Since this RA helps to eliminate oxygen vacancies (Vo) in the gap, the tail bits of retention decreased from 33% to 14.6% for the memory chip.The proposed model and RA have practical application value to improve the reliability (endurance and retention) of memory chips.This intelligent prediction and repair module helps to promote the industrialization of RRAM.

Switching Mechanism and Reliability Issues in Memory Array
Figure 1 shows the 3D physical diagram of the RRAM array.The RRAM cell is integrated on the BEOL of the standard 28 nm Poly-SiON platform.Detailed information about the RRAM process and chip [22] is in the Experimental Section and Figure S2 (Supporting Information).Figure 1b is the typical I-V curve of the TaOx-based RRAM, showing the bipolar switching characteristics.The program voltages for set/reset are 1 and 1.4 V, respectively.The Forming voltage is 1.6 V, and the compliance current is 100 μA. Figure 1c shows the I-V curves during the reset loop from 1.1 to 1.4 V. From 1.1 V on, the current decreases gradually and is well-fitted with the quantum point conductance (QPC) model. [23]Consequently, the filament morphology in our device is the shape of an hourglass.Changes in the model parameters ( x and  y ) for all fits are shown in Figure 1d.Here, the  y determines the constriction width, and  x determines the constriction length. [24]The excellent fit is found when constant V0 = 0.1 V, indicating a remaining tunnel barrier.The nearly constant  x and systematically increasing  y indicate a narrowing of the filament, corresponding to the rapture process of the hourglassshaped conductive filament (CF) (inset of Figure 1d).
The operation scheme of incremental step pulse programming (ISPP) is applied to RRAM.The initial pulses of the set operation are 1.3 V/700 ns applying on BL and reset operation 1.7 V/700 ns applying on WL, respectively, with the incremental step of 0.1 V.The voltage of the reading operation is 0.3 V.When the low resistance state (LRS) of the devices is lower than 30 KΩ within six steps, it is set success. [25]When the device's resistance value exceeds 200 KΩ in 6 steps, it is reset successfully.Figure S3 (Supporting Information) demonstrates the endurance characteristics of 1Kb cells on the 28 nm RRAM chip.As shown in Figure S3 (Supporting Information), memory units failing at the low resistance state (LRS), and middle resistance state (MRS) are caused by reset failure.Most devices can program up to 10 5 cycles with enough windows.However, tail bits would occur inevitably, especially in the large-capacity memory array, which is the most severe problem for the memory chip.The statistical overview of failed devices is shown in Figure 1e.The statistical overview of failed devices in the 1 Mb array shows that 63%, 28%, and 9% of devices failed in LRS, MRS, and high resistance states (HRS), respectively.The devices failing in HRS usually occur in the first few cycles, which can be easily removed by early screening.Therefore, detecting and reducing the device failures in LRS and MRS is essential for ensuring high production yield.Through the subsequent operation, those cells whose resistance is trapped below 25 KΩ can no longer be successfully reset, even if we raise the reset voltage.We refer to them as "real fail", and this phenomenon is reported in references [24] and [26] By contrast, these fault cells between 25 and 200 KΩ that could be successfully reprogrammed indicate a "fake fail", which is also reported in references [27] and [28] named soft-error.(Figure 1f).Based on the switching mechanism of bipolar Ox-RRAM, [29,30] the unbalanced electric field during programming leads to the gradual accumulation of Vo 2+ in the switching region, resulting in reset failure.If the device states can be predicted in advance, we can apply the repair strategy to the devices before they fail.For example, we can replace the real failed units through data rewriting technology The  y and  x determine the constriction width and length, respectively.Nearly constant  x and systematically increasing  y indicate a narrowing of the filament.e) Classification of the failed devices.The proportions of failed devices in LRS, MRS, and HRS are 63%, 28%, and 9%, respectively.f) Whether the device's state is "real fail", or "fake fail" is associated with the device's resistance.The devices with a resistance between 25 and 200KΩ may program successfully during the subsequent operation, indicating the "fake fail." and recover the fake failed units by means of an optimized programming algorithm, which would greatly improve the lifetime of memory chips.

Endurance Prediction Model for Memory Array
The resistive switching behavior of RRAM can be described as the change of the device's physical state (determined by the CF's morphology, the distribution of oxygen vacancies, the concentration of oxygen vacancy, and activation energy of ion mobility), which is reflected in changing of the resistance states.The resistance state is also affected by the cumulative effect of external conditions such as the number of programming pulses, voltage amplitude, and system noise.It is an impossible equation-fitting task for humans to combine all these effects into a comprehensive model.Hence, ML's complex pattern-matching capability is instrumental for RRAM to predict cells' possible states in the future.A prediction model based on LSTM is established to predict the states of the cells in the memory chip during endurance.LSTM is a long and short-term memory network, a special kind of recurrent neural network (RNN).Compared with traditional RNN, LSTM is more suitable for processing and predicting important events with long intervals in time series and can solve the gradient problem.Macroscopically, the nature of the lifetime prediction of a chip is to predict the resistance value of RRAM devices after a certain number of programming cycles.By defining the total number of cycles as a time series and defining a fixed number of cycles as a time slice, the task of predicting the number of cycles is converted into the task of predicting time slices.This kind of prediction task fits the LSTM architecture.For the RRAM device would be influenced by the accumulation of factors such as voltage amplitude, pulse number, and system noise during endurance, the LSTM network can combine the past and current characteristics of the task to complete the prediction.This characteristic of LSTM is well-suited for analyzing the RRAM accumulation effect during endurance.
In this model, the input Xt consists of nine dimensions of data.In order to obtain the input data of nine dimensions, we operate the RRAM chip as shown in Figure S4 (Supporting Information).To speed up the experiment, we execute the 500 cycles without verification.At the end of 500 cycles, 10 ISPP cycles are applied to verify the state of the devices.Because the failure behaviors are related to the morphology of the CF, the evolution process of CF's morphology will be represented by the resistance fluctuation.After 10 cycles of ISPP operations, we perform consecutive read operations and name it 100Read.The reason of consecutive reading is to read the devices' resistance value more accurately and get the fluctuation from the resistance value of devices. [25]he voltage of the read operation is 0. Figure 2a shows the whole work process of our proposed framework, including training, predicting, and repair strategy.In the process of model training, the data of 9 dimensions and the label of units' state are used as the training set.We define the "real fail" as label "0" and the "fake fail" as label "1".During the training, LSTM is unrolled along time so that the backpropagation algorithm updates the weights.The cross-entropy loss function and Adam optimizer are used for training.The model's output dichotomizes device states into "real fail" and "fake fail".
The predicting process of the model is shown in Figure 2b.The Xt in the current time slice (T N ), Cell State, and Hidden State of the last time slice (T N-1 ) are entered into the model that has been trained to predict the states of units in the next time slice (T N+1 ).Only the V forming is input to the model in the first time slice (T0).The Cell State and Hidden State are the param-eters of LSTM, and they could iterate over time.This model is able to generate real-time predictions.In chip design, separate control circuits and driver circuits can be designed for different blocks of the memory chip.In the prediction process, the LSTM and the normal endurance operation can be synchronized.Moreover, the RA operation signal fed back by LSTM can be performed at idle moments between the finite-state machines, without taking up extra time.The predicted accuracy increases with the increase of the training span and finally amounts to 86.75% with 20-time slices (Figure 2c).During prediction, the accuracy rates are 83.08% and 81.58% under 1 prediction span and 2 spans, respectively (Figure 2d).Here, a prediction span is defined as 500 cycles.

Synergy Between Prediction Model and Resurrection Algorithms
In accordance with the prediction results, a collaborated resurrection algorithm (RA) is proposed to recover these "fake fail" devices.Figure 3a demonstrates the pulse scheme of the algorithm package for RA.According to QPC theory, [31] The reason for the failure of RRAM is that the state of the hourglass-shaped filament becomes unstable due to the unbalanced electric field, which eventually leads to program failure.Therefore, when the unit is predicted to be a "fake fail" under the traditional ISPP programming (① and ② in Figure 3a), the filament morphology is shown in ① and ② in Figure 3b.When it is predicted to be a "fake fail", it means that the large set voltage causes the oxygen vacancy (Vo 2+ ) to gradually accumulate towards the interface, which leads to the thicker hourglass-shaped filament constriction.At this time, the equilibrium state of the CF has not been destroyed.The CF is in an unstable state.Applying a little higher single reset pulse combined with the original set operation, the Vo 2+ can gradually return to a balanced state under the little higher reset voltage.
A reset operation with a larger pulse width (③ and ④ in Figure 3a) is added after the traditional ISPP programming.The operating voltage is set as Vreset (Mean) +0.2 V, and the pulse width is 1 μs.This kind of reset operation can suppress the accumulation of Vo 2+ at the constriction of hourglass-shaped CF caused by the excessive set pulse.This algorithm package will be applied multiple times in order to slowly pull back oxygen ions to the oxygen reservoir, realizing the Vo 2+ redistribution in the switching region.Figure 3b (③ and ④) shows the schematic diagram of the filament's morphologies during recovery.Therefore, the Vo 2+ in the switching region redistributes and turns back into the initial equilibrium state.The detailed process of resurrection algorithms is shown in Figure S5 (Supporting Information).
We calculate the percentage of "real fail" devices and "fake fail" devices before and after applying RA.The percentage of "real fail" devices decreases by 35% (Figure 3c).The percentages for two groups of "fake fail" devices are shown in Figure 3d.The total percentage of "fake fail" devices decline by 29%.The percentage of "fake fail" devices of resistance values between 25 and 35 KΩ decreases by 26%.The percentage of "fake fail" devices, with resistance values ranging between 35 and 200 KΩ, drops by 32%.Meanwhile, the total recovery rate of "fake fail" cells is 55.5% higher than that without the RA (Figure 3e).The overall lifespan  Because of the synergistic effect of the prediction model and resurrection algorithms, the percentages decrease by c) 35% for "real fail" devices, d) 26%, and 32% for two groups of "fake fail" devices.e) The recovery rates for two groups of "fake fail" devices increase by 43% and 68%, respectively.
of the memory chip is expected to increase due to the reduction of real failed devices and the recovery of fake failed devices.

Data Retention Improvement of Memory Chip
Another factor that affects chip reliability is data retention characteristics, which would be divided into two aspects: short-term retention (relaxation) and long-term retention. [32,33]Figure S6 (Supporting Information) shows the relaxation characteristics of LRS and HRS extracted from 2 Kb units, respectively.The short-term retention is investigated by calculating the mean (μ) and standard deviation () of the resistance distribution over time.The  and μ of HRS increase with time, while LRS has little change.In order to study the factors that impact the relaxation of units, the units are operated for one cycle, 100 cycles, 500 cycles, and 1000 cycles after forming operation.Then they are modulated to different target resistance values (210, 230, and 250 KΩ) before relaxing.Figure 4a shows the relationship between the relaxation characteristics and the resistance values under different cycles.When the devices are operated for the same cycles, the higher the target resistance value is, the larger the  is.It shows that the  of HRSs increases as the number of programming rises.Therefore, the relaxation of the memory array becomes more severe with the endurance increases and higher HRS.
To control the relaxation, the RA operation would be applied to units between forming operation and traditional ISPP programming.For the HRS without RA, the tail bits gradually increase to 22% in 1 s.(Figure 4b).During the relaxation process, the  and μ of HRS also increase.The variation of μ is 7.21 KΩ, and the variation of  is 11.67 (Figure 4c).To clarify the effect of the RA on HRS relaxation, we conclude the statistical distribution of HRS during the relaxation process by adopting different cycles of the RA package (Figure 4d,e).After applying RA, the variation of mean and standard deviation decreases significantly.Compared with statistical distribution without RA, the tail bits of HRS gradually decrease with the increasing RA cycles, and the tail bits of HRS are well controlled by applying ten cycles of the RA package.As shown in Figure 4d, the tail bits decrease from 22% to 13.5%.By calculating the  and μ on HRS after ten cycles RA, the variation of  and μ decrease during relaxation.The variation of μ declines from 7.21 to 1.2 KΩ, almost by a factor of 6.The variation of  decreases from 11.67 to 10.1 (Figure 4e).The decrease of  and μ means that the resistance state will be more stable, and the tail bits in the relaxation will be held in check.It is worth noting that the tail bit becomes larger with more RA cycles (Figure 4d).As such, the RA needs careful design.To elucidate the optimization mechanism, we extract the density of Vo (N(EF)) for HRS with and without RA.Following Mott's approach, [34] the density of Vo 2+ in the gap could be calculated, and the density of Vo 2+ is inversely correlated with the slope of ln I and 1/KT.The density of Vo 2+ (N(EF)) in the interface of RRAM is obtained by the I-V curve after RA.The fitting result in Figure S7 (Supporting Information) indicates that the slope of the fitting curve with RA is greater than that without RA.The fitting result shows that the traps in the gaps are indeed decreased by applying the RA, and the density of Vo 2+ decreases as well.
According to the principle that RA operation could optimize the relaxation of the device, we also study the optimization of the long-term retention characteristics of the devices by applying RA cycles.Figure S8 (Supporting Information) shows the data retention for the entire 1 Mb chip at 125 °C.As the baking time increases, HRS has an obvious tendency to decline toward LRS, and LRSs are more stable than HRSs.The resistance value of almost all LRS devices is lower than 35 KΩ.Although some tail bits of HRS appear during baking, the resistance value of most HRS devices surpasses 200 KΩ.At the same time, the memory window of all devices is 6×−8× with the increase of baking time.These results suggest that more attention should be paid to HRS stability.HRS degradation is due to the combined effect of vertical diffusion of Vo and lateral diffusion of O 2− .[37][38] Figure 5a is the resistance distribution of HRS after baking 300 h at 125 °C by applying traditional ISPP programming.The units are programmed for 10 cycles, 100 cycles, 500 cycles, and 1000 cycles before baking.The illustration of Figure 5a shows the statistical distribution of HRS under different programming cycles.The tail bits have a positive correlation with the number of programming cycles.When the programming cycles reach 1000 cycles, the tail bits for HRS reach 33%.We believe that the state of CF would not be stable with the increasing cycling, indicating a trade-off between retention and endurance.
According to the result of Figure S7 (Supporting Information), the RA helps clean up the oxygen vacancies in the gaps of conducting filaments, and it would improve the long-term retention for HRS.The statistical distribution of the units is shown in Figure 5b by applying different RA cycles(5 cycles, 10 cycles, 15 cycles, 20 cycles, 50 cycles) after 1000 ISPP cycles and then baking at 125 °C for 300 h.When applying 15 RA cycles to the devices, the tail bits decreased obviously.However, when applying 50 RA cycles, the effect of reducing the tail bit is not obvious.The beneficial effect of RA is demonstrated in Figure 5b, where the tail bits fall sharply from 33% to 14.6%.This work provides a unique method of leveraging the collaborative effect of the LSTM-centered prediction model and RA to improve the stability and longevity of RRAMs. Figure S9 (Supporting Information) is the hardware implementation scheme of the prediction model and RA.The circuit block diagram mainly includes the input of the data set matrix, which performs matrix multiplication, addition, and transcendence operations with the parameter matrix in LSTM.The internal operations and logical judgments are controlled through control logic and state machines.The circuit output is the predicted result of the network.This hardware implementation scheme provides the potential to embed this intel-ligent prediction and recover module into the storage controller on SoC and further promote the wide application of RRAM.

Conclusion
We investigate the reliability of the 28 nm RRAM chip with a machine-learning approach.Using the LSTM neural network, we establish a prediction model that can predict the cell state of "real fail" or "fake fail" during endurance with a training accuracy rate of 86.75%.Based on the predicted results, a collaborated resurrection algorithm is employed to recover these anticipated fault devices and improve the cycling capability of RRAM chips.This kind of resurrection algorithm is also beneficial to controlling the relaxation and improving the data retention of RRAM chips.This proposed prediction model combined with the algorithm would promote the industrial application of RRAM technology.

Experimental Section
Devices Fabrication and RRAM Chip: Figure S2 (Supporting Information) shows the RRAM stack with TiN/IL/TaOx/TiN structure was integrated on the 28 nm Poly SiON platform.Figure S2b (Supporting Information) was the cross-sectional view of the whole 1T1R cell.The detailed image of the RRAM is shown in Figure S2c (Supporting Information).The RRAM unit was built between the contact plug (CT) and Metal 1 by adding only one non-critical extra mask.The bottom electrode (BE) was designed to avoid the adverse effect of the defective CT.Physical vapor deposition (PVD) deposits the switching layer and top electrode.An interfacial layer (IL) with a thickness of 2-5 nm was formed between the switching layer (TaOx) and BE. Figure S2a (Supporting Information) shows the physical diagram of the 1 Mb embedded RRAM chip, and the footprint of the 1 Mb embedded RRAM chip was 1300um × 1135um.The schematic diagram of the System on Chip (SoC) is shown in Figure S2d (Supporting Information).The RRAM chip include 1 Mb RRAM memory array, driving circuit, decoding circuit, and control logic circuit. [21]haracterization: The DC-mode and pulse-mode characteristics of the devices were measured with an Agilent B1500A Semiconductor Characterization System.The RRAM chip was measured by ADVANTEST V 93 000.

Figure 1 .
Figure 1.a) 3D cross-sectional view of the whole 1T1R array.b) The typical IV curves of the RRAM cell.Inset: morphology of the conductive filament (CF) composed of oxygen vacancies.c) I-V fitting by QPC model during reset program.(Grey dots: experimental DC IV data; blue solid line: fitting curve by QPC model.Inset: the quantum mechanical model for filament conduction.d) The change of the model parameters  x and  y obtained for all fits.The  y and  x determine the constriction width and length, respectively.Nearly constant  x and systematically increasing  y indicate a narrowing of the filament.e) Classification of the failed devices.The proportions of failed devices in LRS, MRS, and HRS are 63%, 28%, and 9%, respectively.f) Whether the device's state is "real fail", or "fake fail" is associated with the device's resistance.The devices with a resistance between 25 and 200KΩ may program successfully during the subsequent operation, indicating the "fake fail." 3 V.The 100Read is comprised of 100Read HRS and 100Read LRS .Reading in HRS is named 100Read HRS , and reading in LRS is named 100Read LRS .During each time slice (T),500 cycles without verification, 10 ISPP operations, and consecutive read operations are allowed to execute.Xt is obtained by preprocessing the measurement data under each time slice.Therefore, the nine-dimensional data collected under each time slice are forming voltage (V forming ), the mean value of 100Read HRS , the mean value of 100Read LRS , local fluctuation of 100Read HRS , local fluctuation of 100Read LRS , global fluctuation of 100Read HRS , global fluctuation of 100Read LRS , the mean value of set voltages, and the mean value of reset voltages.The local fluctuation of resistance of 100read is obtained by adding sobel operator for 1D edge detection.We obtain the global fluctuation of resistance of 100read by normalizing the variance of 100 resistance values.

Figure 2 .
Figure 2. The prediction model and the predicted accuracy rate in training and prediction.a) The whole work process of prediction and repair system b) The model for predicting the states of the cells in the memory chip by LSTM.The units' states of T N+1 are acquired through the Hidden State calculated by Activation Function softmax and Function argmax.c) The predicted accuracy rate increases with the increase of the training span and finally reaches 86.75%.d) With the prediction span increasing, the accuracy rate decreases.Two prediction spans are acceptable.

Figure 3 .
Figure 3. a) Resurrection algorithm for the predicted failure device.Pulse scheme of one base package for RA.A reset operation executes periodically in the normal programming process.b) CF morphology in different programming stages.This algorithm package is applied multiple times to realize the Vo redistribution in the switching region.Because of the synergistic effect of the prediction model and resurrection algorithms, the percentages decrease by c) 35% for "real fail" devices, d) 26%, and 32% for two groups of "fake fail" devices.e) The recovery rates for two groups of "fake fail" devices increase by 43% and 68%, respectively.

Figure 4 .
Figure 4.During the relaxation process, the standard deviation of different target resistance values varies with relaxed time after the device operates for different cycles: a) 1 cycle, 100 cycles, 500 cycles, and 1000 cycles.The relaxation of the memory array becomes severe with increasing relaxation time, target resistance value, and cycle number.b) Statistical distribution and c) fitted normal distribution of HRS during the relaxation process.The tail bits gradually increase with time and reach 22%.d) Statistical distribution and e) fitted normal distribution of HRS values after applying the RA.

Figure 5 .
Figure5.a) The accumulation probability of the HRS after 300 h baking at 125°C.Tail bits increase with the increasing number of programming cycles.b) By using the optimized programming algorithm (RA) with 15 cycles of the base package, tail bits are significantly reduced from 33% to 14.6% after 300 h baking at 125°C.