Pulsed I–V Analysis of Slow Domain Switching in Ferroelectric Hf0.5Zr0.5O2 Using Graphene FETs

In this study, the domain switching mechanism of ferroelectric HZO thin films is investigated by analyzing the bulk charge of a graphene field‐effect transistor with an HZO dielectric device by using a pulsed IV measurement method. The domain switching speed, which is generally difficult to observe from a typical DC‐IV analysis of metal‐oxide‐semiconductor field‐effect transistors using a parameter analyzer, is investigated via the fast pulsed IV analysis method. Based on the measurements, most of the ferroelectric HZO domains are fast switched within 100 ns; however, domains that require a longer switching time in the order of 1 ms are also identified. Short pulses can be continuously applied to minimize the influence of other domains that are not switched by the switched domain. The feasibility of partial switching of the domains, which can be utilized for the multi‐functional operation of ferroelectric HZO devices, is observed. The results suggest that further investigation of the physical properties of slow‐switching domains is necessary to develop future synaptic array applications.


Introduction
Recent advancements in semiconductor device technology have led to improved operational performance via physical scaling. [1,2]owever, further performance enhancement has been limited by the need to maintain the power consumption per unit area at approximately 100 W cm −2 .5][6][7][8][9][10] Most recently, ferroelectric HfZrO (HZO) FETs have been used to improve swing [11][12][13][14][15][16][17][18][19][20] and implement progressive conductivity modulation for synapse operation.The L. Chen group achieved excellent spike-amplitude dependent plasticity (SADP) and spike DOI: 10.1002/aelm.202300511-rate dependent plasticity (SRDP) by exploiting the pulse linearity and polarization-voltage curve durability in ferroelectric field-effect transistors (FeFETs) combined with a WS 2 -channel and HZO dielectric structure. [21]Additionally, M. Si proposed a mechanism related to hysteresis behavior as a function of the thickness of ferroelectrics. [22]erroelectric analysis methods analyze the polarization value using the positiveup negative-down (PUND) method or grasp the overall characteristics of the ferroelectric by comparing the polarization value while changing the amplitude and pulse width. [23,24]Thus, the absolute polarization value of the ferroelectric can be determined; however, there are limitations to analyzing its effects on an actual device and the manner in which the domain changes.The ferroelectric polarization effect from the pulse can be observed; however, there is a limitation in analyzing the state of the domain change in real-time.Although the domain of ferroelectric HZO thin film exhibits an extremely fast operating speed when a considerably higher voltage than the coercive voltage is applied or in a small area with a relatively large crystalline phase.In the case of a general V DD section or in many polycrystals, the influence of slowly changing domains cannot be ignored. [25]Based on previous research that measured the charging effects via pulsed-IV analysis, we compared the effect on the transconductance of a graphene feild effect transistor (GFET) device by analyzing the relationship between the dipole charge and the interface trap using a pulse and analyzing the operating mechanism of a ferroelectric HZO thin film. [26]However, the analysis of the effect on a single pulse is lacking in the analysis of each slow domain change based on the electric field.
In this research, we analyze the change in the saturation current of a GFET device using a ferroelectric HZO gate dielectric by applying a pulse bias that changes the ferroelectric polarization.The reason for using a GFET lies in its sensitive response to external electric fields compared to the metal-ferroelectric-metal structure.Additionally, the electrical conductivity of graphene exhibits a linear change in response to the polarization of ferroelectrics or trapped charge.[28] Moreover, we observe the operating mechanism by monitoring the real-time HZO

Experimental Section
Figure 1a shows the device fabrication process flow.A 50 nm oxide trench pattern was formed on an SiO 2 (300 nm)/Si substrate via a reactive ion etching process.Subsequently, 50 nm TiN was deposited inside the trench using a sputtering system.A buried gate electrode was then formed by planarizing using chemical and mechanical polishing processes.The buried gate structure was used to apply a uniform electric field across the channel region.Subsequently, 10 nm HZO was deposited via an atomic layer deposition (ALD) process.Tetrakis(ethylmethylamino)hafnium (TEMAHf) and tetrakis(ethylmethylamino) zirconium (TEMAZr) precursors per each cycle were introduced in sequence at 250 °C, followed by rapid annealing at 500 °C for 30 s in an N 2 atmosphere to obtain high-quality ferroelectric thin film structures.A chemical vapor deposition (CVD) graphene sheet was transferred on top of the HZO layer via a vacuum transfer method to ensure stable and consistent device operation. [29]he graphene channel region was patterned using a photolithography process and graphene etching process using O 2 plasma after covering the entire graphene region with a thin metal hard mask (Au 30 nm). [30] An Au hard mask layer was used to eliminate the photoresist (PR) residues on the graphene channel region, which often increases the device stability and performance.Subsequently, an additional Au contact metal (100 nm) was deposited onto the source and drain region via an E-beam evaporation process.Following that, a 30 nm Au wet etching process was performed to etch off the hardmask layer, which opened the channel region of graphene between the source and drain metal region.A part of Au hardmask covering the source and drain region remained because it was covered by the second Au metal layer.The final device structure can be seen in the scanning electron microscopy image depicted in Figure 1a.

Device Fabrication
A 50 nm oxide trench pattern was formed on an SiO 2 (300 nm)/Si substrate via a reactive ion etching process.Subsequently, 50 nm TiN was deposited inside the trench using a sputtering system to form a buried gate electrode with significant advantages over other structures in terms of the uniformity of the electric field applied to the channel region.On planarizing the gate electrode using chemical and mechanical polishing processes, 10 nm HZO was deposited via a ALD process.
TEMAHf and TEMAZr precursors were deposited alternately in one cycle at 250 °C to obtain high-quality ferroelectric thin film structures.Thereafter, rapid annealing treatment was performed at 500 °C for 30 s in an N 2 atmosphere to crystallize the ferroelectric HZO thin film.
Subsequently, CVD graphene sheets were transferred via a vacuum transfer method to ensure stable and consistent device operation as it can reduce impurities, such as oxygen and moisture, between the graphene and the substrate.The graphene channel was patterned via a photolithography process using a metal hard mask (Au) to prevent PR residues on the graphene channel that may occur when patterning the graphene channel using O 2 plasma.Finally, source and drain electrodes (Au) were formed via an E-beam evaporation process and wet etching.

Characterization and Analysis
For the overall ferroelectric HZO component analysis, SIMS (Cameca, IMS 6F) was employed to analyze the components of Hf, Zr, O, Ti, and N. Additionally, XRD (Rigaku, SmarLab) was performed to analyze the crystal structure of the ferroelectric thin film and the crystal state of the TiN thin film based on the temperature.
The P-V curves of metal-ferroelectric-metal HZO were measured by using a ferroelectric tester (Radiant Technologies Inc. Precision Premier).The ideal ferroelectric properties of annealed HZO thin film with a remanent polarization of ≈15 μC cm −2 and coercive voltage of ≈3 V were obtained.Electrical characteristics, including DC-IV and pulsed IV, were measured using a semiconductor parameter analyzer (Keithley 4200 with a pulse measure unit).

Results and Discussion
The secondary ion mass spectroscopy (SIMS) profile of a 10 nm HZO film deposited using the ALD process indicates that the concentrations of Hf and Zr are similar, as depicted in Figure 1b.The higher oxygen concentration can be explained by the matrix effect.X-ray diffraction (XRD) analysis reveals a transition in the crystallinity of HZO as a function of the annealing temperature, as shown in Figure 1c.Specifically, an orthorhombic crystal structure peak, which indicates the ferroelectric characteristics of HZO, was not observed when the annealing process was performed at 450 °C.The structural change occurs at temperatures of 500 °C or higher, as indicated by the XRD analysis.Following annealing at 550 °C, a strong (111) peak was observed, indicating the presence of an orthorhombic phase.We formed ferroelectric films with random domain orientations to investigate the effect of charge trapping.Consequently, we selected the 500 °C annealing condition, which appears to have a less uniform crystal structure.The polarization-voltage curve demonstrates less perfect but decent quality ferroelectric characteristics of the HZO film annealed at 500 °C, as illustrated in Figure 1d.The P-V curve shows V c = ±3 V and 2P r = 30 μC cm −2 .
The typical I-V (current-voltage) curves of a graphene FET exhibit V-shaped transfer characteristics, which arise from the hole conduction on the left side and electron conduction on the right side because the external electric field in the zero-bandgap structure changes the Fermi level position.The Dirac point, which denotes the point at which the carrier type switches from electron to hole or vice versa, while concurrently reaching the minimum density of states (ideally zero, though residual charge facilitates carrier conduction in real scenarios), corresponds to the minimum current point.
Figure 2a illustrates the variations in the I-V curve of the theoretical graphene FET device based on the type of gate dielectric employed.When a conventional gate dielectric is utilized, charge trapping occurs during the gate bias sweep, resulting in a reduction in current owing to the presence of trapped charges.Consequently, the V Dirac point shifts toward the left side.Conversely, when a ferroelectric material is used as the gate dielectric, the current increases owing to ferroelectric polarization and maintains a certain level.Subsequently, a rapid change in current is observed as the V Dirac point shifts toward the right side during the polarization change.In practical scenarios, graphene is often exposed to the air without a passivation layer, resulting in a natural p-type doping effect caused by moisture or oxygen.Consequently, the current in the electron branch is lower than that in the hole branch.
The I-V characteristics of the graphene FET were analyzed using both DC-IV and pulse I-V measurements performed using a Keithley 4200 with a PMU system (Figure 2b) while increasing the bias from −5 to 10 V, as depicted in Figure 2c,d.The results show that the rise time of the pulse applied to the gate affects the V Dirac values, which shifts toward a positive bias with decreasing rise time, indicating a higher hole doping in the channel and more electron charging in the HZO.At a rise time of 10 μs, the HZO did not respond to the change in gate bias.Conversely, in the case of reverse sweeping, the V Dirac values shift toward a negative bias, indicating higher electron doping in the channel and less electron charging in the HZO.
The density of states of graphene exhibits a nearly linear behavior in the low V g region, which enables the separation of the two contributions of charge traps and ferroelectric dipole charges by measuring the devices at different time scales using the pulse I-V method.The results suggest that certain hysteresis-free ferroelectric FETs reported in the literature only operate within a specific frequency range (DC to 1 kHz), with limited balance between charge trapping and dipole switching.Notably, the pulse measurement revealed that the saturated current of the graphene device decreased as the rise time of the applied pulse decreased.Theoretically, when the ferroelectric domain undergoes rapid switching, the single-crystal HZO thin film should respond well even to short pulses, and there should be no significant difference in the current saturation of the GFET device.However, the actual HZO thin film produced has a polycrystalline structure, and the saturation current is reduced by partially switching domains using an externally applied bias.Therefore, a sufficient pulse width is necessary, similar to the application of a DC bias, or multiple pulses are required to change a region where polarization does not occur.
Figure 3 illustrates the transient responses of GFETs to short gate pulses.The pulses, ranging from -4 to +8 V or 4 to −8 V, are applied to facilitate dipole switching.The base bias and pulse height were determined based on the hysteretic I-V characteristics shown in Figure 2. The temporal dependence of the saturation current during the pulse duration was monitored at +4 or −4 V, respectively.At this bias, the majority of dipoles are expected to be polarized.The pulse durations, 0.1, 1, and 10 ms, were determined considering the typical time constant of charge trapping in the order of microseconds to milliseconds and dipole switching in the order of nanoseconds to microseconds.In addition, the rise time of the pulse was set to 10% of the pulse width considering the changing polarization of the ferroelectric during the pulse duration.Initially, it was expected that the influence of dipole switching would saturate much faster than the charge trapping.In fact, the difference can be used to deconvolute the time dependence of charge trapping and dipole polarization, primarily because the influences of dipole switching and charge trapping on the drive current appears in opposite directions.The positively polarized dipole attracts electrons in the channel, increasing the current, whereas the charge trapping accumulated in the interface of HZO and graphene layer reduces the electron concentrations in the graphene channel; thereby reducing the saturation current.
Remarkably, as illustrated in Figure 3, the experimental results exhibit an unusual behavior when a 0.1 ms pulse with a 10 μs rise time was applied to the GFET to switch the graphene into the electron conduction branch.The applied pulse caused a drastic reduction in current during the rise time, which can be attributed to the influences of charge trapping, and the current gradually recovered, indicating the influences of dipole polarization.Since the rise time is already within the timescale that can cause charge trapping in the HZO layer, the initial current drop is expected to be caused by charge trapping.However, the gradual current recovery process in the order of milliseconds is slower than the poling process values reported in the literature.Analysis of the 0.1 and 1 ms pulse cases reveal that the time constant of this poling process takes approximately 150 μs.Based on the amount of current recovery, we can estimate the amount of dipole charge required for the poling process.Considering the full polarization charge is 15 μC cm −2 , the slow switching corresponds to 50% of the total dipole charge.In the case of a 10 ms pulse, an even more intriguing behavior was observed.An additional current increase, with a time constant of ≈1 ms, was observed within 4-5 ms.The observation suggests that at least three switching processes with different time constants coexist within the HZO layer.The slowest switching process, which is the last to occur, requires further investigation because it is likely to be associated with the interaction with charge trapping or a physically existing mechanism that occurs in specific domain structures.
Switching into the hole conduction branch may yield even more interesting results, as it is widely known that hafniumbased high-k dielectrics exhibit pronounced charge trapping in positive bias regions, with detrapping primarily occurring in Figure 5. Schematic of the polarization switching mechanism by pulsed IV measurement.In the reset state, the domain polarization of the ferroelectric is arranged in the same direction, and the cases where a short pulse is incident twice and a long pulse is incident once exhibit similar polarization changes.Additionally, this process can be observed in the same manner as the pulse continues.
negative bias regions.Thus, the impact of charge trapping should be less pronounced during negative pulse application.As explained previously, the difference between the minimum and peak current is much higher in the hole branch compared to the electron branch, indicating that the influence of charge trapping is small and that the influence of dipole switching is much more pronounced.The time constant of dipole switching, as shown in Figure 3, is 150 μs, and the amount of dipole charge is 27% of the total charge.The differences in dipole charge between the curve shown in the hole and electron branches may be caused by the dipole charges compensated by concurrent electron trapping.Therefore, the influence of concurrent charge trapping in positive bias regions should be considered when analyzing the ferroelectric switching mechanism.
For the 1 and 10 ms pulse cases, a similar analysis can be conducted, and the time constants obtained from the two curves are 1 and 4 ms, respectively.The analysis for these cases is similar to that of the positive pulse case described earlier.Interestingly, a current hump or dip owing to extremely slow ferroelectric switching behavior was observed at 0.75, 4-5, and 8 ms.Given the presence of weak charge trapping, this behavior may indicate dynamic depolarization behavior resulting from the progressive alignment of dipoles.Extensive investigations are required to better comprehend the underlying mechanisms of this behavior and its potential implications on the operation and performance of ferroelectric FETs.
Furthermore, the programming behavior of ferroelectric HZO was examined, wherein Figure 4 illustrates the dipole switching that occurred at +4 V through the application of a triangular pulse (with a rise/fall time of 10 μs).The degree of poling was monitored by observing the current at V g = 0 V.The difference in current between the pulses reflected the extent of poling.Following the application of nine triangular pulses, the current gradually increased until the 3rd pulse was applied, then stopped for a while.The 7th pulse was applied, and the current increased again and reached saturation after the 8th pulse was applied.In the subsequent investigation, we examined the programming behavior of ferroelectric HZO using rectangular pulses with varying pulse widths and fixed rise/fall times of 10 μs each.When the pulse width was increased to 50 μs, only the 4th pulse was capable of saturating the current level of the GFET, while the 2nd pulse exhibited a peak current and then decreased when a 100 μs pulse width was applied.Through the pulse measurements, it was found that 50% of the dipole could be rapidly switched within 50 μs, while the remaining 50% required a longer pulse.A more detailed domain change trend was observed when a shorter pulse was applied.Half of the domain changed when a triangular pulse of 10 μs was applied thrice, and most of the domain changed when the pulse was applied seven times.Similarly, applying one long pulse or several short pulses had the same effect on the polarization change of the ferroelectric domain.The pulse analysis demonstrates that the polarization of the ferroelectric was arranged within 0.5 to 1 ms, and additional changes occurred based on the bias applied time.Moreover, the domain was partially changed at the pulse level of 10 μs.Thus, applying short pulses several times plays a crucial role in polarization arrangement.It can be concluded that the slowly changing ferroelectric domain is much larger than the domain that responds to fast pulse operation of 10 μs or less.
Figure 5 illustrates that the polarization of the ferroelectric domain can be modeled easily.In the reset state, the domain polarization is aligned in the same direction, and applying a short pulse twice or a long pulse once results in similar polarization changes.This trend can also be observed as the pulse is repeated.Consequently, the HZO ferroelectric can have multiple functions when polarization is controlled using short pulses, and the linearly formed polarization can be utilized as a new synaptic device.Additionally, the polarization rate can be adjusted based on the pulse width, implying the potential for use in a new device structure.

Conclusion
In this study, the pulsed IV measurement method was utilized to analyze the domain switching mechanism of Ferroelectric HZO thin film, and partial switching of domains was observed based on the electric field, indicating the potential for multifunctional operation of the material.This method allows for the non-destructive assessment and analysis of the quantity of slowly responding domains within ferroelectric HZO thin films, particularly in the context of polycrystalline films.Through our research, we have gained valuable insights into how these domains change over time during the application of an electric field, and we have assessed the influence of the number of pulses on these changes.It was concluded that HZO ferroelectrics can exhibit multi-functions via polarization control using short pulses, with the ability to linearly form polarization, making it suitable for use as a new synaptic device.The polarization rate can also be controlled by adjusting the pulse width, indicating the potential to use the material in innovative device structures.

Figure 1 .
Figure 1.a) Schematic of the device fabrication process flow, b) SIMS profile of the ALD HZO thin film, c) XRD spectrum of orthorhombic HZO annealed at different temperatures from 450 to 550 C, and d) P-V curves of Ferroelectric HZO annealed at 500 C. The ferroelectric properties of the fabricated HZO thin film can be confirmed through a component analysis of the 10 nm thick HZO thin film via the ALD process, XRD, and P-V curve trend.

Figure 2 .
Figure 2. Typical transient curve of GFET and the difference in the saturation current based on the pulse width.a) Theoretical transient curve of GFET with dielectric and ferroelectric layer, b) Pulse I-sV system, c) I d -V g curves of GFETs with DC bias; d) I d -V g curves of GFETs with pulse at V amp = 10 V, V base = −5 V, V amp = −10 V, and V base = 5 V.As the pulse width becomes shorter, the V Dirac of the GFET device moves and the saturated current gradually decreases.

Figure 3 .
Figure 3.Time versus drain current curve over time while a pulse is applied.The charge generated by V amp = 8 V with pulse width of 0.1 ms is 2.38 × 10 −9 , 4.24 × 10 −8 C at 1 ms and 1.06 × 10 −6 C at 10 ms.When V amp = −8 V is applied, the charge generated in the pulse width of 0.1 ms is 6.5 × 10 −9 C, calculated as 3.9 × 10 −8 C at 1 ms and 4.14 × 10 −7 C at 10 ms.

Figure 4 .
Figure 4. Three types of applied pulses: t r = 10 μs, t w = 0 μs (triangular pulse), t r = 10 μs, t w = 50 μs (rectangular pulse), t r = 10 μs, and t w = 100 μs (rectangular pulse), as well as the change in the drain current after several pulses are applied.As the number of applied pulses increases, the drain current increases, and the polarization of the HZO thin film changes based on the number of pulses.