Reconfigurable Logic‐In‐Memory Cell Comprising Triple‐Gated Feedback Field‐Effect Transistors

A reconfigurable logic‐in‐memory (R‐LIM) cell performs logic‐in‐memory functions as well as reconfigurable logic gates. The R‐LIM cell is constructed with triple‐gated (TG) feedback field‐effect transistors (FBFETs) that are reconfigured in n‐channel or p‐channel modes via electrostatic doping. Each TG FBFET has one control gate electrode and two program‐gate electrodes that determine the channel mode. Their reconfigurability enables the symmetrical operation of the n‐channel and p‐channel modes through an on‐current ratio of 1:04. Furthermore, the R‐LIM cell performs eight Boolean logic operations, storing the logic outputs for ≈100 s under zero‐bias conditions. The R‐LIM cell is useful for developing in‐memory computing systems with high energy efficiency and functional logic.


Introduction
[6][7][8] In conjunction with LIM computing, reconfigurable logic gates have emerged as a new computational logic mode. [9,10][13] Combining reconfigurable logic gates and LIM is crucial to extend the functionality of next-generation electronics.
Feedback field-effect transistors (FBFETs) are promising components of LIM because of their excellent switching and DOI: 10.1002/aelm.202300526[20][21][22] Moreover, FBFETs can also be utilized for reconfigurable logic gates with multi-gated structures.25][26][27] We design a reconfigurable LIM (R-LIM) cell with eight triple-gated (TG) FBFETs and examine the memory characteristics and performance of eight Boolean logics (YES, NOT, AND, OR, NAND, NOR, XNOR, and XOR gates).Each TG FBFET has one controlgate (CG) electrode and two program-gate (PG) electrodes that determine the channel mode; the CG electrode is located between the PG electrodes.Unlike the single-gated structure that configures cells differently for each logic operation, the doubleor triple-gated structure performs reconfigurable logic operations in a single cell.Furthermore, compared with the double-gated structure, the triple-gated structure has the advantage with respect to actual chip fabrication because this structure does not require additional circuits to switch the gate role; for the doublegated structure, additional circuits are needed because the roles of the two gates should be switched whenever the channel mode needs to be changed. [25]Owing to the structural features of TG FBFETs, additional circuits are not required to switch the input gates, depending on whether they operate in the n-channel or pchannel modes, such that R-LIM cells can be designed with fewer transistors and higher functionality.The R-LIM cell has been verified through a device simulator, but its realization has not been reported yet. [27]Therefore, in this study, we fabricate the R-LIM cell comprising TG FBFETs and investigate the operating mechanism and electrical characteristics of the TG FBFETs in detail.And we demonstrate the performance of the R-LIM cell.

Device Structures and Operation Mechanisms of Triple-Gated Feedback Field-Effect Transistors
The circuit symbol and schematic of a TG FBFET are shown in Figure 1a; one CG electrode and two PG electrodes are present on the intrinsic region of the p + -i-n + silicon layer.A CG controls the charge carrier injection into the channel, and the two PGs electrically connected determine the channel mode.An optical image of a fabricated TG FBFET is shown in Figure 1b, and the schematics, energy band diagrams, and circuit symbols are illustrated in Figure 1c.The TG FBFET can be reconfigured in either n-channel or p-channel mode by the polarity of the PG voltage (V PG ).When a positive V PG and negative CG voltage (V CG ) are applied to the gate electrodes, the n-channel mode operates.The Si layer has a p + -n * -p * -n * -n + structure in which the p + region is a drain, the n * -p * region is a channel, and the n * -n + region is a source region.Here, the n * (p * ) region is an n-type (ptype) region electrostatically doped by applying a positive (negative) gate voltage.In the n-channel mode, the channel injection of charge carriers is initially blocked by the potential barriers generated by V CG and V PG .When V CG and the source voltage (V S ) lower the height of the potential barrier on the source side, electrons flow into the channel and accumulate in the potential well.Similarly, the electron accumulation lowers the height of the potential barrier on the drain side such that holes flow into the channel and accumulate in the potential well.Accordingly, the injection and accumulation of charge carriers are repeated to trigger a positive feedback loop, and the device is rapidly turned on.Next, the Si layer of the device operating in the p-channel mode has a p + -p * -n * -p * -n + structure (in which the p + -p * region is a drain, the n * -p * region is a channel region, and the n + region is a source region) by applying negative V PG and positive V CG .In the p-channel mode, a positive feedback loop is triggered by controlling the channel injection of holes with the drain voltage (V D ) and V CG .

Electrical Characteristics of Triple-Gated Feedback Field-Effect Transistors
Figure 2a shows the output characteristics of the n-channel mode with various V CG values when a V PG of 4.0 V and negative V CG values are applied.Herein, V S is swept from 0.0 to −4.0 V.The device exhibits abrupt increases in current owing to the latch-up phenomenon; the device operates in a positive feedback mechanism, and this mechanism causes the latch-up phenomenon.The latch-up voltage (V latch-up ) shifts gradually (−1.3 → −1.4 → −1.6 → −1.7 → −1.9 V) with a change in V CG (−1.6 → −1.8 → −2.0 → −2.2 → −2.4 V).As V CG increases in the negative voltage direction, the height of the potential barrier (blocking the electron flow from the source) increases such that more electrons are required to turn the device on.In addition, as V S is swept from −4.0 to 0.0 V, abrupt decreases in current are observed, indicating the elimination of the positive feedback loop.Figure 2b shows the output characteristics of the p-channel mode for various V CG values.V latch-up shifts to the higher The transfer characteristics of the n-channel mode for various V S values are shown in Figure 2c.As V CG is swept from −5.0 to 5.0 V, the potential barrier hindering the charge carrier injection is lowered, and the latch-up phenomenon occurs.In addition, , and as V S supplies more electrons, the latch-up phenomenon occurs at a higher potential barrier.Reverse voltage sweeps indicate that the drain-source current (I DS ) is maintained until V CG is swept from 5.0 to −5.0 V.These bistable characteristics imply that as long as V S is supplied, the generated positive feedback loop is not eliminated, even if V CG is reduced to −5.0 V.The transfer characteristics of the p-channel mode in Figure 2d show the variation in V latch-up for various V D values.As more holes are supplied with increasing The maximum on-currents in the n-channel and p-channel modes are 44.15 and 42.58 μA μm −1 , respectively, as depicted in Figure 2c,d.Consequently, the TG FBFET exhibits nearly symmetrical characteristics between the n-channel and pchannel modes with an on-current ratio of 1:04.Moreover, the TG FBFET exhibits excellent switching characteristics with a high ON/OFF current ratio (≈10 7 ) in both channel modes.Furthermore, we examine the transfer characteristics of the n-channel mode operated by V D and the p-channel mode operated by V S (Figure S1, Supporting Information).Notably, in the n-channel mode (the p-channel mode), the TG FBFET is in the ON state at V CG = 4.0 V (−4.0 V) and the OFF state at V CG = −4.0V (4.0 V) regardless of whether V D or V S is used as the supply voltage.These voltage conditions are used to operate the R-LIM cell.Some logic gates share the same circuit topology of the nchannel or p-channel modes in the R-LIM cell, that is, the same circuit diagram.For example, AND/OR/YES gates in Figure 4a and Figure S2a (Supporting Information), are operated in the same circuit topology in which all the elements in the pull-up (pull-down) network are operated in the n-channel (p-channel) mode.In addition, the table shows which input voltages are applied to Elements 1-8 to perform each gate operation.The timing diagrams for each gate operation are shown in Figure 4b and Figure S2b,c (Supporting Information); all voltages are applied with a pulse of 1 ms.

Cell Structures and Logic Gate Operations of Reconfigurable Logic-In-Memory Cell
In the case of the AND gate operation in Figure 4b, Logic Operations 00, 01, 10, and 11 are performed sequentially.Here, V IN1 is applied to Elements 1, 5, 7, and 8, and V IN2 is applied to Elements 2, 3, 4, and 6.When Input Logic 00 is applied, the output logic is 0 because only the elements in the pull-down network are turned on.Next, when Input Logic 01 is applied, Elements 2, 6, 7, and 8 are turned on.Then, the cell returns Output Logic 0 because the p-channel mode Elements 7 and 8 placed in series connect V OUT with V SS .Input Logics 10 and 11 also operate similarly, and the output logics are 0 and 1, respectively.The memory characteristics of the R-LIM cell are shown in Figure 4b for the hold operation.While all voltages are set to zero for 10 ms for the hold operation, V OUT is maintained at the initial output logic value.
Because each element has charge-storage capability, the R-LIM cell exhibits logic retention characteristics that store the output logic value under zero-bias conditions. [17]Moreover, the OR/YES gate operations are performed in the same circuit topology as the AND gate operation by simply changing the combination of input voltages.Their detailed information is described in Figure S2 (Supporting Information).The series/parallel structures formed by the TG FBFETs in the R-LIM cell play a key role in performing these logic operations.For Input Logics 01 and 10 of AND/OR gates, two pull-up and pull-down network elements are turned on.Here, V OUT is only connected to either V DD or V SS because turned-on elements in the pull-up or pull-down networks are connected in series, and turned-on elements on the opposite side are connected in parallel.Accordingly, the series/parallel structures of the R-LIM cell allow Input Logics 01 and 10 to operate properly.
As illustrated in Figure 5a and Figure S3 (Supporting Information), NAND/NOR/NOT gates are operated in the same circuit topology; the pull-up and pull-down network elements operate in the p-channel and n-channel modes, respectively.For the NAND gate operation, V IN1 is applied to Elements 3, 5, 6, and 7, and V IN2 is applied to Elements 1, 2, 4, and 8.The timing diagram in Figure 5b shows the logic and hold operation of the NAND gate.When Input Logic 00 is applied, only the elements in the pull-up network are turned on, and then the output logic is 1.Next, for Input Logic 01, Elements 4, 5, 6, and 8 are turned on, and then the output logic is 1 because V OUT is only connected to V DD by Elements 5 and 6.Similarly, when Input Logics 10 and 11 are applied, the cell returns Output Logics 1 and 0, respectively.NOR/NOT gate operations are also conducted in the same circuit topology as the NAND gate operation.Their detailed information is described in Figure S3 (Supporting Information).Here,   5a has an exactly opposite topology to that of the circuit diagram of the AND/OR/YES gates in Figure 4a. Figure 6 demonstratesthat the XNOR/XOR gates are conducted in the R-LIM cell with independent circuit topologies.These circuit diagrams have two n-channel mode elements and two p-channel mode elements in both pull-up and pull-down networks.First, for the XNOR gate in Figure 6a, the same channel mode elements are connected in series in the pull-up network and parallel in the pull-down network.V IN1 is applied to Elements 1, 4, 5, and 7, and V IN2 is applied to Elements 2, 3, 6, and 8.For the XOR gate in Figure 6b, as opposed to the XNOR gate, the same channel mode elements are connected in parallel in the pull-up network and in series in the pull-down network because the XNOR/XOR gates have opposite output logic values.However, the elements to which V IN1 and V IN2 are applied are the same as those in the case of the XNOR gate.
The timing diagram in Figure 6c shows Input Logics 00, 01, 10, and 11 of the XNOR gate operation.When Input Logic 00 is applied, only Elements 1, 2, 3, and 7 are turned on, and then the output logic is 1.When Input Logic 01 is applied, the output logic is 0 because the turned-on Elements 7 and 8 connect V OUT with V SS .Similarly, Input Logics 10 and 11 result in Output Logics 0 and 1, respectively.The timing diagram of the XOR gate operation in Figure 6d shows the opposite output logic values to those of the XNOR gate operation.When Input Logic 00 is applied, the p-channel mode elements are turned on.Then the output logic is 0 by Elements 3 and 4. Next, when Input Logic 01 is applied, the output logic is 1 because the turned-on Elements 5 and 6 connect V OUT with V DD .Furthermore, when Input Logics 10 and 11 are applied, the output logics are 1 and 0, respectively.Consequently, the XNOR/XOR gate operations show complete output logic values and stable memory characteristics without external bias voltages.
The average energy consumption per operation calculated for all Boolean logic operations is ≈2.57nJ.The energy consumption of the OR 11 operation is the smallest at ≈1.54 nJ, and the energy consumption of the NOR 10 operation is the largest at ≈3.69 nJ.The energy consumption of each logic operation is not significantly different because the R-LIM cell performs all the Boolean logic operations in a single structure.The main cause of the energy consumption is the short-circuit current in the logic transitions.Nevertheless, no energy is consumed during the hold op-eration because the R-LIM cell maintains the output logic values under zero-bias conditions.
Table 1 shows the comparison of operating characteristics of various reconfigurable logic gates.In terms of the efficiency of reconfigurable logic, it is important to implement several logic gates with a small cell area and fewer components.With regard to the components and the number of reconfigurable logic gates, our R-LIM cell is superior to others.The R-LIM cell performs LIM operations of eight different Boolean logic gates with relatively few components.In addition, the reconfigurable logic gates of most other studies require additional input inverters and some changes in cell configurations, which causes circuit complexity or overload.In contrast, the R-LIM cell performs all Boolean logic operations without any input inverters and any changes in a single-cell configuration.

Logic Retention Characteristics of Reconfigurable Logic-In-Memory Cell
Figure 7 shows the logic retention characteristics of the R-LIM cell for the XOR gate.We increase the hold operation time to 100 s to confirm the logic retention of Output Logics 1 and 0. All input logic pulses are applied for 1 ms, and then an external voltage of 0 is applied for 100 s.For the XOR gate in Figure 7, the voltage values of Output Logics 1 and 0 are maintained at 75.47% and 48.08% of the initial V OUT , respectively.The retention char- acteristics of Output Logics 0 and 1 should be the same, because of the configuration of eight TG FBFETs in the R-LIM cell; the configuration of the pull-up network elements is symmetrical to that of the pull-down ones.Despite of this, Figure 7 shows that the retention characteristic of Output Logic 0 has a little variation before 20 s in comparison with that of Output Logic 1.One possible reason for the difference in the retention characteristics of Output Logics 0 and 1 is the different types of charge carriers mainly involved in the logic retention characteristics.For Output Logic 0, electrons are injected and accumulated in the channel regions of the TG FBFETs by a negative source voltage.Conversely, for Output Logic 1, holes are injected and accumulated in the channel regions of the TG FBFETs by a positive drain voltage.Consequently, electrons and holes are mainly involved in the retention characteristics of Output Logics 0 and 1, respectively.Herein, the channel region is lightly p-doped with 10 16 cm −3 , and thereby the recombination rate of electrons is faster than that of holes.Therefore, Output Logic 0 has a little variation while Output Logic 1 is relatively stable.The logic retention time is expressed as the time until the V OUT decreases to 37%.For the XOR logic gate, the R-LIM cell has a long logic retention time of over 100 s.The logic retention characteristics of the AND/OR/YES, NAND/NOR/NOT, and XNOR gates are presented in Figure S4 (Supporting Information), and all the logic gates have a logic retention time of almost 100 s.In addition, the simulated retention characteristics for the XOR logic gate at different temperatures are shown inFigure S5 (Supporting Information), indicating that the high-temperature (360 K) retention can be significantly reduced, compared with the low-temperature (300 K) one.
The operating speed is inherently limited because of the retention (over 100 s); the retention originates from the maintenance of the accumulation or the depletion of charge carriers in the channels of the TG FBFETs.Nevertheless, the operating speed can be enhanced by introducing additional pulses between logic operations to return the TG FBFETs to the initial states.In our previous work, the operating speed of an inverter consisting of FBFETs was enhanced from a voltage pulse of 1 ms to a voltage pulse of 1 ns by applying a reset operation. [26]By applying the reset pulse prior to the logic operation, the R-LIM cell can perform the logic operation at a faster speed.Figure S6 (Supporting Information), shows that the TG FBFETs have memory characteristics.On the other hand, the retention time of the TG FBFETs differs from that of the R-LIM cells.The retention time of the TG FBFETs is calculated by applying the write, hold, and read operations.Although charge carriers are accumulated in the channel in the write ON operation if the charge quantity drops below a certain level due to recombination, no current flows when the read voltage is applied.In contrast, the retention time of the R-LIM cell is calculated by continuously measuring the V OUT without read voltage.Here, the elements of the R-LIM cell operate like capacitors, thereby preventing a sudden change in voltage.Thus, the difference in retention time between the TG FBFETs and R-LIM cells is caused by differences in the measurement methods.

Conclusion
We designed an R-LIM cell comprising TG FBFETs that can be reconfigured in n-channel and p-channel modes.In the reconfigurable logic gate operations, the n-channel and p-channel modes show their symmetrical switching characteristics, and the oncurrent ratio is very low at 1:04.Their reconfigurability enables to perform logic operations of the AND, OR, YES, NOT, NAND, NOR, XNOR, and XOR gates in a single R-LIM cell, and some logic gates have the same topology as the channel modes.Furthermore, all logic gates exhibit logic retention times of ≈100 s with zero static power consumption.

Experimental Section
Device Fabrication: The TG FBFETs were fabricated on a p-type (100)oriented silicon-on-insulator wafer with a 100 nm-thick silicon active layer (doping concentration of ≈10 16 cm −3 ).First, a silicon dioxide gate dielectric layer with a thickness of 25 nm was grown on the active layer.A 400 nmthick poly-silicon layer was deposited by low-pressure chemical vapor deposition (LPCVD) and etched with a 1 μm gap by a dry etching process to create a TG structure.The CG was 2 μm long, and the two PGs were 3 μm long.Gate sidewall spacers were formed using a tetraethyl orthosilicate (TEOS).For heavy n-doping, the source and PG regions were implanted with 3 × 10 15 cm −2 of P + ions at 50 keV.Similarly, the drain and CG regions were implanted with 3 × 10 15 cm −2 of BF 2 + ions at 40 keV for heavy p-doping.Subsequently, a rapid thermal annealing was performed at 1050 °C for 30 s.After interlayer dielectric deposition using TEOS, the drain, source, and gate electrodes were formed using a metal alloy composed of Ti/TiN/Al/TiN.

Figure 1 .
Figure 1.Device structures and operation mechanisms of TG FBFETs.a) Schematic and circuit symbol of TG FBFET.b) Optical image of TG FBFET.c) Schematics, energy band diagrams, and circuit symbols of reconfigurable n-channel and p-channel modes.

Figure 2 .
Figure 2. Electrical characteristics of TG FBFETs.a) Output characteristics of n-channel mode under various V CG .b) Output characteristics of p-channel mode under various V CG .c) Transfer characteristics of n-channel mode under various V S .d) Transfer characteristics of p-channel mode under various V D .

AFigure 3 .
Figure 3. Structure of R-LIM cell.a) Circuit diagram of R-LIM cell.b) Optical image of R-LIM cell.

Figure 4 .
Figure 4. AND gate operation of R-LIM cell.a) Circuit diagram of AND gate and a table summarizing which input voltages are applied to Elements 1-8 to perform AND gate operation.b) Timing diagram of AND gate operation with hold operation.

Figure 5 .
Figure 5. NAND gate operation of R-LIM cell.a) Circuit diagram of NAND gate and a table summarizing which input voltages are applied to Elements 1-8 to perform NAND gate operation.b) Timing diagram of NAND gate operation with hold operation.

Figure 6 .
Figure 6.XNOR and XOR gate operations of R-LIM cell.a) Circuit diagram of XNOR gate and a table summarizing which input voltages are applied to Elements 1-8 to perform XNOR gate operation.b) Circuit diagram of XOR gate and a table summarizing which input voltages are applied to Elements 1-8 to perform XOR gate operation.c) Timing diagrams of XNOR gate operation with hold operation.d) Timing diagrams of XOR gate operation with hold operation.

Figure 7 .
Figure 7. Logic retention characteristics of R-LIM cell for XOR gate.

Table 1 .
Comparison of operating characteristics of reconfigurable logic gates.