Electrolyte‐Gated Vertical Transistor Charge Transport Enables Photo‐Switching

Proposals for new architectures that shorten the length of the transistor channel without the need for high‐end techniques are the focus of very recent breakthrough research. Although vertical and electrolyte‐gate transistors are previously developed separately, recent advances have introduced electrolytes into vertical transistors, resulting in electrolyte‐gated vertical field‐effect transistors (EGVFETs), which feature lower power consumption and higher capacitance. Here, EGVFETs are employed to study the charge transport mechanism of spray‐pyrolyzed zinc oxide (ZnO) films to develop a new photosensitive switch concept. The EGVFET's diode cell revealed a current‐voltage relationship arising from space‐charge‐limited current (SCLC), whereas its capacitor cell provided the field‐effect role in charge accumulation in the device's source perforations. The findings elucidate how the field effect causes a continuous shift in SCLC regimes, impacting the switching dynamics of the transistor. It is found ultraviolet light may mimic the field effect, i.e., a pioneering demonstration of current switching as a function of irradiance in an EGVFET. The research provides valuable insights into the charge transport characterization of spray‐pyrolyzed ZnO‐based transistors, paving the way for future nano‐ and optoelectronic applications.


Introduction
Transistor is the cornerstone of electronic circuits, acting as the main component in logic gates, ring oscillators, inverters, and amplifiers.However, the need to constantly shorten the device's channel length has been a bottleneck in achieving increasingly better-performing devices.Generally, the most common strategies for producing short-channel transistors require complex and costly techniques, such as electron beam lithography and high-energy-ion implantation. [1]As alternatives, new device architectures and materials technologies have emerged to shrink the channel length and improve transistor performance without requiring extremely precise and expensive techniques.Hence, the transistor family constantly diversifies with brand new members, especially the vertical fieldeffect transistor (VFET), one of the most promising devices to provide channel lengths with cost-effective and extreme miniaturization.VFETs are fabricated by vertically stacking conductive, dielectric, and semiconductor layers, similar to piling up a Schottky diode and a capacitor that share an intermediate electrode.[6] These features make VFET the most suitable platform for plenty of functional applications using natureinspired and bio-compounds, [7] highly stretchable/flexible, [8] and transparent [9] materials.Considering photodetectors, it is advantageous to achieve short channel lengths to ensure that upon the generation of excitons, the dissociated charge carriers can traverse shorter distances to the electrodes, thereby mitigating the recombination rate. [93]he versatility of VFETs is already a promising benchmark for providing scalability and facilitating integration with other electronic components that share the same hierarchical fabrication concepts, viz.light-emitting devices, [10] non-volatile memories, [11] and radio-frequency identification tags. [12]he electric field permeability of the VFET's intermediate electrode is an important aspect to be considered during device design and materials selection.This property allows the semiconductor layer to be influenced by the gate, which in turn controls the current flow through the transistor's channel using voltage.Nanowires, [13] nanotubes, [14] and 2D compounds [15] are suitable to play the role of intermediate electrode materials.The gate insulator's dielectric properties are also crucial.The use of nanostructured dielectrics, which eventually deliver low capacitance while requiring high gate voltages, often represents a potential bottleneck for printed and flexible VFETs.Thereby, the recent addition to the transistor family, viz. the electrolyte-gated fieldeffect transistor (EGFET), has successfully addressed the challenge of achieving scalability and materials integration to the next generation. [16][19] The device that merges the VFET and the EGFET is the so-called electrolyte-gated vertical field-effect transistor (EGVFET).Despite being a recent proposal, EGVFET has demonstrated continuous operation at a current density magnitude of 10 6 A cm −2 , [20] as well as in multisensory artificial synapses. [21]The cost-effectiveness of fabricating and integrating different functional materials within VFET architectures ultimately depends on the choice of semiconductor material.
Focusing on nano-and optoelectronics, zinc oxide (ZnO) has stood out as an interesting option due to its solution processability and outstanding optoelectronic properties.ZnO allows optoelectronic applications within the UVA spectrum (320 -420 nm) due to its wide bandgap of 3.35 eV, [22] being it widely exploited as an active layer in photovoltaic cells, [23] Schottky diodes, [24] transistors, [25] gas sensors, [26] photodetectors, [27] and memristors. [28]Emphasizing the transistor applications, ZnO films have been used in several device architectures, viz.inplane gated transistors (IPGTs), [25] VFETs, [29] EGFETs, [30] and more recently EGVFETs. [18]It can be deposited by several techniques, from the most sophisticated ones, such as vacuum thermal evaporation, [31] to the lowest cost routes, such as spray pyrolysis from precursor solutions. [32]However, ZnO films obtained from precursor solutions (viz.zinc nitrate, zinc acetate, zinc chloride, etc.) are generally defect-rich, causing unintentional n-type doping through the formation of shallow donor levels. [33]These features significantly affect the electrode/semiconductor interface, impacting the charge transport properties of the transistor channels.A persistent lack arises from understanding the transport properties of spray-coating technology, which is at the heart of most interest in low-cost and large-area electronics, [34] to produce functional semiconductors for the emerging VFET and EGVFET technologies.Common defects in ZnO include zinc vacancy, zinc interstitials, oxygen vacancy, voids, and cluster defects, [35,36] In this scenario, the study of the charge transport in spray-coated ZnO films using already-assembled transistor platforms may elucidate the device operation dynamics, which is in turn the key to enhancing spray-coated ZnO properties.Even more decisively, we argue that the comprehension of the charge transport dependence on the gate's electric field will undoubtedly be insightful for the next generation of phototransistor-and radiation-sensor applications of EGVFETs. [37]The ability to control the transistor channel through photo-switching not only re-lies on the intrinsic properties of the materials but also on understanding charge transport mechanisms at interfaces and in the bulk.For example, the electrical current flow through ZnO is significantly affected by factors, such as the high density of defect states that can promote trapping and de-trapping processes, thereby reducing the mobility and lifetime of the photogenerated carriers. [38]n this work, we explore charge transport in EGVFETs employing a spray-coated ZnO/silver-nanowire (ZnO/AgNW) Schottky diode as an active cell, and a cellulose-based electrolyte as the gate dielectric.First, we investigated the stand-alone Schottky diode employing Ohm, Mott-Gurney, and Mark-Helfrich, [35,39] formalisms, obtaining information about its electron mobility and density of traps.Then, we investigate the diode cell within the EGVFET using differential resistance, Norde generalized, and Cheung's methods. [40,41]We used gate voltage and an external radiation source as an alternative approach to study the transport mechanisms, since severe temperature variations may cause tricky implications for the electrolyte.Our findings reveal that the electric current switching of ZnO EGVFETs can be triggered by UV irradiance, which is interesting in UV-detector phototransistor applications.Our devices demonstrate the successful integration of efficient diode and capacitive cells into a newly developed EGVFET, providing insights into the significance of spray-coating techniques for next-gen nano-and optoelectronics applications.

Results and Discussion
To provide a clear visualization of the ZnO-based EGVFET, Figure 1a-d exhibits the device's counterpart morphology, profilometry, and assembly sketches.The typical ZnO film height profile, acquired by profilometry, is exhibited in Figure 1a, allowing the measurement of an average thickness of ≈ 200 nm with low roughness and high uniformity along the lateral distance of the sample.Figure 1b displays an atomic force microscopy (AFM) image acquired from the AgNW electrode that was previously deposited (spray-coating) on the ZnO thin film.In this topography, one may notice that the percolated AgNWs result in a randomly network-like formation, in which the uncovered area ensures the transparency and permeability features.Figure 1c exhibits the height profile obtained from Figure 1b, where the AgNW thickness can be easily visualized.It is worth mentioning that the AgNW film sheet resistance was measured as ≈ 10 Ω sq −1 by a four-point probe, which is ideal for intermediate electrodes featuring electric field permeability functions, [44] as required by the vertical architecture of the EGVFET.As the AgNW film is a perforated electrode, its effective area is smaller than the geometric area delimited by a shadow mask to pattern the electrodes design.For calculation purposes, we considered the device area as the geometric dimension from the shadow-mask area, A = 0.006 cm 2 .A self-standing hydrogel sticker based on cellulose with lithium hydroxide was used as an electrolyte dielectric layer (see the Experimental section for details).The electrolyte dielectric layer provides a high double-layer capacitance of 5 μF cm −2 and ionic conductivity around 10 −3 S cm -1 . [43]A gold wire is positioned over the electrolyte to act as the top-gate electrode, leading to an EGVFET based on an ITO/ZnO/AgNW/electrolyte/Au stack, as depicted in Figure 1d.A sketch of the airbrush performing the spray deposition is also shown in this figure to represent the ZnO film deposition method.
Photoluminescence (PL) is an important technique for providing valuable information about the crystallinity and opticalelectronic properties of materials.Figure 1e presents the PL spectrum from the ZnO film, revealing three major emission peaks: 419 nm (violet), 484 nm (blue), and 536 nm (green).Different synthesis techniques can result in various types of defects, generating energy levels within the semiconductor bandgap and, consequently, different photoluminescence emissions peaks are observed throughout the visible range. [45]Here, we employed the spray deposition technique, which stands out compared to more conventional techniques due to its low cost, compatibility with large-area electronics, rapid manufacturing, and relatively low temperatures (a more detailed comparison is presented in Table S1, Supporting Information).The violet peak is commonly attributed to the transition between the conduction band and zinc vacancies.The asymmetry of the 419 nm peak suggests a superposition of closely located emission peaks.The deconvolution of this peak, presented in the inset of Figure 1e, shows three distinct emission peaks at 390 nm, 416 nm, and 421 nm.The 390 nm peak corresponds to the near band edge transition of ZnO, serving as an indicator of good crystallinity, [46] being responsible for excitonic recombination. [47]The emission peaks at 416 and 421 nm can be attributed to radiative defects related to interface traps, [48] caused by the transition between the trap level and the valence band.The visible peaks represent defect-related luminescence, explained by radiative transitions between donor levels and deep acceptors, [46] which has been correlated to structural defects, such as zinc interstitials, zinc vacancies, oxygen interstitials, and dislocations. [49]The 484 nm emission peak can be related to shallow energy defects or impurities, while the one at 536 nm can be associated with deep transitions from the conduction band to intrinsic defects, such as oxygen vacancies. [50]he investigation of charge transport in ZnO-based devices has been accomplished using Schottky diodes, [35,[51][52][53] and field-effect transistors, [54,55] allowing the evaluation of space charge formation and properties, such as electron mobility and the density of traps.58] The apparent reason is that the electrolytes would degrade under any condition far from the environment temperature.The charge transport investigation in an EGVFET within this frame requires an alternative means (other than temperature) to control charge injection.Here, we investigate the stand-alone diode, and the EGVFET under the gate effect field influence and under illumination as alternatives to investigate the charge transport mechanism.
The Schottky diode counterpart of a vertical transistor is often a bottleneck concerning the envisioned electrical performance, mainly considering high current density, high I on /I off ratios, and low threshold voltages.Accordingly, we fabricated the standalone diode cell and employed it as the device platform for the first investigation of the charge transport mechanism in the ZnO channel.Figure 2a displays the current versus voltage (I-V) curve of the ITO/ZnO/AgNW Schottky diode measured in the dark, under room conditions.The device's small area provided a high on-current density (J on ), J on = 230 mA cm −2 at V = 1.4 V.The I-V profile displays a typical rectifying behavior similar to that predicted by thermionic emission theory, showing no zero displacements and allowing a high rectification ratio, viz.RR ≈ (8.4 ± 5.8) ×10 4 , at V = ± 1.0 V. To further investigate the diode cell properties, we studied the charge transport mechanism across the device.Figure 2b exhibits the I-V plot on a log-log scale, in which the power-law relationship between current and voltage is evidenced, depending on the voltage range.Assuming that I  V m , one may notice that such a dependence can arise from m.This indicates that changes in the conduction mechanism are taking place for increasing V. Particularly, we found m ≈ 1.25 at V < 0.16 V, which is interpreted as typical thermal emission (TE) over the potential barrier occurring during ohmic conduction. [59]In general, for diodes under low positive voltages, the current is expected to increase linearly (i.e., m ≈ 1), following the ohmic behavior, [60] as described by: where n 0 is the density of free charges in thermal equilibrium, A is the effective area, q is the electric charge, μ is the electron mobility, and t is the thickness.At 0.16 V < V < 0.85 V, we observed a non-ohmic region on a log-log I-V curve, as evidenced by the m ≈ 5.67 (Figure 2b).According to the literature, [61] m > 3 indicates that the ZnO bulk resistance does not limit the current.Still, it is associated with traps within the ZnO bandgap, which is consistent with the trap-filling space-charge limited current (TFLC) regime.Figure 2c illustrates the gradual filling of the charge-carrier traps.The corresponding transition from ohmic to TFLC occurs at the transition voltage, V T = 0.16 V. Assuming that the density of trapping states is uniform and that there is an exponential distribution of traps (EDT) in energy, i.e., n t (E) = N t /kT c exp(-E/kT c ) at the TFLC regime; the current is expected to increase with the voltage following the Mark-Helfrich equation [39] : where N c is the effective density of states in the conduction band, N t is the density of traps, ϵ 0 is the vacuum permittivity, and ϵ r is the relative permittivity.At V = 0.85 V, the trap-filling limit is achieved.Such limit is associated with a change in the charge transport mechanism from the trap-filling to trap-free space-charge limited current (SCLC), which occurs beyond the trap-filling limit voltage, V TFL > 0.85 V, when all traps are filled by strong injection, [59] as illustrated in Figure 2d.Within this frame, we found m ≈ 2.01, meaning that an excellent approximation can be provided by the Mott-Gurney law, [35] which predicts m = 2 as described by the following expression: One may note that this equation is a particular case of Equation (2) when m = 2 and N c = N T .When producing diodes with three different thicknesses, the same sequence of m corresponding to ohmic conduction, TFLC, and trap-free SCLC is obtained.This suggests such mechanisms are linked to the interface-limited phenomena (viz.Figure S2, Supporting Information).However, it is noteworthy that the current magnitudes in forward and reverse bias are altered, indicating that the bulk also plays a role in impacting the ZnO channel bulk resistance.
It is worth mentioning that the trap-free SCLC regime in a diode cell has been used as an alternative to evaluating the electron mobility in vertical field-effect transistors, [59,62,63] This is due to the boundary conditions of the widely used equations for assessing the saturation mobility in planar field-effect transistors (FETs), which lose their physical meaning in the vertical transistor's analysis.It is important to emphasize that in FETs, the saturation mobility has a 2D (2D channel) and it is measured at the semiconductor/dielectric interface area, i.e., parallel to the film surface.On the other hand, the SCLC mobility obtained in vertical transistors, measured perpendicularly to the film surface, displays a 3D(3D channel), [64] that better approaches a measurement at the semiconductor/intermediate-electrode interface.For the reasons above, the mobility values obtained from FETs and vertical transistors may differ, since they differ in dimensionality.Generally, saturation mobilities reach higher values than SCLC mobilities.However, planar transistors have lower current densities and operate at higher voltages when compared to vertical transistors.
Using Equation (3), considering a fill factor, FF = 0.107 (see Supporting Information) that is a factor accounts for the off-current originating only from the nanowires area and considering that the relative permittivity of ZnO is ɛ r = 8.5, [65] we calculated  ≈ (8.04 ± 0.10) ×10 −3 cm 2 V −1 s −1 .[68][69][70][71][72][73][74] Furthermore, the slight difference between the values can be attributed to different ZnO deposition methods and solvents that modify properties such as grain boundary, defects, and surface roughness, which may affect electronic material properties.In contrast, the saturation mobility found in ZnO transistors with the planar channel may achieve values as high as  ≈ 1 cm 2 V −1 s −1 . [25,75,76]One may use the V TFL to determine the density of traps, once the following equation gives the relationship between these quantities: In agreement with Equation (4), and considering V TFL ≈ 0.85 V (Figure 2b), we calculated N t ≈ (1.96 ± 0.12) ×10 16 cm −3 for our ZnO films obtained by spray pyrolysis.This value is similar to 2.1 × 10 16 cm −3 , as reported for hydrothermally grown ZnO films, [77] and 1.5 ×10 16 cm −3 , as reported for sol-gel-derived ZnO films. [78]he complete vertical transistor architecture is accomplished by positioning the capacitive cell over the diode cell (as zoomed in Figure 1d).Figure 3a exhibits the output characteristic curves of the ITO/ZnO/AgNW/electrolyte/Au EGVFET, along with their respective leakage current (I GS -V DS ).The measurements were performed in the dark, varying the V GS from 0 to 2 V at room conditions.Also, V GS was limited to 2 V to ensure that the device worked within the electrochemical window of the electrolyte, preventing permanent changes or damage.In a previous report, it was verified by cyclic voltammetry that there are no faradaic current contributions between AgNW and the electrolyte in this range. [18]Therefore, there are purely capacitive contributions causing the EGVFET to operate by field-effect phenomena, which is possible due to the permeability of the AgNW intermediate electrode to the gate electric field, a result of its mesh structure, therefore having a perforated area.The I GS is much lower than the I DS , exhibiting independence of V DS and a weak dependence on V GS , which ensures that the device is operating properly due to the modulation of the channel through the field-effect phenomena.In Figure 3a, the current density increases until J on = 366.6 mA cm −2 , at V GS = 2 V.We measured the output characteristics with the AgNW intermediate electrode grounded.In contrast, the supplied voltage (viz.V DS ) was applied to the ITO bottom electrode.With this connection, a saturation current is reached at the reverse-biased Schottky diode, i.e., the reverse current is barely dependent on V, which is a close-to-ideal behavior. [79]Nogueira et al. reported an EGVFET based on an ITO/ZnO/AgNW diode cell that displayed an on-current density of 65.3 mA cm −2 when grounding the ITO electrode and applying V DS to the AgNW intermediate electrode. [18]In this scheme, the EGVFET output characteristics presented a voltage-dependent current at V DS < 0 (i.e., reverse bias).The non-saturation behavior in a reverse-biased Schottky diode is typically associated with a bias dependence on the Schottky barrier height. [80]However, further evidence is required before claiming this is the case.
An equivalent circuit can represent the EGVFET wherein a diode cell is connected in series with a capacitor cell, as sketched in Figure 3b.Whereas an ideal capacitor may well approximate the capacitor cell, the diode cell can be represented by a branch wherein an ideal diode is connected in series with a resistance (R s ) and in parallel to another (shunt resistance, R sh ).Accordingly, one may attribute the change in the saturation current (reverse bias) to a significant change in R sh .Figure 3c shows the EGVFET output differential resistance (R dif , obtained from output characteristics, where each curve of I DS -V DS is measured with a different V GS constant), which was calculated for V GS varying from 0 to 2 V using the following equation: In Figure 3c, we observed the formation of two plateaus, separated each other by a region where the resistance is dynamic and varies from point to point.The plateau at reverse bias provides insight into R sh , whereas the plateau at forward voltage represents the value of R s . [81]Notice that V GS applied to the EGVFET resulted in a slight difference between the forward I-V curves, and consequently, R s is weakly changed, evidenced in the zoom presented in the inset of Figure 3c.On the other hand, the parallel contribution is drastically modified upon increasing V GS .R sh decreases toward the R s value, gradually causing the diode to lose its rectifying characteristic, making it tend to be a resistor characterized by the resistance R ≈ 600 Ω.Therefore, the rectification ratio (RR = I foward /I reverse ), calculated at V DS = ±1 V, decreases by three magnitude orders (viz.from ≈ 4 ×10 3 to ≈ 5.7) upon V GS increasing from 0 to 2 V.
The current through the EGVFET diode cell is expected to be given by: where n is the ideality factor, k is the Boltzmann constant, T is the temperature, and I 0 is the saturation current, which in a Schottky diode cell is given by: where A * is the Richardson constant and ϕ b is the Schottky barrier height.At reverse bias, the current through the diode cell is predominantly the saturation current, i.e., a ϕ b -dependent physical quantity such as described by Equation (7).When the ZnObased EGVFET is at reverse bias, I DS increases as a result of the positive increase of V GS .We attribute such behavior to the fieldeffect phenomenon, which influences the band bending, lowering the effective potential barrier height at the ZnO/AgNW interface and increasing the saturation current.As a result, our EGVFET may be interpreted as a Schottky diode with a variable rectification ratio, which V GS can precisely control.
The analytical methods of Cheung and Cheung [41] and Vieira et al. [82] can provide important information about Schottky diodes.Assuming that for the ITO/ZnO/AgNW diode cell at V GS = 0, the approximations exp(qV D /nKT) ≫ 1 with V D = V-IR s can be considered, both methods can be used to determine the diode cell parameters using a vertical transistor.In addition, the presence of the electrolyte on the electrode interface can generate a minor polarization effect even at V GS = 0, which can differ slightly from the diode parameters' values.For this reason, it is essential to observe the diode cell parameters in situ, i.e., with the diode cell already integrated into the vertical transistor architecture.The following equations describe Cheung's method [41] : whereas the Norde's method generalized by Bohlin [40] follows the equations: being  is an arbitrary constant greater than n.Cheung's and Norde's methods do not allow us to analyze the fieldeffect consequences in the diode cell at V GS > 0, because the field-effect phenomena change the behavior drastically at the semiconductor/intermediate-electrode junction, as verified by the dynamic resistance plot.At V GS > 0, the device boundary conditions may no longer be applied.Figure 3d exhibits the curve traces calculated for dV/dlnI, and H(I), plotted as a function of I, whereas Figure 3e shows the F(V)-V plot.The parameters extracted using both methods are summarized in Table 1.We found R S ≈ 598.3 ± 75.9 Ω, which is in good agreement with ≈ 600 Ω calculated in the differential resistance analysis (Figure 3c, inset).In Table 1, we also show that the ϕ b matches for both methods, indicating the high consistency of our findings.Finally, Cheung's method [41] allowed us to calculate n ≈ 3.4 ± 0.3 (Table 1).When the ideality factor is equal to unity (n = 1), the diode can be entirely explained by Figure 4a presents the transfer curve of the EGVFET operating at a reverse bias (V DS = −1 V).The transfer curve profile resembles the transfer characteristics of transistors in a conventional architecture.The main figures of merit were calculated using the transfer data (I DS and I DS 1/2 curves), as presented in Figure 4a, leading to I on /I off ≈ 8.2 ± 3.4 ×10 3 , V TH ≈ 0.97 ± 0.15 V, and g m ≈ 1.32 ± 0.26 mS (transconductance peak at V GS ≈ 2 V).Such figures of good operation of the EGVFET as a transistor, allowing it to be applied in simple circuits for signal amplification, inversion, and/or switching.
The diode, whether in a stand-alone configuration or as an active cell in the EGVFET, exhibits rectification characteristics that align with the expectations outlined in Equation 6.According to the Cheung and Norde methods (viz.Table 1), the ideality factor and Schottky barrier height remain consistent, while the series resistance slightly increases when the ZnO/AgNW comes into contact with the electrolyte.This suggests the contact induces a polarization effect at the interface, even under zero V GS conditions.However, this difference proves negligible when considering the limits within the margin of error.
The formation of the conduction channel that leads to the transfer characteristics (Figure 4a) can be explained by the dynamics that occur in the perforations of the intermediate electrode.When the gate electrode is unbiased, ϕ b makes the charge extraction inefficient at the reverse bias.In this scenario, the saturation current is low and limited to the AgNW effective area (I off ), which is smaller than the geometric area of the shadow mask used to pattern the electrode due to the empty spaces between the interconnected nanowires (viz., the source perforations).Figure 4b shows a 2D cross-section front view of a single perforation with size "D" to illustrate I off along the EGVFET channel.When the gate electrode is biased, an electrical doublelayer (EDL) is formed at the electrolyte interfaces with the gate and intermediate electrode.This effect leads to charge carrier accumulation at the ZnO interface so that the region of the perforations becomes saturated with mobile electrons, with low leakage current, as verified in Figure 4a.Such charges at the ZnO interface reduce the effective potential barrier by inducing strong band bending that narrows the depletion layer. [83]Consequently, one may visualize a virtual contact forming along the perforation area.According to the theoretical results reported by Nawaz et al., [4] two types of conduction channels can be formed depending on the size of the intermediate electrode perforations.If the perforation gap D has a nanoscale size, the channel is concentrated at the center of the gap leading to a tunnel-like shape, [84] as illustrated in Figure 4c.If D has a microscale size, the channel is mainly concentrated at the edges of the gap, leading to an edge-drive channel, [4] as presented in Figure 4d.The D-size of our AgNW electrode is not regular (viz.Figure 1b), i.e., it presents a morphology with different perforation sizes randomly distributed over the intermediate electrode area, with a predominant presence of microscale gaps.Therefore, the current in the EGVFET's active layer will be a sum of the currents from the minor tunnel-like and the major edge-driven channels.
Figure 5a displays the log-log I-V plot featuring the EGVFET output curves acquired at 0 ≤ V G ≤ 2 V.As the voltage is applied to the gate, the regions that follow Ohm, Mark-Helfrich, and Mott-Gurney propositions undergo continuous changes, shifting V T and V TFL until the curve no longer presents three distinct regions, leading to m = 1.2 at V GS = 2 V. Within this frame, the Mark-Helfrich and Mott-Gurney conditions are entirely suppressed, giving way to a barely ohmic behavior, along the entire curve in forward bias.To get an in-depth view of how the device behavior is changed upon V GS > 0, we proceed to analyze the quantity m explicitly (from I  V m ) using the differential slope, m = d(ln I DS )/d(ln V DS ), [85] calculated at different V GS conditions.Figure 5b exhibits the corresponding m versus V DS curves.The horizontal dashed lines (green and red) are eye guides for m = 1 and m = 2, representing the ohmic and SCLC regimes, respectively.At V GS = 0, m is modified point by point reaching values greater than 6.Such a high m is responsible for the TFLC behavior, which confirms our previous analysis (viz.m ≈ 5.67, Figure 2b).As V GS increases, the TFLC maximum decreases in magnitude, and it is shifted on the x-axis to lower values of V DS , indicating that V GS > 0 is responsible for allowing a faster filling of Consequently, less voltage is required in the channel for the space-charge traps to be filled.The curves start to reach the red dashed line (m = 2) at lower V DS , compared to the situation in which V GS = 0 is applied.Such behavior means that charge transport predominantly takes place as trap-free SCLC.Finally, at V GS > 1.5 V, the device stops presenting both the TFLC and the trap-free SCLC regimes, whereas its output characteristics become parallel to the green dashed line (m = 1) in Figure 5b.In this scenario, the EGVFET output characteristics are reduced to an average ohmic behavior.This occurs because the field-effect phenomena induce a flat-band condition in the diode cell, allowing the charges to be injected through the effectively lowered Schottky barrier.
[88][89][90] Therefore, our EGVFETs can be exploited as UV photodetectors.Then, we evaluated the use of UV radiation as an energy source that causes changes in the charge carrier injection to conduct a complementary investigation to contrast the electric field effect (i.e., gate influence) with the photoresponse.Accordingly, we measured the device output characteristics at V GS = 0 V as a function of the 355 nm UV irradiance to evaluate how UV light affects the charge transport mechanism.Figure 6a presents a scheme illustrating the experimental setup for the photocurrent experiment.
Figure 6b exhibits the EGVFET log-log output curves acquired under different UV irradiance levels, from 0.04 to 0.75 mW cm −2 .In contrast, Figure 6c displays the corresponding curve featuring m versus V DS in the same irradiance range.Compared to the effect of V GS , the UV changes the profile of the curves similarly.Thereby, TFLC and trap-free SCLC regimes are shifted in V DS and continually suppressed as the irradiance increases.We argue that  V GS increases the charge carrier accumulation at the ZnO/AgNW interface through field-effect phenomena, causing a faster fill of traps.In Figure 7a-c, a hypothesis is presented to interpret the phenomenon found in this work in terms of a model proposed by Subramanian et al. [37] Figure 7a,b shows that the charge carrier accumulation due to V GS > 0 shifts the ZnO conduction band energy level leading to a thicker depletion in the active layer band diagram.Such a change in the conduction band energy results in a lower effective Schottky barrier height once tunneling can occur.Figure 7c presents a band diagram of the EGVFET's active layer at V GS = 0 under UV illumination.When the ZnO film absorbs UV photons, there is an increase in the charge concentration due to the generation of excitons, i.e., electrons are promoted to the conduction band, generating holes in the valence band.Such electron-hole pairs are dissociated by the V DS , giving rise to the photocurrent.In our case, it represents the increase in the charge carrier accumulation in the channel, as similarly reported for photodiodes. [42]In a photodiode, the surface potential at the active interface is reduced due to the photocurrent generation, [91] affecting the band bending and increasing the material conductivity. [92]The changes in band bending affect the depletion width, resulting in a transport that is more independent of the Schottky barrier height.Consequently, I DS tends to approach an ohmic behavior when the EGVFET is under UV illumination, as verified in the m-V DS plot (Figure 6c).
Based on the above interpretation, we can state that I DS can be switched by the incident light, resulting in an operation profile similar to that obtained when applying V GS .Notice that both V GS and UV are responsible for the accumulation of charge in the perforations; however, through different physical phenomena.The first provides charge accumulation through the EDLs, whereas the second is through photogeneration.This is possi-ble in the EGVFET architecture due to the morphology of the intermediate electrode, which enables photons to reach the ZnO through the perforation area and allows EDLs to be formed at the ZnO/electrolyte interface in the perforated area.Thus, our EGVFET shows excellent potential for future applications as a UV photodetector.Besides, meaningful information on the transport mechanism was obtained without the need for temperature variation that could damage the cellulose gel electrolyte.This method is an innovative proposal to evaluate the transport mechanism using vertical transistors.Therefore, in addition to delivering a device with good functioning and pointing out a promising application, our findings also contribute to a better understanding of the spray-coated ZnO electrical properties when such a semiconductor comes to diodes, EGVFETs, and photodetectors.
The EGVFET demonstrates a pathway for fabricating transistors with tiny nanometer-thick channels that display very low operating voltages.However, a significant challenge persists: how to integrate a high number of these transistors into a functional active-matrix integrated circuit.The electrolyte employed in our study, an ion-gel sticker, is manually cut and positioned onto the semiconductor.As we strive to move toward integrated circuits, it becomes imperative to produce solid or quasi-solid electrolytes that can be patterned down to the nanoscopic size.The manual cutting and positioning approach becomes impractical at such dimensions, necessitating avenues for improvements in the current integrability of EGVFETs for more intricate applications.Thus, in the current state of the art, EGVFETs are relegated to single-device or low-density-array applications (e.g., photo-switching), which involve the multi-function integration within a single device and/or the circuit arrays made of a small number of transistors.

Conclusion
A transparent and printed ZnO-based EGVFET was fabricated, and characterized and its potential for application as a phototransistor was tested.The ZnO-based EGVFET displayed well-defined electrical characteristics that arise from three distinct I-V power-law relationships that rule the charge transport in the device's diode cell, viz.ohmic conduction, TFLC, and trap-free SCLC.From charge-transport characterization, the density of traps in the spray-deposited ZnO was determined as (1.96 ± 0.12) × 10 16 cm −3 , and the SCLC electron mobility as (8.04 ± 0.10) ×10 −3 cm 2 V −1 s −1 .When positioning the capacitive cell over the diode counterpart and applying V GS , a continuous shift in the trap-filling and trap-free SCLC regimes was observed.This behavior was attributed to the charge carrier accumulation at the perforations of the AgNW electrode, causing a shift in the charge transport regimes toward a barely ohmic behavior with resistance around 600 Ω.The observed resistance shift was attributed to the field-effect phenomena, which reduces the potential barrier height at the ZnO/AgNW interface.Under this same condition, the EGVFET on-current density increased to 366.6 mA cm −2 .By analyzing its transfer characteristics, we found that the vertical architecture enables the operation of the device at low potentials, achieving V TH = 0.97 ± 0.15 V, with a high transconductance (g m ≈ 1.32 ± 0.26 mS), and I on /I off = (8.2± 3.4) ×10 3 .These characteristics highlight the potential of spray deposition for the production of high-performance transistors.The EGVFET also exhibited I DS switching under 355 nm UV light, resulting in changes in the charge carrier transport characteristics, similar to those obtained under V GS .However, these changes are caused by different physical phenomena .The UV detection mechanism was evaluated regarding the transport mechanisms in the diode cell, showing that the irradiance effect on the device enables its functioning as a phototransistor.Our findings demonstrate that EGVFET switching can be performed as a function of irradiance, expanding the range of potential applications of these devices for light sensing.This study has raised important questions to advance the knowledge about the relevance of spray-coating techniques in producing reliable ZnO films for nano-and optoelectronics applications.

Experimental Section
Pre-patterned interdigitated ITO electrodes (100 nm thick, W = 30 mm, L = 50 μm, Ossila) on float glass substrate were employed as the EGVFET source electrode.Over this electrode, a 200 nm thick ZnO film was deposited by spray pyrolysis of a 0.1 mol L −1 zinc acetate dihydrate (Zn(CH 3 COO) 2 2H 2 O, Sigma Aldrich) / methanol (CH 3 OH, Sigma Aldrich) solution.Preceding deposition, the organic precursor solution was stirred for 15 min at 60 °C until complete dissolution.The spraycoating deposition was conducted using a homemade system, where an airbrush spray nozzle was affixed to a 3D printer framework, enabling the airbrush to move horizontally across the substrate during the spray process, resulting in the formation of a uniform film.The ZnO layers were deposited with a spray nozzle traversing speed of 60 mm s −1 , a vertical distance of 120 mm from the airbrush to the sample, and at a temperature of 400 °C.This temperature is necessary for the precursor pyrolysis, leading to the in situ formation of ZnO. [42]The thickness of the ZnO film was assessed through profilometry using a Bruker DektakXT Stylus profilometer.
The EGVFET drain electrode (intermediate electrode) was fabricated using Ag nanowires (AgNWs) deposited onto the ZnO film by spray-coating their dispersion (Sigma-Aldrich, length between 20 and 50 μm) in isopropyl alcohol.The AgNW film was deposited with a spray nozzle traversing speed of 60 mm s −1 , a vertical distance of 100 mm from the airbrush to the ZnO, at a temperature of 120 °C (viz.for solvent evaporation), and using a 1 mm × 1 mm shadow mask.The sample was annealed at 200 °C for 30 min to improve the electrical contact of the AgNW.At this stage, the ITO/ZnO/AgNW diode cell is accomplished.
A self-standing hydrogel sticker based on cellulose with lithium hydroxide was used as an electrolyte dielectric layer for the capacitive cell.Additional details regarding the self-standing hydrogel preparation can be found elsewhere. [43]A gold wire was affixed over the electrolyte to complete the transistor architecture, serving as the top-gate electrode.The EGVFETs were measured using a Keithley SCS-4200 in the atmosphere and at room temperature.The field-effect influence was evaluated in the dark, and the UV exposure influence was evaluated using a homemade system with a Roithner LED (model XSL-355-3E-R6) as the 355 nm source.The LED irradiance was calibrated using a Hamamatsu photodiode (model SI-1133-01).Five devices were fabricated, and the reported parameters and figures of merit represent the calculation of mean values along with their respective standard errors.This methodology was employed to systematically evaluate device-to-device variations comprehensively.

Figure 1 .
Figure 1.a) Height profile of the glass/ZnO sample, acquired using profilometry.b) Topography (AFM image) of the spray-coated AgNW films over ZnO.Lateral scale bar: 5 μm.c) Height profile of the AgNW/ZnO sample acquired from the AFM.d) 3D sketch, cross-sectional (front view) illustration of the EGVFET architecture and the ZnO spray-coating deposition using an aerograph airbrush.The vertical double-head arrows identify the diode and capacitive cells in the cross-sectional view.e) PL spectrum of the ZnO film.Inset: Deconvolution of the PL spectrum within the frequency range of 375 to 435 nm.

Figure 2 .
Figure 2. a) I-V characterization of the ITO/ZnO/AgNW stand-alone Schottky diode.b) Log-log plot of the I-V data.Three charge transport regions are identified (as ascribed to the different m), whereas V T and V TFL are the transition voltage and the trap-filled limit voltage, respectively.c) Schematics of the diode in the trap-filling limited regime.d) Schematics of the diode in the trap-free space charge limited regime.

Figure 3 .
Figure 3. a) EGVFET output curves at different V GS from 0 to 2 V along with their corresponding leakage current (I GS -V DS ).b) sketch for the equivalent circuit applied to describe the EGVFET highlighting its diode and capacitive cells.c) Differential resistance versus V DS .Inset: zoom in the 1.0-1.5VDS range.d) dV/dlnI and H(I) versus current plots analyzed using Cheung's method.(e) F(V) plot analyzed using the Norde's method.

Table 1 .
ITO/ZnO/AgNW diode cell and stand-alone device parameters extracted by Cheung's and Norde's methods.± 0.01 the thermionic emission model, such a high ideality factor of 3.4 ± 0.3 suggests that the ZnO/AgNW junction cannot be explained purely by this model, as expected from the transport mechanisms observed in the Schottky diode that presented the influence of trap states.

Figure 4 .
Figure 4. a) EGVFET transfer characteristics acquired at V DS = −1 V along with their corresponding leakage current (I GS -V GS ), and its I 1∕2 DS −V GS plot.b) 2D cross-section front-view of a single perforation of D size, and the I off formation over the AgNW electrode; c) the tunnel-like channel formation when D is in nanoscale size; d) the edge-drive channel formation when D is in microscale size.

Figure 5 .
Figure 5. EGVFET charge transport mechanism evaluation.a) Output curves on a log-log scale for different V GS .b) The differential slope m as a function of V DS for different V GS , highlighting the ohmic (m = 1) and SCLC (m = 2) regions.

Figure 6 .
Figure 6.EGVFET response under UV irradiation.a) Scheme illustrating the experimental set-up to carry out measurements under UV.Charge transport mechanism evaluation of the EGVFET in terms of its (b) output curves on a log-log scale for irradiance levels under 355 nm UV light, and (c) the differential slope as a function of V DS for different irradiance levels.

Figure 7 .
Figure 7. Schematic illustration of the EGVFET architecture and the ZnO band diagram.The charge transfer mechanisms are sketched considering: a) V GS = 0 in the dark; b) V GS > 0 in the dark, c) V GS = 0 under UV.