Exploring Multi‐Bit Logic In‐Memory with Memristive HfO2‐Based Ferroelectric Tunnel Junctions

The increasing demand for data movement and energy consumption in physically separate von Neumann architectures, where the processor and memory are distinct entities, highlights the severity of the memory‐wall problem. Thus, memristor‐based logic‐in‐memory (LiM) has garnered significant interest as it is a paradigm that enables both logic and memory functionalities to be performed within a single device. Ferroelectric tunnel junctions (FTJs) have the advantages of low energy consumption and high scalability; thus, they are particularly appropriate for use as analog memristors in LiMs. Precise and accurate programming of the analog resistance states in FTJs is essential to achieve an efficient memristor‐based LiM design. However, existing switching models for FTJs cannot completely consider the ferroelectric domain switching, which challenges multi‐bit LiM operations. This particularly applies in cases involving updates from one intermediate resistance state (IRS) to another IRS, such as transitioning from State 01 to 10 in 2‐bit LiM. In this study, a novel phenomenon associated with domain switching is observed in the IRS of an HZO FTJ device and applied it to an LiM implementation. These findings can contribute to the operational accuracy and update rules of not only FTJ‐based LiMs but also other FTJ applications, such as crossbar arrays.


Introduction
The conventional computing paradigm is based on the von Neumann architecture, in which the processor and memory are physically separated.[3] The most significant obstacles are power-DOI: 10.1002/aelm.202300618consumption efficiency issues owing to data movement and latency caused by bottlenecks. [4]The battery life and realtime processing must be considered to achieve the ultimate goal of implementing edge devices, which requires the resolution of excessive power consumption and latency issues. [5,6]Therefore, the concept of logic-in-memory (LiM) has been proposed to improve energy efficiency and shorten the computational time.
LiM provides computational functionality directly within memory cells, thereby eliminating the need for data transfer. [7,8]Precise and accurate programming of analog states and the ability to store states in a nonvolatile manner are key factors to implement LiM. [9]Memristors, which can change their resistance state based on the history of current and/or voltage, are essential in realizing LiM, because they can store resistance states in a nonvolatile manner. [10,11][14][15][16] Among them, HZO-based ferroelectric tunnel junctions (FTJs) are appropriate devices for LiM and other memristive applications owing to their low power consumption, high scalability, and complementary metal-oxide-semiconductor (CMOS) compatibility. [4,17]The basic concept of FTJ-base LiM is as follows. [18]The polarization state of FTJ is modulated by an externally applied voltage pulse, which directly affects the tunneling current, the output of the FTJ.Assuming a basic 1-bit LiM, the low and high tunneling currents corresponding to HRS and LRS of the FTJ are logical outputs 0 and 1, respectively.The polarization state of FTJ can be evaluated after being written by an external applied voltage pulse, making it a sequential V-R logic.21] In general, the domain switching, which determines the resistance state of doped-HfO 2 -based FTJ is explained as a nucleationlimited switching (NLS) model. [22,23]However, the NLS model only analyzes the resistance change in response to voltage pulses in the high-resistance state (HRS) and low-resistance state (LRS).Consequently, the NLS model fails to adequately explain the transition between intermediate resistance states (IRSs), particularly for 2-bit or higher LiM operations.Although many studies are conducted on 1-bit binary switching operations between two logic states (corresponding to the HRS and LRS) in ferroelectric HZObased devices, [24] studies on multi-bit operations are scarce.Precise programming and state change mechanisms for transitions between different IRSs are required to perform 2-bit or higher LiM operations in a single device.To the best of our knowledge, this phenomenon has not been investigated.
In this study, we analyzed the state transition between different IRSs, which is essential for the operation of memristor (FTJ)based multi-bit LiMs, and successfully performed the V-R logic gate parallel-based LiM operations.The resistance state changes in the IRS of the FTJ device were investigated by resistance state change ratio and polarization parameter change ratio measurements, revealing a specific regularity in the domain switching.This study provides a profound insight into the domain switching mechanism and confirms the potential for parallel multi-bit LiM operations in FTJ devices by introducing a novel regularity in the IRSs.

Results and Discussion
The 4.5 nm-thick HZO-based FTJ device was designed for memristor-based multi-bit LiM implementation.It was fab-ricated in a metal-ferroelectric-metal structure, as shown in Figure 1a-top.A detailed description of ferroelectricity and on/off memory property of the fabricated FTJ device is provided in Figure S1 (Supporting Information).The FTJ-based sequential V-R logic gate operation can be achieved by applying voltage signals to the top electrode (TE) and/or bottom electrode (BE) of FTJ, changing the resistance state of HZO.A 1-bit logical operation can be performed by setting HRS to state 0 and LRS to state 1.As shown in Figure 1a-bottom, States 00, 01, 10, and 11 were used to implement parallel multi-bit logical operations and simultaneously represent States X and Y. Figure 1b shows the schematic energy band diagram (EBD) and underlying mechanisms of FTJ with multiple nonvolatile state characteristics.Even if TiN is used for both top and bottom electrodes, asymmetric EBD can be formed, and the reasons are as follows.At the interface of TiN and HZO, TiO x N y , and/or TiO x can be induced by oxygen collected in HZO. [25,26]Therefore, the EBD of TiN/HZO/TiN can have an on/off difference due to the asymmetric tunneling barrier. [27]Figure 1b-top-and-bottom shows a schematic of the polarization of a thin HZO film oriented in a one direction owing to an external voltage signal.The resistance state is determined by the change in the tunneling barrier depending on the oriented polarization direction, where the high-resistance state (HRS) and when applying pre-writing pulses of positive and negative polarity that can induce the same IRS in HRS and LRS.g) Domain state after a programming pulse with an amplitude equal to or less than the pre-writing pulse (applied to the top of (f)), each with a positive polarity, was applied from the state in each of the two cases of (f).low-resistance state (LRS) correspond to the OFF and ON states, respectively.States 01 and 10 are automatically determined to be IRS when HRS and LRS are set as State 00 and State 11, respectively.An FTJ device can be controlled by applying an appropriate external voltage signal, which leads to partial domain switching.Thus, two specific IRSs can be programmed, setting them as States 01 and 10, respectively.A description of the memory characteristics of fabricated HZO FTJ devices are provided in Figure S2 (Supporting Information).Figure 1c provides a brief explanation of States 00, 01, 10, and 11, and the input and output signals for parallel 2-bit logical operations.States 00, 01, 10, and 11, which correspond to the respective resistance states determined by the polarization direction of the HZO film, become the output signals, and the voltage pulse required to transition to another state becomes the input signal.Figure 1d illustrates the V-R logic gate operation process.As shown in Figure 1c, States 00, 01, 10, and 11 first represent the initial resistance state XY.In the initial resistance state, the input voltage pulse sequences are applied to TE and BE; the input voltage pulse sequence for TE is AB, and that for BE is CD.The voltage pulse sequences AB and CD induce a transition from the initial resistance state XY to another resistance state, referred to as the final output resistance state X′Y′.At this, X′Y′ must be one of States 00, 01, 10, or 11 (identical to XY).Therefore, the V-R logic gate operation requires precise resistance state control programming, relying on clearly distinguished multi-resistance states and an evident state change mechanism.However, the state change from one IRS to another cannot be explained by the existing HZO-based FTJ-related models.
HZO-based FTJs are typically described using the NLS model. [28,29]This model treats the ferroelectric as comprising multiple independent devices, and the switching time is determined by individual nucleation processes rather than by domainwall propagation. [30]Although the NLS model adequately describes the polarization switching in HRS and LRS, it does not explain the switching behavior in IRS. Figure 2a-c presents the domain switching behavior in two cases with the same IRS and different poling pulses and pre-writing pulse conditions (polarity and amplitude).The pre-writing sequences used to write HRS, LRS, and IRS are shown in Figure 2a-left.The conditions of utilized pulses are as follows: the black square represents a poling pulse with an amplitude of −1.5 V, capable of inducing a full upward polarization (HRS); the red square represents a poling pulse with an amplitude of +1.5 V, capable of inducing a full downward polarization (LRS); the blue square represents a pre-writing pulse with an amplitude of +0.65 V, capable of inducing a partial upward polarization (IRS) when the polarization is not in a full upward state; the yellow square represents a pre-writing pulse with an amplitude of −0.9 V, capable of inducing a partial upward polarization (IRS) when the polarization is not in a full downward state.All poling pulses used are 5 μs, and all programming pulses used are 10 μs. Figure 2a-right shows the resistance states corresponding to each pre-writing sequence.In pre-writing sequence ①, a pulse with an amplitude of −1.5 V, inducing the HRS, is applied, which leads to HRS, whereas in pre-writing sequence ②, a pulse with an amplitude of +1.5 V, inducing the LRS, is applied, which leads to LRS.In pre-writing sequence ③, a pulse with an amplitude of −1.5 V, inducing the HRS, is followed by the application of a pre-writing pulse with an amplitude of +0.65 V, capable of inducing the IRS, which results in IRS.In pre-writing sequence ④, a pulse with an amplitude of +1.5 V, inducing the LRS, is followed by the application of a pre-writing pulse with an amplitude of −0.9 V, capable of inducing the IRS, which results in IRS.The IRS results for pre-writing sequence ③ and ④ exhibit an approximately exact match, as indicated by the purple dashed square.
Figure 2b,c depicts changes in the resistance state under the application of the same sequential programming pulse train, following pre-writing sequence ③ and ④, which represent identical IRS. Figure S3 (Supporting Information) thoroughly describes the sequential programming pulse train of Figure 2c.The blue line in Figure 2b presents the case in which the pre-writing pulse used to set the initial IRS has a positive polarity with an amplitude of +0.65 V as indicated by the blue square in pre-writing sequence ③ presented in Figure 2a.It is observed that the resistance state for the sequential programming pulse train of negative polarity changes after a threshold voltage of ≈−0.4 V.Moreover, the yellow line in Figure 2b presents the case in which the pre-writing pulse used to set the initial IRS has a negative polarity with an amplitude of −0.9 V, as indicated by the yellow square in pre-writing sequence ④ presented in Figure 2a.Thus, the resistance state does not change even with an amplitude higher than a threshold voltage of −0.4 V applied, due to the application of a sequential programming pulse train of negative polarity with the same polarity as the pre-writing pulse.Subsequently, the resistance state begins to change when a pulse with an amplitude greater than −0.9 V, corresponding to the amplitude of the pre-writing pulse, is applied.Cases where a sequential programming pulse train with an amplitude below the threshold voltage (without inducing a change in the resistance state) is applied are shaded using semitransparent colored black squares to enhance the visibility of the tendency of the two measurement results.The same trend can be observed in Figure 2c, where the polarity of the sequential programming pulse train is positive.The yellow line indicates that the pre-writing pulse used to write the initial IRS has an amplitude of −0.9 V. Owing to the opposite polarities of the pre-writing pulse used to write the initial IRS and sequential programming pulse train, a change in the resistance state is observed after a threshold voltage of ≈+0.3 V.Moreover, the blue line indicates resistance state changes when a pulse with an amplitude greater than +0.65 V, the amplitude of the pre-writing pulse, is applied, rather than the threshold voltage of +0.3 V. Figure S4 (Supporting Information) thoroughly describes changes in the resistance state, which is represented by a green dashed square.Therefore, even at the same resistance state, the domain state differs depending on the combination of pulses used to in addition, the domain behavior for subsequent programming pulses is different.
This domain switching behavior can be explained by nucleation spot differences depending on the polarity of the applied pulse. [31]Figure 2d-g presents schematics of different domain states within an identical resistance state and distinct domain switching behaviors when the same pulse is applied to these do-main states.Based on the concept of the independent nucleation process in the NLS model, which is typically used to explore the switching of doped-HfO 2 -based FTJ devices, we can gain insight into this phenomenon through the differentiation of nucleation spots depending on the polarity of the programming pulse. [32]he yellow circles depict the nucleation spots located near BE that may participate in domain switching when a pulse of negative polarity is applied.The blue circles represent the nucleation spots near TE that may participate in domain switching for a pulse with a positive polarity.The four types of pulses used for the illustration were identical to the pulse conditions of the same color presented in Figure 2a-left.The blue and yellow arrows indicate the growth of nucleation spots involved in the switching owing to the applied pulse, and the domain-wall movement is omitted.When a poling pulse with a negative or positive polarity and a sufficient magnitude to align the polarization in one direction is applied to an FTJ device in any arbitrary state, as shown in Figure 2d, nucleation and growth are induced in the spots represented by the yellow or blue circles.Therefore, all domains become either upward HRS or downward LRS, as shown in Figure 2e; these results are the same as those of pre-writing sequence ① and ② presented in Figure 2a.As the nucleation spots are separated by the polarity of the applied pulse, we can state that: in Figure 2e-top, domain switching occurs owing to nucleation at the yellow circle near BE, leading to HRS; in Figure 2e-bottom, domain switching occurs owing to nucleation at the blue circle near TE, leading to LRS.Moreover, when pre-writing pulses with amplitudes of +0.65 and −0.9 V are applied, which can induce different domain states with the same resistance state in HRS and LRS, respectively, as shown in Figure 2f. Figure 2f-top and bottom displays identical resistance states, indicated by the corresponding areas occupied by the yellow and blue boxes.Domain switching occurs at specific spots susceptible to nucleation in near the TE and BE. Figure 2g illustrates the domain switching behavior in two cases with different domain states at an identical resistance state when an identical programming pulse is applied.Figure 2gtop depicts the domain switching behavior when the same amplitude of the programming pulse is applied after a pre-writing pulse with an amplitude of +0.65 V has induced domain switching near the nucleation-susceptible spot near the TE.The resistance state change induced by additional switching with a programming pulse equal to or less than that of the pre-writing pulse is negligible or nonexistent, as illustrated by the semi-transparent red lines in Figure 2b,c.In Figure 2g-bottom, a pre-writing pulse with a negative polarity of −0.9 V is applied, followed by a programming pulse with a positive polarity of +0.65 V.The domain switching occurs in the nucleation-susceptible spot near the TE rather than occurring near the BE.As illustrated by the dashed green squares in Figure 2c, applying the same pulse to an identical resistance state and different domain states induces distinct resistance states owing to nucleation-spot differences.
The separation of nucleation points according to the pulse polarity and occurrence of nucleation at each susceptible-nucleation spot imply that the ratio of domain switching when applying a programming pulse with a polarity different from that of the prewriting pulse is directly proportional to the total area that is initially aligned in the opposite direction by the pre-writing pulse.Separate nucleation spots in response to the polarity of applied pulse near the TE and BE and randomness of domain nucleation Figure 3. Cross-check validation for the theory that states "separated nucleation spot depends on the polarity of the applied pulse".a-f) DC readbased resistance state change measurement.a,b) Schematic representations of the sequence consisting of poling pulses, pre-writing pulses, sequential programming pulse trains, and DC read bias.c,e) Resistance states extracted using sequences (a) and (b), respectively.d,f) Resistance state changes normalized to the range of 0-1 after the respective negative and positive threshold voltages derived in (c) and (e), respectively.g-l) Pulse-based NDand PU-IRS measurements.g,h) Schematic representations of the sequence consisting of poling pulse, pre-writing pulse, and two triangular unipolar pulses.i,k) Transient current difference between the first triangular unipolar pulse from the subsequent triangular unipolar pulse extracted by (g) and (h), respectively.j,l) Polarization parameter changes normalized to the range of 0-1 after the respective negative and positive threshold voltages derived in (i) and (k), respectively.spots are the main reasons for this phenomenon, which can be simply defined by the theory that states "the separated nucleation spot depends on the polarity of the applied pulse".The randomness of domain nucleation spot is explained by the NLS model. [33]e conducted further measurements at IRS to validate this hypothesis.We performed the DC read-based resistance state change ratio and pulse-induced transient current-based derived polarization parameter change ratio measurements to verify the obtained results.Figure 3a-f presents the DC read-based resistance state change ratio measurement.Figure 3a depicts a sequence, which involves a poling pulse with an amplitude of −1.5 V to induce an HRS, followed by pre-writing pulses with amplitudes of +0.6, +0.9, and +1.5 V to induce various IRSs, sequen-tial programming pulse train of negative polarity, and a DC read bias of −0.25 V; all poling pulses used are 5 μs, and all programming pulses used are 10 μs.Unlike poling pulse and pre-writing pulse, DC read is not a pulse, so DC read is expressed as circles.Figure 3c shows the measured results.Similarly, Figure 3b depicts a sequence, which involves a poling pulse with an amplitude of +1.5 V to induce an LRS, followed by pre-writing pulses with amplitudes of −0.6, −0.9, and −1.5 V to induce various IRSs, sequential programming pulse train of positive polarity, and a DC read bias of −0.25 V. Figure 3e shows the measured results.Figure 3c illustrates that measurements for various IRSs indicate a change in resistance state when a programming pulse with amplitude beyond the negative threshold voltage of −0.4 V is applied.Figure 3e illustrates that measurements for various IRSs indicate a change in resistance state when a programming pulse with amplitude beyond the positive threshold voltage of +0.3 V is applied.Moreover, cases where an applied sequential programming pulse train with an amplitude below the threshold voltage are shaded using semi-transparent colored black squares to enhance the visibility of the tendency of the two measurement results.Figure 3d,f illustrates the resistance state change ratio after each threshold voltage is normalized to the range of 0-1.It is apparent that the change of the resistance state ratio approximately exactly matches regardless of the IRS level.Additionally, the characteristics of device-to-device variations for five different devices fabricated under the same conditions were also verified and described in detail in Figure S5 (Supporting Information).
Figure 3g-l presents the negative-down (ND)-and positive-up (PU)-IRS measurements that were conducted for cross-checking purposes to validate "the separated nucleation spot depends on the polarity of the applied pulse" theory.These measurements are variations of the positive-up-negative-down (PUND) measurement, and a detailed description of the typical PUND measurement method can be found in Figure S6 (Supporting Information).We deviated from the typical PUND methos, where all polarizations are aligned in one direction using a poling pulse of opposite polarity before applying a triangular unipolar pulse. [34,35]nstead, we performed the ND-and PU-IRS measurements after inducing IRS.The ND-and PU-IRS measurements consisted of the first and second triangular unipolar pulses, each inducing transient currents with and without polarization switching, respectively.Performing ND and PU-IRS enables the derivation of polarization parameter ratio changes solely due to current induced by polarization switching, through the analysis of the difference between the two transient currents in the various IRSs.Figure 3g illustrates the sequence of ND-IRS, which involves a poling pulse with an amplitude of −1.5 V to induce an HRS, followed by pre-writing pulses with amplitudes of +0.6, +0.9, and +1.5 V to induce various IRSs, and two triangular unipolar pulses with an amplitude of −1.5 V.All unipolar triangular pulse used are 250 μs each of rising time and falling time, a total of 500 μs. Figure 3h illustrates the sequence of PU-IRS, which involves a poling pulse with an amplitude of +1.5 V to induce an HRS, followed by pre-writing pulses with amplitudes of −0.6, −0.9, and −1.5 V to induce various IRSs, and two triangular unipolar pulses with an amplitude of +1.5 V. Figure 3i,k shows normalized values of the polarization parameter resulting from the switching contribution for each sequence.It is apparent that distinct transient currents are generated because of varying amounts of the switched polarization depending on the level of IRSs in both cases with positive and negative pre-writing pulse polarities.Moreover, shading is employed using the semi-transparent colored black squares where an amplitude below the threshold voltage is applied to enhance the visibility of the tendency of the two measurement results.Figure 3j,l illustrate the normalized polarization parameter change ratio when amplitudes beyond the threshold voltage are applied, in the range of 0-1.It is apparent that the polarization parameter change ratio approximately exactly matches regardless of the level of IRSs.These results agree with the findings presented in Figure 3d,f, obtained through the DC read-based resistance state change ratio measurement.Consequently, cross-checking the results of the two measurements supports the validity of the theory concerning "separated nucleation spot depends on the polarity of the applied pulse".
The resistance state change resulting from the applied pulse at IRS can be predicted by applying the theory "separated nucleation on the polarity of the applied pulse", allowing for programming.The change ratio the resistance state to programming pulses was consistent across various IRSs, and LRS HRS, enabling accurate programming from one to another targeted IRS.By applying this approach to memristors, such as FTJ devices, LiM architectures with more than 1-bit functionality within a single device can be designed.Figure 4a illustrates the configuration of four distinct resistance states 00, 01, 10, and 11, which serve as the initial and output resistance states to demonstrate the operation of a parallel 2-bit LiM based on FTJ devices.In this configuration, States 11 and 00 are set to the LRS and HRS, respectively, and States 01 and 10 are automatically set as IRSs.Based on the applied theory, the resistance states in not only the LRS and HRS states (States 11 and 00, respectively) but also in the IRS states (States 01 and 10) can be precisely controlled using the change ratio of the resistance state.To apply this approach, LRS and HRS were normalized to 0.00 and 1.00, respectively, allowing the representation of each state as a ratio.In particular, States 00, 01, 10, and 11 were assigned the values of 1.00, 0.67, 0.34, and 0.00, respectively.To allow for small deviations during operation, the state value was assigned to maximize the margin.Figure 4b illustrates the switching relationship between States 00, 01, 10, and 11.The diagram, derived from the measurement data presented in Figure 3c-f, demonstrates that States 01 and 10 exhibit different switching relationships depending on whether their source was State 00 or 11. Figure 4c presents the conditions of input pulse sequences AB and CD, which were appropriately configured based on the information presented in Figure 4b.In this configuration, AB and CD are encoded as the TE and BE, respectively.Figure 4d  Figure 5a,b depicts the logical operation results corresponding to output resistance states X′ and Y′, respectively, that are represented using Karnaugh maps; this method yields a simplified logical expression by tabulating it with the minimum term in each cell.For instance, the two minimum terms within the blue square of Figure 5a are derived through the following process.First, in Figure 5a-top-left, the value on the left side of blue square (1) indicates that when the initial resistance state is XY = 00, the input pulse sequences AB = 10 and CD = 00 are encoded, leading to the output state X′ = 1.Similarly, the value on the right side of blue square (1) indicates that when the initial resistance state XY = 00, the input pulse sequences AB = 10 and CD = 01 are encoded, leading to the output state X′ = 1.In all four cases (XY = 00, 01, 10, and 11), X′ = 1 when AB = 10 and CD = 00, and X′ = 1 when AB = 10 and CD = 01.That is, regardless of the condition of XY, X′ is determined by AB and CD.Both the left and right values of the blue square share the typical conditions of A = 1 and B = C = 0, and only the condition of D differs by 0 and 1.Consequently, the proposed approach can be used to represent X′ = A B C, and logical expressions for X′ and Y′ can be simplified; thus, Equations 1 and 2 are obtained in parallel.We can simultaneously obtain two logical output states X′ and Y′ through the same process by selecting two of the four input pulses (A, B, C, and D) as logic operands and performing a logic operation.Figure 5c shows the results of parallel Boolean operation through the X′ and Y′ equation.For instance, the first line in Figure 5c, Output X′ is 0 (FALSE) and Output Y′ is q (NOT q), is derived through the following process.As can be seen in the first line, X, Y = 0, A, C = 1, B = p, and D = q.If X = 0 and Y = 0, where the initial resistance state is State 00, are applied to equations 1 and (2) then the X′ and Y′ equations are given by: Thereafter, A and C = 1 mean that the corresponding V amp sequence is applied, and in this case, B and D maybe 0 or 1, respectively.If A, C = 1 is applied to the above Expressions 3 and 4, the X′ and Y′ equations are given as follows: Finally, if you apply the C (p) and D (q) selected as the operator, the X′ and Y′ equations are given as follows: Y ′ = q (8) X′ = 0 means that 0 (FALSE) logic operation can be performed because 0 is obtained regardless of 0 or 1 that B (p) and D (q) can have.Y′ = q means that the q (NOT q) logic operation can be performed because regardless of the 0 or 1 that B can have, 1 is obtained when D is 0, and 0 is obtained when D is 1.As described, each of X′ and Y′ can simultaneously perform the logic operation of FALSE and NOT q.
A complete Boolean logical function with parallel 2-bit logical operations has been successfully implemented with only two logical operational steps.Parallel 2-bit logical operations are based on the exact programming scheme and the verified theory "separated nullification spot dependencies on the polarity of the applied pulse".This implementation means that the proposed FTJ enables efficient parallel LiM computing with multi-logical operations, and is expected to be applicable to other ferroelectricbased memory devices.

Conclusion
In this study, we investigated the domain switching behavior within the IRS of HZO FTJs and applied this analysis to implement an FTJ-based parallel multi-bit LiM.The theory of "separated nucleation spot depends on the polarity of the applied pulse" was introduced and cross-checked using the DC readbased and pulse-induced transient current-based measurements.The confirmed domain switching regularity at various IRSs was applied to the state change of States 01 and 10 (two IRSs of the 2-bit LiM).The logic operation results demonstrated that a complete 16 Boolean logic function could be implemented in parallel using only two logic operation steps.These findings suggest that the proposed FTJ is an appropriate device for efficient parallel LiM computing, and the investigated domain switching behavior is expected to have broader utility in the analysis of ferroelectricbased devices and in state-update settings for FTJ applications, such as crossbar arrays.

Experimental Section
Fabrication: HZO ferroelectric thin films with a thickness of 4.5 nm were grown on a TiN/SiO 2 /Si substrate by PEALD at 180 °C.They were deposited using tetrakis (ethylmethylamido)hafnium(IV) and tetrakis (ethylmethylamido) zirconium(IV) with O 2 as the oxidant.HfO 2 and ZrO 2 were alternately deposited to prepare HZO with a ratio of Zr:Hf = 1:1.The top TiN electrode was deposited via RF magnetron sputtering in Ar and N 2 atmospheres using a circular-patterned hard mask (r = 100 μm).Subsequently, the initial amorphous HZO thin films were crystallized in a N 2 atmosphere at 600 °C for 70 s to stabilize the ferroelectric phase.
Electrical Measurements: Electrical measurements were performed using a parameter analyzer (4200A-SCS, Keithley) with a 4225-PMU.The lowlevel current was measured using a preamplifier connected to the SMU.All measurements were performed at room temperature and preceded by 10 6 field cycles to rule out the wake-up effect in the pristine state.

Figure 1 .
Figure 1. Outline of FTJ-based parallel 2-bit LiM.a) Schematic of the fabricated FTJ and its four states (State 00, 01, 10, and 11) based on resistance.b) Underlying mechanisms of FTJ for expressing nonvolatile multi-resistance states.c) Relationship diagram of input and output for parallel 2-bit logic operations based on four states.d) Schematic of the V-R logic gate operation process.From left to right, the initial resistor state, applying the input voltage pulse sequence, and final output state.

Figure 2 .
Figure 2. Different behavior of domain switching according to the "separated nucleation spot depends on the polarity of the applied pulse" theory.a) Pre-writing sequences and corresponding resistance states.b) Resistance state change for the sequential programming pulse train of negative polarity.c) Resistance state change for the sequential programming pulse train of positive polarity.d) Schematic representation of nucleation spots that can participate in domain switching of FTJ devices.e) Domain states after nucleation when pulses inducing (top) HRS and (bottom) LRS.f) Domain stateswhen applying pre-writing pulses of positive and negative polarity that can induce the same IRS in HRS and LRS.g) Domain state after a programming pulse with an amplitude equal to or less than the pre-writing pulse (applied to the top of (f)), each with a positive polarity, was applied from the state in each of the two cases of (f).
illustrates the output resistance states induced when the input pulse sequences are encoded for each initial resistance state.Each solid line corresponds to the resistance states of X′Y′ (States 00, 01, 10, and 11) with values of 1.00, 0.67, 0.34, and 0.00, respectively.The colored area includes all 64 encoding results from the actual device corresponding to the encoding of each input pulse sequence AB (00, 01, 10, and 11) and CD (00, 01, 10, and 11) in the four initial resistance states (States 00, 01, 10, and 11).The process for obtaining the results for a total of 64 encodings performed on actual devices is detailed in Figure S7 (Supporting Information).At this point, States 01 and 10 are set as A, C, D = 1, B = 0 and A = 1, B, C, D = 0, respectively.Each state can be stably operated despite the presence of small deviations because of the large margin.

Figure 4 .
Figure 4. FTJ-based parallel 2-bit LiM.a) Four resistance states (State 00, 01, 10, and 11) used as the initial resistance state XY and final output resistance state X'Y' of logic operation to demonstrate FTJ-based parallel 2-bit LiM operations.b) Switching relationships between States 00, 01, 10, and 11.States 01 and 10 (in case of IRS) have different switching conditions in some cases.c) Input pulse sequence corresponding to AB and CD encoded through TE and BE.d) Output resistance state X'Y' after the logical operation of encoding the input pulse sequence from the initial resistance state obtained from the actual device.Each solid line is a value of 1.00, 0.67, 0.34, and 0.00 corresponding to four states (States 00, 01, 10, and 11) of X'Y'.Colored areas are small deviations from the logic operations.

Figure 5 .
Figure 5. Parallel logical operation implementation.The output a) X' and b) Y', are represented as a Karnaugh map based on the results of logical operations.c) Derivation of the complete 16 Boolean logic functions.