Side‐Gate BN‐MoS2 Transistor for Reconfigurable Multifunctional Electronics

Developing 2D reconfigurable multifunctional devices is of great potential in further miniaturizing the chip area and simplifying circuit design. 2D van der Waals (vdW) heterostructures offer a novel approach to realizing reconfigurable multifunctional devices. Despite the numerous previous reports that have integrated various functions in a single 2D heterostructures device, most of those devices are based on a complex multilayer heterostructure or an air‐unstable channel material, limiting their ability to be applied in integrated circuits. There is an urgent need to develop 2D reconfigurable multifunctional devices that have a simple structure and stable electrical properties. In this work, a side‐gate reconfigurable device is illustrated based on simple BN‐MoS2 vdW heterostructures. Three different functions in a single device have been achieved, including a diode, double‐side‐gate reconfigurable logic transistor, and top floating gate memory. A lateral n+‐n homojunction is created along the MoS2 channel and the rectification ratio is above 105. Reconfigurable logic operations (OR, AND) can be achieved in a single double‐side‐gate device and the current on/off ratio is ≈t 104. Moreover, the device can act as a floating gate memory under back gate operation. Those results pave the way for integrating the same reconfigurable multifunctional devices to realize complex electronic systems.


Introduction
In past decades, the silicon complementary metal-oxidesemiconductor (CMOS)-based chips have made great progress DOI: 10.1002/aelm.202300621 in data processing, as the feature size of the transistors continues to scale down along the lines of Moore's Law. [1,2]To fulfill the requirements of big data and artificial intelligence, the traditional siliconbased device size has been reduced to its physical limits. [3,4]A new generation of devices with new materials and novel structures is urgently needed.2D layered materials, such as graphene, hexagonal boron nitride (h-BN), and transitionmetal dichalcogenides (TMDs) are of interest for the designs of electronics and optoelectronics due to their abundant unique properties. [5,6][12] For example, He et al. realized a high-performance diode, transistor, photodetector, and programmable rectifier, based on an asymmetric MoTe 2 -MoS 2 -BN-Graphene vdW heterostructures device. [10]Ambipolar 2D semiconductors, such as WSe 2 and BP, their polarity can be adjusted from ambipolar type to n or p-type by electrostatic doping.Miao et al. constructed reconfigurable logic and neuromorphic circuits based on doublesplit-local-gate WSe 2 homojunction. [13]Appenzeller et al. constructed BP transistors with reconfigurable polarities for secure circuits. [14]However, most of those reconfigurable multifunctional devices are based on complex multilayer heterostructures or air-unstable channel materials, [10,11,14,15] inevitably limiting their application and manufacture in integrated circuits.Thus, it is highly urgent to develop 2D reconfigurable multifunctional devices with simple structures and stable electrical properties.
In this work, we propose a side-gate multifunctional reconfigurable device based on simple BN-MoS 2 vdW heterostructures.We realize the integration of three different functions in a single device, including a diode, double-side-gate reconfigurable logic transistor, and top floating gate nonvolatile memory.The side gate voltage can control the carrier concentration in the MoS 2 channel due to the capacitive coupling between the side gate and the extra extension of the top floating gate. [16,17]We demonstrate is ±30 V, at V ds = 0.1 V. d) Output curves of the MoS 2 diode device in the device under control gate voltage of −3 V for side gate1 (SG1) and side gate2 (SG2), respectively.e) Transfer curves of SG1 under different SG2 biases for V ds = ±1 V, to verify that logic OR gate and logic AND gate can be switched in a single device.V sg1 and V sg2 are the voltage applied to SG1 and SG2.Taking 1 and −5 V as input "1" and "0" of V sg1 and V sg2 .Taking the channel current (I ds ) of on state and off state as output logic "1" and logic "0", respectively.that a lateral n + -n homojunction with side-gate-tunable rectification behavior is created along the MoS 2 channel.The device exhibits rectification ratios of 10 5 as a diode.While the device is modulated by two side gates simultaneously, reconfigurable logic operations (OR, AND) can be realized in a single device by switching the direction of the source-drain voltage.The current on/off ratios of AND and OR logic reach ≈4 orders of magnitude.Moreover, the device can act as a nonvolatile top floating gate memory under back gate operation.Those results pave the way for integrating the same reconfigurable multifunctional devices to realize complex electronic systems.Our work provides a new perspective for regulating the carrier concentration of 2D semiconductors.This side gate device configuration is also suitable for other 2D semiconductors.

Results and Discussion
Figure 1a,b describe the schematic and optical image of the sidegate BN-MoS 2 field-effect transistor, respectively.MoS 2 and BN serve as the channel material and the gate dielectric, respectively.The top Au serves as the top floating gate, covering only half of the MoS 2 channel near the source electrode.The coupling capacitance is created between the side gate and the extra extension of the top floating gate. [16,17]BN and MoS 2 are mechanically exfoliated from bulk materials and then transferred onto the predeposited source, drain, and side gate electrodes (Cr/Au) on a highly p-doped silicon substrate with 300 nm SiO 2 .Finally, a local Au top floating gate is deposited by electron beam evaporation.The detailed fabrication processes are shown in Figure S1 (Supporting Information).A well-defined and clean interface between Au and MoS 2 is achieved using the vdW bottom contacts. [18,19]The Raman spectrum and atomic force microscopy (AFM) height images of MoS 2 and BN are shown in Figure S2 (Supporting Information). [20]The thicknesses of the MoS 2 and BN are 3.2 and 11.2 nm, respectively.
As shown in Figure 1a, we realize the integration of three different functions in a single device, including a diode, double-sidegate reconfigurable logic transistor and top floating gate memory.The top floating gate memory under back gate control is marked by the red solid rectangle in Figure 1a, where Au, BN, and MoS 2 serve as floating gate, tunneling, and channel layers, respectively.The side-gate-tunable rectification diode is marked by a green solid rectangle in Figure 1a.Due to capacitive coupling between the side gate and the extra extension of the top floating gate, a lateral n + -n homojunction is created along the MoS 2 channel.The double-side-gate reconfigurable logic transistor is marked by bule solid rectangle in Figure 1a, where the side gate1 (SG1), side gate2 (SG2), and drain-source current (I ds ) serve as input signal1 (IN1), input signal2 (IN2), and logic output (OUT), respectively.Combined with the rectification effect of the MoS 2 channel current, reconfigurable logic operations (OR, AND) can be realized in a single double-side-gate transistor by switching the direction of source-drain voltage without additional control terminals.Figure 1c-e shows the typical electronic properties of the top floating gate memory, diode, and double-side-gate logic transistor in a single device, respectively.Detailed characterization and discussion of all these devices are provided below.
We first study the rectification effect of a diode based on MoS 2 side-gate field-effect transistor (SGFET).The simplified schematic of the capacitances involved in the SGFET is depicted in Figure 2a.The Cst and Ctg are series-connected, where Ctg is the top floating gate capacitance, Cst is the coupling capacitance between the side gate and the extra extension of top floating gate. [16,17]Figure 2b shows the transfer curves of the SGFET, with the side-gate voltage (V sg1 ) sweeping from −5 to 2 V at different source-drain bias (V ds ).The transfer curve exhibits typical n-type semiconductor behavior with a high on/off ratio of ≈10 6 at V ds = 1 V.[23] The high on/off ratio resulting from the atomic thickness of MoS 2 and its sensitivity to electrostatic control renders it highly suitable for logic operation. [13,24,25]igure 2c furthermore highlights the output curves (I ds -V ds ) under V sg1 ranging from −5 to 5 V with a step size of 1 V.When V sg1 > 3 V, the device shows large channel current that is nearly symmetric under negative and positive biases, indicating Ohmiclike contacts between the MoS 2 channel and the bottom Cr/Au bottom electrodes, and the channel is in a charge accumulation state.As V sg1 decreases from 3 to −5 V, the channel current gradually decreases; conversely, the current under positive bias drops much faster than that under negative bias.Therefore, the channel current indicates reverse rectification behavior with a peak rectification ratio exceeding 10 5 .The rectification behavior of channel current is consistent with the transfer characteristic curve of the SGFET in Figure 2b. Figure 2d presents the charge doping state and energy band diagram along the MoS 2 channel under the negative side gate voltage (V sg ).Previous reports have shown that MoS 2 is intrinsically n-doped due to sulfur vacancies. [26]Due to the strong Fermi level Pinning effect, the half area of the MoS 2 channel near the source electrode remains n-type doped when a moderately negative V sg is applied, but the electron concentration is reduced dramatically as negative V sg induces positive charges in the MoS 2 . [11]In this way, a n + -n junction is formed along the drain to source direction.Notably, multilayer MoS 2 is essential for the formation of n + -n junction.The intrinsic current of multilayer MoS 2 without gate voltage is much higher than that of monolayer MoS 2 due to its lower bandgap and high density of states at the conduction band minimum. [27,28]The multilayer MoS 2 channel remains in the high current state when the electron concentration is reduced at a moderately negative V sg .The electron of monolayer MoS 2 can easily be completely depleted at a very small negative V sg .Figure 2e shows that the variation of rectification ratio with V sg1 can be divided into three stages, corresponding to the three states of the channel (deplete state, n + -n junction, and accumulation state).The electrical transport across the n + -n junction can be expressed by the equation: J = J 0 (exp qV ds nkT − 1), where J is the channel current density, J 0 , n, k, and T are the reverse saturation current density, ideality factor, Boltzmann constant, and temperature in Kelvin, respectively. [29,30]When V ds > 3kT/e (≈0.08 V), the equation can be simplified as: J = J 0 (exp qV ds nkT ). [29,30]The output curve at V sg1 = −3 V is shown in Figure 2e, and the inset shows the linear fitting of Ln (I ds ) versus V ds in the range from −0.075 V to −0.275 V.The ideality factor n is estimated to be 1.67 at room temperature (T = 300 K).The large ideality factor of the diode in SGFET indicates that the transport is controlled by recombination processes. [11]The transfer and output curves of MoS 2 SGFET under different V sg2 are shown in Figure S3 (Supporting Information).It demonstrates that SG1 and SG2 have almost the same control ability for the MoS 2 channel.In comparison, we also fabricate SGFET that the MoS 2 channel is completely covered by top floating gate in Figure S4 (Supporting Information), and the channel current doesn't exhibit rectification effects.This proves that the device configuration that only half area of the MoS 2 channel is covered by the Au top floating gate is crucial for rectification effects to occur.The transfer and output curves versus time are shown in Figure S5 (Supporting Information).The electrical characteristics show negligible changes over time.Due to the air-stable MoS 2 channel protected from external environment by BN, the MoS 2 SGFET exhibits robust electrical stability, which has also been demonstrated in conventional double-gate MoS 2 transistors encapsulated by BN. [31] Then we construct a double-side-gate MoS 2 field-effect transistor to realize the reconfigurable logic OR and AND gates.As shown in Figure 3a, V sg1 and V sg2 serve as input signal1 (IN1) and input signal2 (IN2), respectively, while the channel current (I ds ) serves as the logic output (OUT).When V sg1 = "0" (−5 V) and V sg2 = "1" (1 V) or when V sg1 = "1" (1 V) and V sg2 = "0" (−5 V) at V ds = 1 V, the channel is turned off (output logic 0) due to the competition between SG1 and SG2 for control of the channel potential and conduction (Figure 3b).Conversely, the channel is turned on (output logic 1) under the same input signals due to the rectification effect of channel output current.When the two gate input voltages are both "0" (−5 V) or "1" (1 V), SG1 and SG2 work together to facilitate the turning off or turning on of the channel due to the intrinsic n-doped doping of MoS 2 (Figure 3b).This competition and cooperation effect in double-side-gate MoS 2 FET have also been observed in traditional double-gate FETs. [32,33]s shown in the current mappings in Figure 3c, sweeping the gate voltage from −5 V to 1 V at V ds = ±1 V for both SG1 and SG2, the output current in the right-top corner is significantly higher than the other three corners at V ds = 1 V, and the corresponding logic function is the AND gate; conversely, the output current in the left-bottom corner is significantly lower than the other three corners at V ds = −1 V, and the corresponding logic function is the OR gate.By combining the rectification effect and double-gate modulation, we can achieve reconfigurable logic functions (OR and AND gates) in a single double-side-gate MoS 2 field-effect transistor without the need for additional control terminals by simply switching the direction of source-drain voltage.The on/off ratios of AND gate and OR gate reach ≈10 4 .In addition, as shown in Figure S6 (Supporting Information), the same logic functions can be achieved by reversing the polarity of the V ds bias terminal and the ground (GND) terminal, further improving the device's freedom of operation.We have also fabricated a double-side-gate WSe 2 field-effect transistor that the WSe 2 channel is completely covered by top floating gate in Figure S7 (Supporting Information), and the XNOR gate can be realized in a single WSe 2 device.This proves that the side gate configuration can be extended to other 2D semiconductors besides MoS 2 .
These results demonstrate the great potential of double-side-gate devices to implement more complex logic functions with simplified integrated circuit design.
Finally, we investigate the electrical properties of the top floating gate memory under back gate operation.Figure 4a displays the back gate bidirectional-sweeping transfer curves under different sweeping range of back-gate voltage (V bg ). Figure 4b shows the back gate bidirectional-sweeping transfer curves under different V ds with a fixed sweeping range of V bg .V bg is swept from negative to positive voltage region and back to negative voltage region.The hysteresis window, which is gradually increase with the maximum value of V bg (V bg,max ), can be clearly observed.The hysteresis window is also called memory window (ΔV), which is defined as the shift of threshold voltage in the bidirectional sweeping transfer curves. [34]The size of memory window determines the reliability of the memory.A memory window of ΔV = 20 V can be achieved when V bg,max = 30 V.
Figure 4d,e present the energy band diagrams and charge tunneling mechanisms in the device at different memory operations. [16,34,35]When a large positive V bg (+V bg ) is applied, electrons accumulate in the MoS 2 channel due to the electrostatic doping effect.At the same time, a positive electrical potential is generated between the top Au and MoS 2 due to the large concentration gradient of electrons between MoS 2 channel and Au floating gate, which will make the accumulated electrons tunnel from the MoS 2 to Au through the Fowler-Nordheim mechanism. [34,35]fter +V bg is removed, the tunneled electrons remain trapped in the Au due to the large electron potential barrier between Au and BN.The negatively charged top floating Au can acts as an effective negative local gate, which can deplete the electrons in the MoS 2 channel.Although only half area of the MoS 2 channel near the source electrode is covered by the top Au, the channel conductance is programmed to the high resistance state (HRS).On the other hand, when a large negative V bg (−V bg ) is applied, electrons in MoS 2 channel are depleted.The electrons trapped in the top floating Au are tunneled back to the MoS 2 channel due to the strong built-in electric field between the negatively charged top Au floating gate and the depleted MoS 2 channel. [34,35]The channel conductance is erased to the low resistance state (LRS).It is worth noting that the coupling capacitance between the back gate and the extra extension of the top floating gate has also been reported to contribute to the charge tunneling between the MoS 2 channel and the Au floating gate. [16]Only a small area of the top floating gate can be coupled to the back gate due to the shielding effect of the side-gate metal electrode, so the charge tunneling mechanism in this device is more similar to the conventional top floating gate memory. [16]Figure 4c shows the retention characteristics of HRS and LRS at a reading voltage of 0.5 V.The changes in HRS and LRS are negligible, and the on/off ratio of HRS and LRS exceeds 10 5 over a period of 1000 s.All these results fully demonstrate that this Au top floating gate device is a promising nonvolatile memory for future applications.
In Table S1 (Supporting Information), we summarize the on/off ratio of various MoS 2 -based heterostructure devices for diode, logic gate, and memory in the previous reports.Unlike ambipolar semiconductors, MoS 2 is intrinsically n-doped due to sulfur vacancies and strong Fermi level pinning near the conduction band. [33]Therefore, it is difficult to realize MoS 2 -based reconfigurable logic gate in a single device.Most of the reconfigurable logic gate in a single MoS 2 device is based on MoS 2 thickness engineering, photoswitching logic, and electrolyte gel gating transistors. [21,23,24,32]It is usually necessary for MoS 2 to form heterostructures with other unstable 2D semiconductors to achieve a diode, such as BP and MoTe 2 . [10,36,37]To integrate multiple functions in a single device, complex multilayer heterostructures containing at least three 2D materials is fabricated, such as MoTe 2 -MoS 2 -BN-Graphene, and MoS 2 -BN-Graphene. [10,11,38]Compared with other reports, our devices feature comprehensive device parameters, robust electrical stability, simple device structure and fabrication process.The performance of the device can be further optimized by adjusting the thickness of MoS 2 and BN, the area of the top floating gate, and the area of the side gate electrode, which requires further investigation.

Conclusion
This work designs and fabricates a side gate reconfigurable multifunctional transistor based on BN-MoS 2 vdW heterostructures.A diode, double-side-gate reconfigurable logic transistor and top floating-gate memory are successfully integrated in a single device.As a diode, this device exhibits side-gate-tunable rectification behavior with a rectification ratio exceeding 10 5 .As a doubleside-gate reconfigurable logic transistor, the logic function can be switched between AND gate and OR gate by simply switching the direction of source-drain voltage, without the need for additional control terminals.The current on/off ratios of the AND gate and OR gate reach ≈10 4 .As a top floating-gate memory, the device can retain its charge for up to 1000s with an on/off ratio of 10 5 .Those results provide a means for integrating the same reconfigurable multifunctional devices to realizing complex electronic systems.Our work provides a new perspective for regulating the carrier concentration of 2D semiconductors.This side-gate device configuration has the potential to be extended to various 2D semiconductors for achieving more fascinating functions, such as ptype and ambipolar semiconductors. [32]Additionally, the floating gate memory under side gate operations have been realized in WSe 2 /BN/Graphene heterostructures. [39]

Experimental Section
Device Fabrications: First, electron beam lithography (EBL) and electron beam evaporator (Texas Instruments DE400) were used to define Cr/Au (5 nm/30 nm) bottom source, drain, and side gate electrodes on the highly p-doped silicon substrate with 300 nm SiO 2 after a lift-off process.Afterwards, MoS 2 flake was mechanically exfoliated and dry transferred onto the pre-deposited source-drain bottom electrodes using PF gel films (Gel Pak Co., Ltd.) under a microscopic alignment system.BN was then dry transferred onto MoS 2 and bottom side gate electrodes by the same method.Finally, EBL and electron beam evaporator are used to define top Au (20 nm) floating gate on the BN-MoS 2 heterostructures.The device is vacuum annealed at 200 °C for 1 h to remove absorbents and enhance the interaction between MoS 2 and BN.
Measurements and Characterizations: The Raman spectra of BN and MoS 2 was recorded using a Raman spectrometer (HORIBA Jobin Yvon HR800) with a 514 nm excitation laser.The thicknesses of BN and MoS 2 were examined using the atomic force microscope (Multimode 8, Bruker) under the tapping mode.The electrical measurements were carried out under ambient conditions at room temperature using the commercial high-resolution photoelectric scanner (MStarter200) and semiconductor parameter analyzer (Agilent B1500A).

Figure 1 .
Figure 1.Reconfigurable device based on BN-MoS 2 vdW heterostructures.a) Schematic image of side-gate BN-MoS 2 transistor.b) Optical image of side-gate BN-MoS 2 transistor.MoS 2 , BN, and top Au floating gate are marked by solid lines in white, blue, and yellow, respectively.c) Typical bidirectionalsweeping transfer curve of the MoS 2 top floating gate memory in the device under back gate operation.The sweeping range of back gate voltage (V bg )is ±30 V, at V ds = 0.1 V. d) Output curves of the MoS 2 diode device in the device under control gate voltage of −3 V for side gate1 (SG1) and side gate2 (SG2), respectively.e) Transfer curves of SG1 under different SG2 biases for V ds = ±1 V, to verify that logic OR gate and logic AND gate can be switched in a single device.V sg1 and V sg2 are the voltage applied to SG1 and SG2.Taking 1 and −5 V as input "1" and "0" of V sg1 and V sg2 .Taking the channel current (I ds ) of on state and off state as output logic "1" and logic "0", respectively.

Figure 2 .
Figure 2. Rectification effect of the diode device based on MoS 2 side-gate field-effect transistor.a) Simplified schematic image of SGFET with capacitances.b) The I ds -V sg1 curves under different V ds .c) The side-gate-tunable rectification behavior of channel current under different V sg1 from −5 to 5 V. d) Distribution of charge-doping and energy band diagram along the MoS 2 n + -n junction.e) Reverse rectification ratios (RF = I −1V /I 1V ) under different V sg1 .f) Rectification behavior of channel current at V sg1 = −3 V.The inset is the linear fitting of Ln(I ds ) versus V ds in the red circle region, where the fitted linear slope is −23.1.The ideality factor n of diode device is estimated to be 1.67 at room temperature (T = 300 K).

Figure 3 .
Figure 3. Reconfigurable logic OR and AND gate based on double-side-gate MoS 2 field-effect transistor.a) Schematic of the reconfigurable logic transistor.The voltages (V sg1 , V sg2 ) applied to side gate1 (SG1) and side gate2 (SG2) are denoted as the logic input (IN1, IN2).The source-drain current, I ds , is measured as the logic output (OUT).b) Output characteristics after applying different voltage biases to the SG1 and SG2.c) I ds is mapped as a function of V sg1 and V sg2 for V ds = ±1 V. Taking 1 and −5 V as input "1" and "0" of V sg1 and V sg2 , the logic functions are shown by the output current level of Ids.The device shows logic AND at V ds = 1 V and logic OR at V ds = −1 V.

Figure 4 .
Figure 4. Characterization of the top floating gate memory under back gate operation.a) Back gate bidirectional-sweeping transfer curves under different sweeping range of back-gate voltage (V bg ) from ±5 to ±30 V at V ds = 0.5 V. b) Back gate bidirectional-sweeping transfer curves under different sourcedrain bias (V ds ) with a fixed sweeping range of V bg = ±30 V c) Retention characteristic of the top floating gate memory device after applying program ( + 30 V) and erase (−30 V) voltages with 5 s duration.The current ratio of the high resistance/low resistance state (HRS/LRS) reaches 10 5 at V ds = 0.5 V after 1000 s. d) Schematic energy-band diagrams of a memory device for program operation.e) Schematic energy-band diagrams of a memory device for erase operation.