Enhanced Performance of Organic Field‐Effect Transistor with Bi‐Functional N‐Type Organic Semiconductor Layer

Organic field‐effect transistors (OFETs) hold great promise for applications in non‐volatile memories, detectors, and artificial synapses due to the good flexibility and biocompatibility. However, certain drawbacks such as high operating voltages and significant degradation in endurance characteristics have hindered their practical implementations. Herein, a novel approach is proposed to enhance the performance of OFETs by incorporating a bi‐functional n‐type polymer semiconductor interlayer, Poly‐{[N,N'‐bis(2‐octyldodecyl)naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (N2200), into a pentacene OFET structure. The device exhibits remarkable improvements, with reliable P/E operation cycles of over than 104 and a retention time of more than 10 years. On one hand, the inclusion of N2200 as an n‐type semiconductor effectively reduces the height of hole‐injection barrier for trapping and thus reducing the working voltage based on the electrostatic induction theory. On the other hand, n‐type semiconductor N2200 serves as a native hole‐consumption (or hole‐trapping) dielectric, and its narrower bandgap restrains the formation of deep hole‐traps, thus favoring the endurance characteristics of the OFET.


Introduction
Flexible electronics, marked by a special class of thin-film electronic devices, have received great research interest due to the DOI: 10.1002/aelm.202300651[3] Of them, three-terminal organic field-effect transistors (OFETs) exhibit remarkable versatility and are well-suited for various applications, such as non-volatile memory, detectors, and even artificial synapses by enabling channel control with a presynaptic gate. [4,5]p to now the electrical performance of OFET is still one of the main challenges hindering its practical application as well as the mechanical compliance of organic semiconductors. [6,7]10][11][12][13][14][15] As a typical small-molecule semiconductor, pentacene is considered as a suitable material for investigating the basic principles of OFET due to its large field-effect mobility and its commercial availability. [16,17][20][21] Therefore, it is essential to further explore the device structure and interface regulation of pentacene OFET memory, aiming to reduce the height of hole-barrier formed by the defects of pentacene.In our previous works, Wang et al. introduced an organic N-type semiconductor interlayer between pentacene and PVN, which consequently reduce the height of the hole-barrier, thus reduced the operating voltage. [22]][17][18][19][20][21][22][23][24][25][26] It was identified by using monochromatic photonexcitation technique that the quick degradation of endurance characteristics in pentacene OFET with poly(2-vinyl naphthanlene) (PVN) electret was dominated by the deep traps in PVN, which are associated with the chemical defects within PVN. [6] Therefore, in order to get a reliable pentacene OFET, polymer electrets are not beneficial to endurance characteristic of memory device, despite its advantages in low-temperature solutionprocessing.
In this work, a bi-functional n-type polymer semiconductor layer, Poly-{[N, N'-bis(2-octyldodecyl)naphthalene-1,4,5,8-bis(dicarboximide)−2,6-diyl]-alt-5,5′-(2,2′-bithiophene)} (N2200), was introduced into a pentacene-based OFET, which shows reliable P/E operation cycles of over than 10 4 and a retention time of more than 10 years.N2200 as an n-type semiconductor reduces the height of hole-injection barrier and thus reducing the working voltage based on the electrostatic induction theory. [27]On the other hand, n-type semiconductor N2200 is a native hole-consumption (or hole-trapping) dielectric, and its narrower bandgap (1.5 eV) restrains the formation of deep hole-traps, thus favoring the endurance characteristics of the OFET.This approach holds great potential for the practical implementation of OFETs in a wide range of applications, including non-volatile memories, detectors, and artificial synapses.

Materials
Thermally oxidized 90-nm SiO 2 coated Si(p + ) wafer was purchased from Hefei Kejing Materials Technology CO., LTD., PVN (M W = 175 kg•mol −1 ), and pentacene were purchased from Sigma-Aldrich, N2200 was purchased from 1-Material.Cu was purchased from Piezotech, and Toluene and butyl acetate were purchased from Aladdin.ZnO target was purchased from Beijing Founde Star Science & Technology CO., LTD.

Fabrication of OFET Memory Devices
OFET memory devices were fabricated according to the schematic drawing shown in Figure 1.Thermally oxidized 90-nm SiO 2 coated Si(p + ) wafer was employed as the substrate.Wafers were cleaned sequentially in an ultrasonic bath with acetone, ethanol, and de-ionized water for 10 min, respectively.Subsequently, ZnO films were deposited on the above substrate by using RF-magnetron sputtering technique in pure Ar with a ceramic target.Then polymer layer was deposited on ZnO films by using spin-coating technique (4000 rpm, 60 s) with a toluene solution of PVN (2 mg mL −1 ) or N2200 (2 mg mL −1 ).In other OFET devices without ZnO, N2200 film was coated on SiO 2 /Si(p + ) substrate by using spin-coating technique with a toluene solution of N2200 (4 mg mL −1 ) at a speed of 3000 rpm for 60 s.PMMA tunneling-layer (concentration of 2 mg mL −1 in butyl acetate) was coated on N2200-covered SiO 2 /Si(p + ) substrate by using spin-coating technique at a speed of 4000 rpm for 60 s.After deposition, PVN films were thermally annealed at 80 °C for 1 h, and N2200 and PMMA films were thermally annealed at 110 °C for 1 h, respectively.Then, 40-nm pentacene film was evaporated using a shadow mask at a pressure of 7 × 10 −4 Pa on the top of polymer film (PVN or PMMA) at a deposition rate of 0.2-0.5 Å s −1 .Cu source/drain electrodes (80 nm) were deposited on pentacene film by using thermal-evaporation technique through a shadow mask with the channel length and channel width of 80 μm and 750 μm, respectively.

Device Characterization
The thicknesses of ZnO, PVN, PMMA, and N2200 were determined by using a spectral ellipsometer (J.A. Woollam, RC2).The thicknesses of pentacene and Cu film were measured with a quartz crystal microbalance.The crystal structures of films were investigated by using X-ray diffraction (XRD) (Rigaku, Ultima III X).The surface morphologies of ZnO, PVN, N2200, PMMA, and pentacene films were characterized by using an atomic force microscopy (AFM, Asylum Research, Cypher-ES).The electrical characteristics of pentacene based OFET memory devices were measured using a semiconductor parameter analyzer (Keithley 4200) on a Cascade Summit 11000B-M platform in air.

Results and Discussion
In our research, a bottom-gated pentacene OFET structure was fabricated, as shown in Figure 1a, where ZnO film acting as an n-type oxide semiconductor prepared by using RF-sputtering technique in an oxygen-deficient chamber was intercalated between gate dielectric SiO 2 and the charge-trapping layer to lower the working voltage of pentacene OFET by reducing the height of hole-injection barrier, which is originated from the positively charged defects formed at the early growing stage of pentacene film. [19,28]A 7-nm PMMA layer was fabricated as the tunneling layer to restrict the holes stored in charge-trapping layer from escaping to pentacene channel after removing negative gate voltage.Here, n-type polymer semiconductor N2200 was employed as the charge-trapping layer instead of PVN used in traditional pentacene OFET structure. [6]For making a comparison, pentacene OFET structure with PVN as the charge-trapping layer was also fabricated, as shown in Figure 1c.
X-ray diffraction (XRD) pattern of the hetero-structure pentacene/PMMA/N2200/ZnO/SiO 2 /Si(p + ) (see Figure S2, Supporting Information) shows that ZnO film was crystallized along <002>-orientation, and pentacene film was crystallized and prefers an <00l>-orientation.Figure 2a shows the transfer characteristics of pentacene OFET with N2200 charge-trapping layer.At a set of sweeping gate-voltage of ±15 V (+15 V→−15 V→+15 V) and a V DS of −3 V, a memory window (V TH-shift between P and E states) of 8.6 V could be determined from the linear form of its transfer characteristics, as shown in Figure 2b.The device shows a typical p-channel characteristics with an I ON /I OFF ratio over 10 5 .The pentacene OFET with N2200 chargetrapping layer also shows a weak n-channel memory characteristics (shown in Figure 2a), due to the ambipolar semiconductor characteristics of pentacene, indicating that there are no highdensity hydroxy-related defects on the surface of PMMA. [29]Comparatively, a memory window of only 4.6 V was determined from the transfer characteristics of pentacene OFET with PVN chargetrapping layer at a set of sweeping gate-voltage of ±20 V and a V DS of −3 V, as shown in Figure 2c,d, indicating that n-type polymer semiconductor N2200 shows a much higher hole-trapping efficiency than PVN.N2200 is a donor-acceptor conjugated polymer (a copolymer of naphthalenediimide and bithiophene).The charge transportation in this polymer semiconductor relies on the hoping processes of electrons or holes between the localized states formed by the nearby - overlap, and the electron mobility is mainly influenced by the stacking density and distance of - bonds.At a negative gate-voltage holes in pentacene channel were driven into N2200 layer through tunneling or thermalcarrier excitation processes.Holes from pentacene channel were consumed by electrons of - pairs in N2200 and then trapped there due to the existence PMMA layer with a large height of holebarrier between N2200 and pentacene as shown in Figure 1b.It means that in N2200 any - stacking cite can serve as a holetrapping cite.So, an n-type polymer semiconductor should have a much larger hole-trapping efficiency than polymer electret, such as PVN and PS, etc. Correspondingly, pentacene OFET with n-type polymer semiconductor as charge-trapping layer should have a larger memory window.
After applying a set of P/E pulses with a fixed amplitude and variable pulse-widths to the gate of pentacene OFET, the device states of pentacene OFETs with PVN and N2200 charge-trapping layer were read at a V DS of -3 V by sweeping the gate voltage from 5 to −5 V, respectively.From Figure 3a,b, the pulse-width dependence of drain currents in P and E states for pentacene OFETs with N2200 was plotted in Figure 3c.At a set of P and E pulses of ±15 V/10 −3 s, the V shift between P and E states or the memory window is ≈2.7 V, indicating that the difference of two logic states are large enough to be distinguished.Pentacene OFET with PVN charge-trapping layer also shows favorable programming and erasing characteristics (see Figure S3, Supporting Information).The endurance characteristics of pentacene OFET with N2200 charge-trapping layer was characterized as shown in Figure 3d.After 4000 P/E operation cycles by using a set of P/E pulses of ±15 V/1s and a V read of 0 V, the ratio of I ON /I OFF for pentacene OFET with N2200 charge-trapping layer only suffers a little decrease.
In present research n-type inorganic semiconductor ZnO in pentacene OFET structure was employed to reduce the height of hole-injection barrier for trapping, thus reducing the working voltage of pentacene OFET.In opinion of plastic application ZnO should be substituted by n-type organic semiconductor.Further considering the low temperature processing advantage, n-type polymer semiconductor should be selected preferentially.Here, in the proposed pentacene OFET structure inorganic semiconductor ZnO was substituted with N2200, as shown in Figure 1d, in which N2200 acts as an n-type semiconductor interlayer reducing the working voltage of pentacene OFET, and on the other hand N2200 acts as the highly efficient hole-trapping dielectric.This pentacene OFET with bi-functional N2200 layer simplifies the device structure, and reduces the fabrication steps of pentacene OFETs.To reduce the whole thickness of pentacene OFET, the whole thickness of bi-functional N2200 layer was ≈18 nm, in which except for the charge-trapping layer of 10-nm N2200 corresponding to that of 10-nm N2200 in pentacene OFET with an n-ZnO interlayer, the thickness of the left N2200 functional layer corresponding to 20-nm n-ZnO layer is only 8 nm.
Figure 4 shows the transfer characteristics of pentacene OFET with bi-functional N2200 layer.At a set of sweeping gate voltage of ±15 V and a V DS of −3 V, a memory window of 7.6 V was obtained, a little lower than that for pentacene OFET with 20-nm ZnO layer.It can be ascribed to the fact that the replacement of 20nm ZnO functional layer with a thinner 7-nm N2200 layer has a  lower ability of adjusting the height of hole-barrier at the interface of pentacene, thus the height of hole-injection for trapping in the OFET structure pentacene/PMMA/N2200(18 nm)/SiO 2 /Si(p + ) should be higher than that in the OFET structure pentacene/PMMA/N2200(10 nm)/ZnO(20 nm)/SiO 2 /Si(p + ), resulting in a lower memory window.In case of a set sweeping gate-voltage ±20 V and a V DS of −3 V, the memory window for pentacene OFET with bi-functional N2200 layer reaches to 13.7 V, the field-effect mobility (μ FET ) of the OFET was calculated as 0.13 cm 2 V −1 s −1 , which benefits from the crystallized pentacene grains, as shown in Figure 4a,b.X-ray diffraction pattern of the hetero-structure pentacene/PMMA/N2200/SiO 2 /Si(p + ) as shown in Figure 5a shows that pentacene film was crystallized and prefers an <00l>-orientation.From the AFM images of each functional layer including N2200, PMMA and pentacene, as shown in Figure 5b,c,d, respectively, the flat morphologies of underlying N2200 and PMMA layers favored the growth of pentacene grains.The average grain size of pentacene is ≈0.6 μm.
The gate-voltage dependence of the drain currents in P and E states for pentacene OFETs with bi-functional N2200 layer after applying a set of pulses with the amplitude ±15 V and variable pulse-widths to the gate of pentacene OFET were also investigated (shown in Figure S6, Supporting Information).The pulsewidth dependence of drain current in P/E states for pentacene OFETs with bi-functional N2200 layer was plotted in Figure 6a.By increasing the amplitude of programming pulse to -20 V with a pulse-width of 10 −3 s, the V shift between P and E states reaches to 3.1 V.The endurance characteristics of pentacene OFET with bifunctional N2200 layer was shown in Figure 6c.After 10 000 P/E operation cycles the drain currents in P/E states of the OFET with N2200 bi-functional layer only suffer a little change.Due to the narrower bandgap of N2200 (1.5 eV) than that of PVN, the endurance characteristics of pentacene OFET with bi-functional N2200 layer was improved much better than that of pentacene OFET with PVN charge-trapping layer. [6]To investigate the possible mechanism for the little degradation of the endurance characteristics of pentacene OFET with bi-functional N2200 layer after 10 000 P/E operation cycles, we recorded the erasing enduring characteristics of the OFET by continuously irradiating the OFET with a fiber-coupled monochromatic-light probe of 635 nm (cor-responding to a photon energy of 1.95 eV), as shown in Figure 6d.The drain current in the E state shows a slow increase, and then becomes saturated.It means that there are pre-occupied holetraps with a low density in native N2200 films, in which holes can be excited by using a 635-nm photon irradiation, resulting in the slow increase of the drain current, similar to that observed in pentacene OFET with PVN charge-trapping layer. [6]In addition, the slow decrease of drain current with the increase of P/E operation cycles in the E state in the dark should be ascribed to the deep hole-traps in N2200, in which the trapped holes cannot be moved by the positive gate pulse, while they can be excited by 635-nm photons.Pentacene OFET with bi-functional N2200 layer also shows excellent retention characteristics, as shown in Figure 6b.At early stage of ≈1700 s as marked by the dotted line in Figure 6b, the drain current suffered a quick degradation, and then degrades slowly, similar with those observed in Si-based charge-trapping memory devices, [12,19,[22][23][24][25][26][27][28][29][30][31][32] which was attributed to the lateral diffusion of the trapped charges.By extrapolating the curve in Figure 6b to 3 × 10 8 s (see Figure S7, Supporting Information), an I ON /I OFF ratio of ≈200 can be inferred for the OFET after 10 years.The reported memory characteristics of pentacene OFET memory device is summarized in Table 1.

Conclusion
In summary, the incorporation of the bi-functional n-type organic semiconductor layer presents significant advancements in the performance of OFETs.The bottom-gated OFET structure, consisting of pentacene/tunneling layer/n-polymer semiconductor/blocking layer/gate electrode, demonstrates exceptional electrical switching speed, distinguished endurance characteristics, and long retention time at low working voltages.The remarkable enhancement in the electrical performance of the OFET memory can be attributed to the dual functionality of the N2200 layer.First, acting as a donor-acceptor conjugated polymer, N2200 serves as an efficient hole-trapping dielectric.Second, as an nsemiconductor, N2200 adjusts the height of the hole-injection barrier for trapping, thereby reducing the working voltage of the OFET.The reduction in working voltage and improvements in endurance characteristics make this approach highly promising for practical implementations in various applications, including non-volatile memories, detectors, and artificial synapses.

Figure 1 .
Figure 1.a) The schematic structure of pentacene OFETs with N2200 charge-trapping layer, b) The schematic drawing of the potentials of conduction band minimum and valence-band maximum (or LUMO and HOMO levels) for SiO 2 , N2200, PMMA, and pentacene.c) The schematic structure of pentacene OFETs with PVN charge-trapping layer, and d) N2200 bi-functional layer.

Figure 2 .
Figure 2. The transfer characteristics of pentacene OFET with N2200 charge-trapping layer a) in the logarithm form, b) in the linear form, and the transfer characteristics of pentacene OFET with PVN charge-trapping layer c) in the logarithm form, d) in the linear form.

Figure 3 .
Figure 3.The programming characteristics under a) −15 V and erasing characteristics under b) 15 V for pentacene OFET with N2200 charge-trapping layer.c) The switching characteristics of pentacene OFET with N2200 charge-trapping layer.d) The endurance characteristics of pentacene OFET with N2200 charge-trapping layer.

Figure 4 .
Figure 4.The transfer characteristics of pentacene OFET with bi-functional N2200 layer a) in the logarithm form b) in the linear form.

Figure 6 .
Figure 6.a) The switching speed characteristics of pentacene OFET with bi-functional N2200 layer.b) The retention characteristics of pentacene OFET with bi-functional N2200 layer.c) The endurance characteristics of pentacene OFET with bi-functional N2200 layer.d) The comparison of ON current variations measured in dark and under illumination of 635 nm light.