A Graphene Geometric Diode with the Highest Asymmetry Ratio and Three States Gate‐Tunable Rectification Ability

Graphene geometric diodes, with applications in THz detection, energy harvesting, and high‐speed rectification, have been previously constrained by graphene quality and geometry feature size. This study presents significant advancements in graphene geometric diodes by employing the h‐BN/monolayer graphene/h‐BN heterojunction and extremely precise electron beam lithography. Two distinct designs of graphene geometric diodes with neck widths of 23 and 26 nm are fabricated, the superior of which demonstrated an asymmetry ratio of 1.97, a zero bias current responsivity of 0.6 A W−1, and a voltage responsivity of 12,000 V W−1, setting new benchmarks for such devices. Integrating this device into a rectification circuit, the experimentally validate that the rectified DC output voltage can be dynamically modulated and even inverted through adjustments to the diode's gate voltage. This behavior aligns seamlessly with graphene's intrinsic tunability of charge carriers, implying promising prospects for the device's application in advanced logic circuits, bidirectional switches, and signal modulation/demodulation techniques.

DOI: 10.1002/aelm.202300695direction while encountering obstacles in the opposite direction.This operational mechanism makes the geometric diodes different from other conventional semiconductor diodes relying on potential barriers, which results in large capacitance and subsequently restricts the cutoff frequency.To maintain the ballistic transport mechanism, [3,4] these diodes require materials with a long mean free path (MFP) so that the charge carriers can move without any scattering and only get reflected at the boundaries of the device.[7][8] Ever since its unveiling in 2004, [9] the remarkable electrical properties of graphene have attracted significant research interest and practical applications.The initial introduction of graphene geometric diodes (GGD) was presented by Zhu et al., [2] who showcased a funnel-shaped GGD with a 75 nm neck width fabricated from exfoliated monolayer graphene.Their work focused on 28 THz rectification by integrating an antenna to the GGD to realize a rectenna.[12][13][14][15][16] In our previous works, through chemical vapor deposition (CVD) grown graphene, we experimentally demonstrated a funnel-shaped GGD with a 50 nm neck width [17] and a novel design of GGD featuring a 28 nm neck width, [18] which paved the way for mass production of such devices.In these works, graphene was placed on a Si/SiO 2 substrate.However, realizing high-quality graphene, which is essential for highperformance GGD, on a Si/SiO 2 substrate presents significant challenges. [19]This is primarily due to two reasons: 1) SiO 2 cannot achieve an atomically smooth surface [20] and 2) the photon scattering originating from SiO 2 significantly hampers the mobility of graphene. [21]Another concern related to maintaining high-quality graphene is the lack of shielding from environmental factors, a crucial step that was not examined in our previous research.As a result, the responsivity of the diodes, even with such small neck widths, ranged only between 0.03 and 0.17 A W −1 .
As one of the solutions to the problems described above, researchers experimented with 1D edge contact in the h-BN/monolayer graphene/h-BN (h-BN/MG/h-BN) heterostructure and were able to achieve a mobility of 140 000 cm 2 V −1 s −1 at room temperature, which is comparable to the theoretical phonon-scattering limit. [22][29] However, the dimensions of these devices are relatively large, with an overall length and width in the μm range and a neck width exceeding 100 nm.Such large dimensions reduce integration density on chips, lead to increased parasitic capacitance, and the large neck width further limits the devices' performance.Only one paper has reported two terminal GGDs, based on the h-BN/MG/h-BN heterostructure, and achieved an asymmetry ratio of 1.58.However, the neck width of the best device in this work was also large (125 nm). [30]The neck width is the most important parameter of a geometry diode, exerting a significant influence on the device's performance.Hence, minimizing the neck width in such devices represents a crucial step toward enhancing their performance.However, reducing the feature size, specifically the neck width of such devices, from more than 100 nm to a significantly smaller value presents a notable challenge, which necessitates not only advanced lithography capabilities but also a comprehensive optimization strategy to attain the desired feature size accurately and consistently (not simply as reducing the width of a line).In this study, we present two different designs for GGDs with the smallest reported neck widths of 23 and 26 nm.Our optimal device (with 23 nm neck width) demonstrates an asymmetry ratio of 1.97 and a zero bias current responsivity of 0.6 A W −1 ; both are the highest values reported to date.This device has been integrated into a rectification circuit and the experimental results confirm that the rectified DC output voltage can be modulated and inversed by altering the diode's gate voltage, which is consistent with the intrinsic tunability of graphene charge carriers.This distinctive attribute of the proposed device indicates that it can play an important role in advanced logic circuits, bidirectional switching, as well as in signal modulation and demodulation circuits.

Results and Discussion
Figure 1a-c shows the optical, scanning electron microscopy (SEM), and Raman spectroscopy mapping (2D band intensity) of the heterojunction transferred on the Si/SiO 2 (580 nm).The presence of the graphene layer is noticeable due to its different contrast with h-BN in the SEM and its different intensity compared to h-BN and SiO 2 in the Raman mapping.The h-BN layers, both upper and lower, have been intentionally chosen to exceed the size and ensure complete encapsulation of the graphene layer.In Figure 1d,e, a cross-sectional high-angle annular dark field scanning transmission electron microscope (HAADF-STEM) image of the heterojunction with its enlarged view reveals the pristine and atomic-scale flat interface between the h-BN and MG.The Raman spectroscopy in Figure 1f further confirms the high-quality MG, where two clear peaks at the G band and 2D band exhibit a ratio of ≈1:2. [31]igure 2a-c illustrates the schematic of the fabrication process of the devices, where two electron beam lithography (EBL) steps are required.The initial EBL step facilitates the formation of the edge contact with graphene.Subsequently, the second EBL step is employed to pattern the graphene into the diode geometry.The SEM images of the fabricated devices of two different designs with neck widths of 23 nm (device 1) and 26 nm (device 2) are shown in Figure 2d,e, respectively.In Figure 2f, the edge contact of the devices was confirmed by the EDX mapping of the cross-sectional image of the contact area.A distinctive feature of the graphene geometric diode is its ability to switch device direction by tuning the gate voltage.While the preferred transport direction of charge carriers is determined by the geometry, the dominant charge carrier in graphene can be switched through the gate voltage.Illustrations in Figure 2g,h provide schematics of the device's operation with varying dominant charge carriers.When holes are the dominant carriers, they effortlessly traverse the neck under forward bias but are reflected at the device boundary under reverse bias, yielding a higher forward current than the reverse current.Conversely, electrons experience the exact opposite scenario.They are reflected at the boundary under forward bias but can easily navigate through the neck under reverse bias, resulting in a forward current that is smaller than the reverse current.
Figure 3a-d compares the measurement results of the fabricated devices 1 (top panel) and 2 (bottom panel).The gate-voltagedriven switching capability is affirmed by the measured I-V characteristics of both devices, as depicted in Figure 3a.Here, the red curves represent the scenario where holes predominate, while the blue curves represent the case when the electrons are the dominant charge carriers.For both devices, we choose two gate voltages at which the forward and backward currents have maximum disparity, corresponding to their highest hole and electron mobility points.Figure 3b shows the measured Dirac curves and extracted mobility of the two devices using Equation (1).The MFP was subsequently derived from Equation (2). [32]For device 1, the maximum hole and electron mobility are 12 800 and 7200 cm 2 V −1 s −1 , corresponding to MFP values of 120 and 54 nm, respectively.These values are much lower than those of device 2, which shows a maximum hole and electron mobility of 131 000 and 185 000 cm 2 V −1 s −1 , with corresponding MFP values of 485 and 907 nm, respectively.The decline in mobility of device 1 can be attributed to the unwanted doping on the graphene during the fabrication process. [33,34]However, the MFP for both devices substantially surpasses the neck width, confirming complete ballistic transport in a large region surrounding the device's neck. (1) where C ox is the capacitance per unit area of the SiO 2 layer, L is the device length, W neck is the neck width (the reason of using neck width as the effective channel width is described in the Figure S6, Supporting Information), h is the Plank's constant, and n is the charge concentration of dominant charge carriers, respectively.One crucial parameter for graphene geometric diodes is the asymmetry ratio, which is the ratio of the current at a fixed forward and backward bias and can be expressed as: [35] A = An A > 1 suggests the forward current exceeds the backward current, indicating positive rectification.Conversely, A < 1 represents negative rectification.The farther A deviates from one, the stronger the device's rectification ability.Figure 3c illustrates how the asymmetry ratio of both devices varies with gate voltage at different V DS values.For each device, the asymmetry ratio changes from a set of values greater than 1 to less than 1, representing the switch of the dominant charge carrier type from holes to electrons.Meanwhile, the trend in the asymmetry ratio plot should align with the trend in mobility.For device 1, the asymmetric ratio reaches a maximum at V GS = −20 V and drops to 1 at ≈V GS = 3 V, then further declines to a value of 0.6; this trend is well aligned with that in the mobility plot.For device 2, some misalignments exist between the trends in the asymmetric ratio and mobility: first, between the point where A = 1 at V GS = −10 V and the minimum mobility point at V GS = −8 V, and second, between the maximum reverse asymmetry ratio at V GS = −7 V and maximum electron mobility point at V GS = −1 V.[38][39] Other than these small misalignments, overall the asymmetry ratio and mobility trends are well-matched for device 2. Another noticeable pattern that can be observed is the increase in the asymmetry ratio with the increase of V DS at a fixed V GS , which is consistent with the behavior of other diodes.For a typical diode, the forward current increases exponentially with increasing V DS , while the backward current increases much slower than the forward current, leading to a larger asymmetry ratio.For both devices, the maximum asymmetry ratio is achieved at V DS = ±1 V.For device 1, a maximum asymmetry ratio of 1.97 is achieved at V DS = ±1 V and V GS = −20 V, which is also the maximum mobility point.Another equally important metric is the current responsivity, which reflects the DC output current a device produces per unit input power and can be derived from the I-V characteristics using Equation (4): [2] responsivity = 1 2 where I′(v) and I′′(v) are the first and second order derivatives of the I-V characteristic, respectively.For device 1, at the point where the asymmetry ratio is 1.97, the zero-bias current responsivity reaches 0.6 A W −1 .Remarkably, these metrics are the highest values of a graphene geometric diode reported to date.In contrast, device 2 shows a maximum asymmetry ratio of 1.25 at V DS = ±1 V and V GS = −7 V, despite having much higher mobility.This can be attributed to two principal factors influencing the asymmetry ratio of the geometric diode: 1) the geometry of the device, which significantly affects the movements of the charge carriers and 2) the mobility of the materials, which ensures that no scattering occurs within the ballistic region.Device 1 shows geometry design as compared to Device 2, resulting in much enhanced performance.
The superiority of the geometry of device 1 can also be validated through Figure 3e, where the two devices are compared using the Monte Carlo simulation method. [2]In the simulation results, the asymmetry ratios for both devices exceed the measured values, which is commonly seen in the simulations of geometric diodes [10][11][12][13][14][15][16] because the simulations do not consider the interactions between different charge carriers and assume perfectly specular reflection at the device edges.For real graphene devices, the edges cannot be perfectly smooth, and the impurities can be introduced into the graphene edge during the fabrication process, both of which reduce the asymmetry ratio of the fabricated devices.However, the simulation results can provide invaluable relative comparisons between different designs, directing efforts toward geometry optimization.Moreover, we measured the voltage responsivity of these two devices at the frequency of 1 kHz as illustrated in Figure 3d.The voltage responsivity is the open-circuit DC output voltage per unit input power.The responsivity of both devices also changes with the gate voltage, maintaining congruence with the mobility trends.Notably, the highest measured voltage responsivity of device 1 reaches a value of 12 000 V W −1 , which establishes a benchmark for a single graphene geometric diode.Unfortunately, the measurements for device 2 could not be completed because the device got burnt due to the consistent passing of current during the measurements.Due to the small neck width, the current density at the neck is very large, which generates a large amount of heat to damage the device.
An additional device, termed device 3, with a neck width of 22 nm and the same design as device 2, was subjected to measurements under a high vacuum condition (<10 −6 Torr) across various temperatures for low-temperature study.The devicemeasured I-V characteristics at zero V GS are shown in Figure 3f, with the extracted asymmetry ratio shown in Figure 3g.With diminishing temperature, the asymmetry ratio diverges from 1.[42] Figure 3h shows the asymmetry ratio at V DS = ±1 V for each temperature.It is worth mentioning that this device has poor performance at room temperature, but its asymmetry ratio reaches a value of 0.6 at 8 K, comparable with the minimum asymmetry value of device 1.This improvement highlights the device's potential for applications in low-temperature environments and also corroborates the ballistic transport mechanism.It is important to note that temperatureinduced changes should not significantly impact the doping of graphene.Therefore, observing an improvement in device performance under low temperatures with no changes in graphene doping strongly supports the explanation that the observed asymmetry characteristics primarily come from the device's geometry rather than from graphene doping effects.
To test the real rectification ability, device 1 was integrated into a basic RC half-wave rectification circuit.The circuit schematic is shown in Figure 4a, where the signal from the signal generator was modulated by the Sine out of the lock-in amplifier and the modulated signal was delivered to the device.Then, one channel of the lock-in amplifier was used to measure the rectified DC output voltage on the resistor load. [43]The applied voltage on the device was monitored by an oscilloscope fixed at a peak value of ≈0.75 V, at which the device remains at a relatively high rectification ability without damage from the heat.Figure 4b illustrates the modulation of the DC output voltage by adjusting the gate voltage, revealing three distinct operational states.These states mirror the three conditions of the Dirac cone depicted in the figure .When the gate voltage lies to the left of the Dirac point, hole carriers predominate, placing the device in a "positive on" state.Consequently, the rectified DC output is positive.Conversely, electron carriers dominate when the gate voltage shifts to the right of the Dirac point, placing the device in a "negative on" state.Therefore, the rectified DC output is reversed.Moreover, if the gate voltage is exactly on the Dirac point, the device loses the rectification ability, rendering it in an "off" state.To gain a clearer insight into the device's state transitions, we map the asymmetry ratio across various V GS and V DS values in Figure 4c, in which the two distinct regions can be seen.The red-shaded region denotes the "positive on" state, while the blue-shaded area indicates the "negative on" state.The intermediate zone, where the asymmetry ratio ≈1, represents the "off" state of the device.Moreover, in the exceptionally small V DS region (< 0.1 V), the shade is close to the "off" region, implying the device exhibits relatively weak rectification ability at these levels.Overall, this gate tunability positions the device as a promising candidate for numerous applications, such as logic gates and signal modulation/demodulation circuits.
To investigate the frequency-dependent rectification performance of the device, we measured the DC output of the device across various input voltages up to 2 GHz.The DC output drops with increasing frequency, as revealed in Figure 4d.This reduction, however, is not inherent to the device but rather arises from the constraints of the employed circuit.Utilizing standard DC probes to test the device introduces impedance mismatch issues at high frequencies.As the frequency increased, a significant portion of the signal power faced reflection at the probe's tip due to the impedance mismatch between the probes and the device electrodes.Thus, the input power delivered to the device was reduced.Nevertheless, we observed a DC output voltage persisting up to 2 GHz.Increasing the amplitude of the input signal might allow us to discern the output signal at even higher frequencies but poses a risk of damaging the device.Therefore, the highest input voltage we applied was 0.5 V.In Figure 4e, we compared our device with a commercial 1N4148 signal diode with a cutoff frequency of ≈240 MHz (measured in Figure S2d, Supporting Information) at a fixed input signal with a magnitude of 0.4 V.At frequencies ≤100 MHz, the commercial diode shows much higher DC output than our device 1.However, at above 100 MHz, due to the cutoff of the commercial device, the DC output rapidly plummeted to the noise level, while our device still exhibits higher DC output than the noise level.This observed behavior further corroborates the influence of external circuit limitations.

Conclusion
In this study, two distinct designs of graphene geometric diodes with the smallest area and neck widths of 23 and 26 nm were fabricated on the high-quality h-BN/MG/h-BN heterojunction through extremely precise EBL processes.The measured results of the best device show the highest asymmetry ratio of 1.97, zerobias current responsivity of 0.6 A W −1 , and voltage responsivity of 12 000 V W −1 .These values set new benchmarks in the field of graphene geometric diodes.The measured performance comparison of the two designs matches well with the Monte Carlo simulation comparison, further strengthening the reliability of our results.Additionally, the temperature-dependent study of one further device indicates the performance of graphene geometric diodes can be substantially enhanced under low temperatures, highlighting their potential for low-temperature applications.Moreover, our work demonstrates the unique gatetunability of the graphene geometric diode in a rectification circuit with three distinct states of the devices observed.tive approach and promising results showcased in this study pave the way for the potential integration of these diodes into intricate logic circuits.

Experimental Section
Preparation of the h-BN/MG/h-BN Heterojunction: We followed and modified the previously reported assembly technique to prepare the high-quality h-BN/MG/h-BN heterojunction. [22]First, h-BN and graphene flakes were mechanically exfoliated on Si wafers, and suitable thicknesses of top and bottom h-BN layers and monolayer graphene were located and marked under an optical microscope.The bottom layer h-BN with a thickness ranging from 20 to 30 nm was selected to easily pick up the graphene and the top layer h-BN.The top layer h-BN with a thickness ≈10 nm was selected to easily etch and observe the graphene location.Meanwhile, a transparent tape attached a small piece of polydimethyl siloxane (PDMS) to a microscope slide as a substrate.A thin layer of poly-propylene carbonate (PPC) was attached to the PDMS as the adhesion layer to pick up the selected h-BN and graphene flakes.At a stage temperature ≈40 °C, the first bottom h-BN layer was picked up by the strong adhesion of the PPC layer, while the MG and second h-BN layer were picked up by the van der Waals force between the h-BN and graphene, and between the h-BN and h-BN, respectively.After the heterojunction was successfully attached to the PPC layer, the substrate was heated to 90 °C to soften and detach the PPC layer.This PPC layer was then covered on a Si/SiO 2 wafer and annealed at 350 °C for 2 h, during which the PPC layer was decomposed, leaving the h-BN/MG/h-BN heterojunction on the Si/SiO 2 wafer.The wafer was p-type, boron-doped Si (resistivity: 0.05-0.2Ω cm) with 590 nm SiO 2 .The low-resistivity Si was used as a back gate for all the devices.
Image Characterization: The heterojunction's SEM image was performed using a Thermo Scientific Helios 5 UX Dual Beam scanning electron microscope.Raman spectroscopy data were gathered through a WITec Apyron confocal Raman instrument.The cross-sectional lamella sample was prepared using the focused ion beam (FIB) technique with the previously mentioned SEM apparatus.This ion beam targeted the sample's bulk surface, bisecting it precisely where the heterojunction interfaced with the metallic electrodes.Subsequently, this lamella was examined using a FEI Titan Themes Cubed G2 300 TEM, operating at an acceleration voltage of 300 kV.
Device Fabrication: First, a layer of PMMA 459K A4 electron beam resist was spin-coated and exposed by EBL to form the electrode pattern, followed by a mixture of O 2 and CHF 3 plasma etching to expose the graphene edge.Then a layer of Ti/Au (5 nm/30 nm) was evaporated on the sample and lifted off in acetone to form the 1D edge contact with the graphene.Before patterning the graphene, we checked the connection by measuring the Dirac curve of the graphene (Figure S2b, Supporting Information).To fabricate the graphene geometric diode, another layer of electron beam resist ARP6200.04 was spin-coated and exposed by EBL to form the diode pattern as a mask to etch the h-BN/MG/h-BN heterojunction.Then, the sample was etched again using a mixture of O 2 and CHF 3 plasma to form the graphene geometric diodes.
During the process, the AR-P 6200.04 electron beam resist was spincoated with a spinning speed of 6000 rpm, achieving a resultant thickness of ≈80 nm.The resist was then baked for 90 s at a temperature of 150 °C.High-resolution geometric diode patterning during the EBL process was executed using the JBX-6300FS EBL tool with an acceleration voltage of 100 kV and a beam current of 100 pA.Post-exposure, the sample underwent development using AR600-546 for 1 min.An etching time of 30 s was employed to expose the edge, which etches roughly 20 nm of h-BN.For the final patterning of the graphene geometric design, an etching time of 1 min was utilized to ensure successful patterning of the graphene.
Monte Carlo Simulation: The simulation was based on the Drude model to simulate charge dynamics within the device.In this simulation, charge carriers were regarded as solid balls that moved based on both the random Fermi velocity determined by the material and the drift velocity determined by the electric fields present in the device.The MFP path, which could be derived from the Dirac curve of the device, is required to input into the simulation to determine the collision time of the charge carriers.During each collision, charge carriers were specularly reflected at the device boundaries.The current at each given bias was calculated based on the times of the charge carriers passing through a fixed vertical boundary per unit time.To ensure a balance between computational accuracy and efficiency, a parameter of 5 × 10 4 total collisions was set in the simulation.
DC Characterization: The DC characterizations of the devices were conducted utilizing a Keithley 4200 semiconductor parameter analyzer with a probe station.During measurement, the gate voltage was applied from the metal stage of the probe station.All the measurements were performed in the ambient environment.
Low-Temperature Characterization: The low-temperature characterization was performed under a high-vacuum condition (4 × 10 −6 mbar) in Lake Shore Cryotronics cryogenic probe stations with Keysight B2912A precision source/measure unit.
AC Characterization: The responsivity measurements were performed using a Agilent 33210A Function/Arbitrary signal generator, a Fluke 17B+ digital multimeter, and a Keysight InfliniiVision DSO-X 3024T oscilloscope.A 100 kΩ resistor was placed in series with the diode during the measurement.The oscilloscope was used to monitor the RMS voltage on the resistor.Then the power delivered to the diode was calculated using the total output power from the signal generator minus the power on the resistor.The open-circuit DC output was measured using the multimeter.
An Agilent E8257D PSG analog signal generator and a Stanford SR830 DSP lock-in amplifier were used for the rectification measurement.This measurement technique was commonly employed in the measurement of the optical rectenna.

Figure 1 .
Figure 1.Imaging characterization of the h-BN/MG/h-BN heterojunction.a) Optical microscope image.b) SEM image.c) Raman spectroscopy mapping of the graphene at the 2D band.d, e) HAADF-STEM image.f) Raman spectroscopy of the monolayer graphene.

Figure 2 .
Figure 2. Schematic illustration of a) the h-BN/MG/h-BN heterojunction, b) 1D edge contact added on the heterojunction, and c) graphene geometric diode with edge contact.SEM images of d) fabricated device 1, and e) fabricated device 2. f) EDX mapping image of the cross-section of the heterojunction.Schematic illustration of the device working mechanism when g) holes are the majority charge carriers, and h) electrons are the majority charge carriers.

Figure 3 .
Figure 3.Comparison between device 1 (top panel) and device 2 (bottom panel).a) I-V characteristics at maximum hole and electron mobility points, b) mobility and Dirac curves, c) asymmetry ratio versus V GS at five different V DS values,and d) voltage responsivity versus V GS. e) Simulated and measured asymmetry ratios at the maximum mobility points of the two devices.Temperature-dependent measurements of f) I-V characteristics at zero V GS , g) asymmetry ratio versus V DS , and h) asymmetry ratio at V DS = ± 1 V of device 3.

Figure 4 .
Figure 4. a) Schematic illustration of the rectification circuit.b) Measured DC output voltage of the rectification circuit at different V GS .c) Asymmetry ratio mapping of device 1 at different V GS and V DS .d) Measured DC output at different frequencies.e) measured DC output of device 1 and a commercial 1N4148 diode.