High‐Frequency fT and fmax in Organic Transistors: Performance and Perspective

In state‐of‐the‐art organic transistors, the transit frequency fT is reported to be fT = 40 MHz for vertical organic transistors, where a voltage‐normalized fT corresponds to 0.36 MHz V−2. The reported highest fT for conventional organic transistors is fT = 160 MHz, where the voltage‐normalized fT is 0.1 MHz V−2. While the reported transit frequency fT of n‐MOSFETs for silicon technology when normalized by the applied biases exceeds 300 GHz V−2. The reported carrier mobility of organic semiconductors is over 100 cm2 V−1 s−1, which is almost an order of magnitude lower than that of silicon. However, the transit frequency fT of organic transistors lags far behind silicon technology by about six orders of magnitude at a comparable device length below 300 nm. In this work, a technology computer‐aided design (TCAD) simulator is adjusted to the experimental DC and AC characteristics of the 200 nm device length vertical organic permeable‐base transistors (OPBTs) based on C60 as semiconductor. The AC performance of the devices is investigated and quantitatively analyzed the influence and contribution of key design, structure and material parameters that determine fT and fmax. The feasible ways to enhance and optimize the highest achievable fT and fmax are identified to reach the GHz−range$\rm GHz-range$ and overcome the limitations to high‐frequency operation in organic transistors.


Introduction
Transit frequency f T (current gain) and maximum oscillation frequency f max (power gain) are important Figuresof-merit (FoM) [1] in high-frequency applications of transistors [2] such as radio frequency (RF) circuits and communication systems. [3]These parameters determine the frequency limits at which the transistor can effectively amplify or process signals. [4,5]Both parameters are influenced by various factors in organic transistors, including the material properties, device geometry, fabrication techniques, and operating conditions.Enhancing these frequencies is a key objective in organic thin-film transistors (OTFTs) design and optimization, as it allows for improved speed, efficiency, and functionality in electronic devices. [6,7]he transit frequency and carrier mobility have been analyzed and reported for OTFTs, highlighting the feasibility of achieving a transit frequency of f T = 1GHz. [8]A roadmap to achieve gigahertz organic transistors has been derived and thoroughly discussed, emphasizing the importance of addressing contact resistance in sub-micrometer devices. [9]If necessary, the dynamics of the charge trap can be taken into account. [10]Additionally, organic bipolar transistors, which present an alternative strategy for achieving GHz frequencies, are reported in detail in Ref. [11].According to a theoretical physical model, it has been reported that achieving gigahertz operation in highly downscaled OTFTs is only possible, if certain conditions for carrier mobility and charge injection barriers are met. [12]Various lithography methods and their impact on reaching a high transit frequency in OTFTs have been reviewed. [13]A comprehensive analysis of the dynamic performance and high-frequency behavior of OTFTs has been conducted based on a compact model. [14][17] OPBTs exhibit promising potential as candidates for high DC and AC performance, [18][19][20] with the ability to approach the GHz high-frequency.This is primarily due to their unique feature of short channel length, which is determined by the thickness of the layers and can be scaled to the 100 nm regime without cost-intensive structuring techniques. [21,22]Additionally their dual-base structure, [23] DC performance, [24] and small-signal measurements have been studied and reported. [1]n this work, our fabricated OPBTs and their measured data are used for adjusting the corresponding DC and AC Technology Computer-Aided Design (TCAD) simulations.We demonstrate that the density of pinholes D ph , rather than their number N Pin , determines the f T and f max of fabricated OPBTs.Therefore, OPBTs with any number of pinholes have the same f T and f max as a single pinhole (1 Pin ) with the same pinhole density, which imposes the internal parasitic capacitance.The significance and influence of most important parameters like internal and external parasitic capacitance, organic semiconductor (OSC) thickness, carrier mobility and contact resistance of OPBTs are investigated.We have conducted a quantitative analysis of the AC performance using the calibrated TCAD simulator, "Synopsys Sentaurus". [25]This analysis is a necessary step toward the development of simplified device models and circuits.Quantitative evidence demonstrates the potential for improvement in both f T and f max using the mentioned material and geometrical parameters.

Device Fabrication, Measurements, and TCAD Simulation
A glass substrate was thermally evaporated with a thin layer of chromium/gold (Cr/Au) by vacuum evaporation.Then, a C 60 layer was deposited on top of the Cr/Au layer, followed by a base aluminium layer.The base aluminium layer was partially anodized to form a thin layer of aluminium oxide at its edges, which served as a passivation layer and also helped in the formation of pinholes.Next, another C 60 layer was deposited on the aluminium oxide layer by vacuum evaporation.Finally, a top aluminium layer was deposited on the C 60 layer and patterned into an emitter electrode. [20]he DC and AC experimental data of an n-type C 60 OPBT have been reported, along with a technique that enables small-signal characterization of such devices. [1]This device has been used as a reference for calibrating the simulator to ensure accurate and actual simulation results and to enable realistic extrapolation to the different dimensions and parameters not yet experimentally achievable.Figure 1a shows a simulated 3D OPBT structure and a schematic cross-section of the fabricated OPBTs is shown in Figure 1b with three parallel electrodes separated by two semiconducting C 60 layers.The device dimensions and the material parameters used in the simulations are listed in Table 1.The simulated collector current I C as a function of the base-emitter voltage V BE is in good agreement with the measured data, as shown in Figure 1c on both linear and log scales.Please note that the TCAD simulation is shown only at V CB = 1 V because there is insignificant variation between different V CB based on experimental data, which is sufficient for our study goal.
The measured current gain |h 21 | of the fabricated OPBT shows good agreement with the simulation results (see Figure 1d).The details of the AC simulation will be discussed in the following section.The calibrated DC and AC simulations with the experimental data of a fabricated device is used to further study the performance analysis and perspectives of OPBTs quantitatively.
We aim to provide some guidance on certain aspects.Currently, parameters related to pinhole dimensions, such as the The device dimensions and material parameters are given in Table 1.
length of a single pinhole, pinhole diameter, and pinhole density, are not controllable by fabrication processes.Due to the nanometer dimensions of the pinholes, there is not a straightforward solution for process control, and pinholes can only be visualized using electron microscopy. [24]Wet-chemical anodization may allow us to adjust pinhole parameters using methods like constant current or constant voltage anodization, and by controlling the anodization temperature.However, this is an area of ongoing research.
Parameters like semiconductor thickness, base layer thickness, and oxide thickness can already be adjusted through process conditions.For instance, the OSC thickness can be reduced to approximately 100 nm (on both the emitter and collector sides) without risking particle-related short circuits.The base layer thickness can be precisely controlled during the metallization process, and we have demonstrated that the base layer can be as thick as 100 nm if anodization is used.Anodization also allows for precise control over the oxide thickness up to 10nm. [20]deally, contact resistance is completely eliminated, which could be achieved through strong doping and appropriate choice of electrode materials.However, in the parameter range we studied, contact resistance does not significantly impact f T , as the bulk resistivity of the semiconductor still limits the transconductance.This leaves charge carrier mobility and OSC thickness as the primary parameters to increase f T .As we have previously shown, a charge carrier mobility of up to 10 cm 2 V −1 s −1 is achievable in the vertical direction using organic semiconductors, enabling GHz − operation range. [26]

Small-Signal AC Analysis of OPBTs
A small-signal frequency analysis was conducted to determine the transistor's admittance parameters, also known as Yparameters. [27]The currents are defined by the following matrix equation, in terms of the Y-parameters matrix and the voltages: The admittance matrix is given by: where A represents the conductance matrix,  is the frequency and C is the capacitance.The relation between the small-signal voltage and the small-signal current at a given operating point is as follows: The small-signal current gain h 21 of an OPBT is calculated by: The measured current gain |h 21 | of a fabricated OPBT is used to determine the f T and extrinsic parasitic capacitance C Par-Ex .The calibration results are shown in Figure 1d, where an extrinsic parasitic capacitance value of C Par-Ex = 2 pF exhibits the best agreement between experimental data (symbols) and simulation results (solid line at C Par-Ex = 0 and dash-line at C Par-Ex = 2 pF) at I C = 1 mA.The extrinsic parasitic capacitances are imposed by the overlap between the base electrode with the emitter and collector electrodes from outside of the active area of OPBTs (see Figure 2a).The estimated dielectric capacitance of the base dielectric of the fabricated OPBT with aluminum oxide would be approximately C diel ≈ 1.3 nF.Remarkably, the simulation results based on Equation (4) shown in Figure 2b reveal that f T, i remains independent and unaffected by the number of pinholes.Hence, we can conclude that the OPBT operates like multiple parallel transistors formed by a single pinhole.Using these simulation results, we can formulate and develop our understanding and elucidate the underlying physics as follows.

Transit Frequency f T at Fixed D ph
The extrinsic transit frequency f T-Ex for an OPBT can be defined as follows, taking into account the impact of external parasitic capacitance: [28] As Equation (6) shows, the intrinsic transit frequency f T, i is independent of the number of pinholes.Therefore, this equation effectively represents the intrinsic transit frequency f T, i of the fabricated OPBT.The density of pinholes determines the internal parasitic capacitance C Par-In and the number of pinholes depending on the size of fabricated devices.The internal parasitic capacitance C Par-In of an OPBT is determined by the overlap between the base and collector, as well as base and emitter, in its active area (refer to Figure 2a).
Hence, the AC analysis is presented for a single pinhole throughout the rest of the text.This significantly simplifies the analysis, optimization, simulation, and modeling of the smallsignal behavior of OPBTs.To optimize the AC behavior, one must consider a single pinhole and incorporate it with the external parasitic capacitance.This will determine the AC behavior of fabricated OPBTs.
Please note that the parameters leading to the DC and AC calibration, as shown in Figure 1c,d (Table 1), are used in all subsequent simulations and figures, except for those parameters specifically mentioned in the caption or legend of each figure.The same principle applies to the prediction of GHz operation.Furthermore, the scaled contact resistance is applied as needed, based on the Where, R x is the calibrated contact resistance of the fabricated device, A 0 is the fabricated active area, R x is the resistance of any scaled area, A x is the corresponding scaled area.

f T and f max in Terms of Bias or Current
A small-signal frequency analysis was performed using the spot frequency method to determine the f T and maximum frequency of oscillation f max . [28,29]The transistor cut-off frequency f T , determined using the spot frequency method, is given by: where f 0 is the spot frequency (we use f 0 = 1 MHz here), Y BB and Y CB are frequency dependent (2).Here, we consider them as f 0 dependent.Figure 3 shows the f T as function of the applied V BE (Figure 3a) and the collector current I C (Figure 3b) at V CE = 1.54 V. Since the frequency depends on either V BE or I C , we use V BE as the variable for simplicity in the rest of the text and analysis.Figures 3 and 1d show the same transit frequency f T for the same operating point, thus further proving the validity of the spot frequency method.
The following expression is used to determine the maximum frequency of oscillation, denoted as f max , of the device: [30] Please note that Y-parameters depend on the frequency (2) (here f 0 ). Figure 3 shows f max as a function of the applied V BE (see Figure 3a) and the collector current I C (see Figure 3b) based on calibrated TCAD for the OPBT at V CE = 1.54 V.
Analysing the f T and/or f max using spot frequency methods demonstrates the potential of OPBT at different applied biases, as shown in Figure 4, rather than at a single operation point (Figure 1d).Therefore, the device has the potential to provide almost six times higher f T (see Figure 4 at V CE = 3 V and V BE = 1.3 V) than the measured one (Figure 1d).Depending on the application requirements and operation points, Figure 4 shows the   possibilities and potential of OPBTs to provide the f T at different operation points.This method also enables to demonstrate the peak f T and f max of OPBTs and the required biases.

How C Par-In Affects f T and f max
The internal parasitic capacitance, which results from the overlap of the base electrode with the emitter and collector in the active area (as shown in Figure 2a), is one of the main limiting factors for both f T and f max .
Figure 5a illustrates the dependence of f T on V BE for various device lengths L D at V CE = 1.54 V.The device length L D corresponds to the length of a single pinhole (see Figure 2a), which determines the density of pinholes and vice-versa, as well as the internal parasitic capacitance C Par-In of the fabricated OPBTs.The device length L D = 150 nm corresponds the fabricated device with a pinhole density of D ph = 50 μm −2 .The smaller the device length L D , the is the density of pinholes and the smaller is the internal parasitic capacitance.The impact of pinhole density and pinhole diameter on OPBT DC characteristics has been thoroughly investigated and reported in Ref. [24].Our finding indicates that within the experimentally obtained range of pinhole diameter and density, neither parameter imposes a significant influence e.g., on transconductance, threshold voltage, on/off ratio etc.This can be attributed to the fact that for a pinhole diameter ranging from 2 to 20 nm, the channel can be fully depleted by the oxide.Consequently, the transconductance is limited by the bulk conductivity of the semiconductor, rather than the density of pinholes, down to a density of 50 μm −2 .
The peak f T and f max as a function of the device length are shown in Figure 5b at V CE = 1.54 V.There is room for improvement and achieving the f T of the OPBT by optimizing and reducing the internal parasitic capacitance (Figure 5a) up to 38 times higher than the measured f T (Figure 1d).We show the result at V CE = 1.54 V in order to keep them comparable with the measured data.However, the devices have the potential to reach even higher f T depending on the operation point (Figure 4).
The rest of the analysis will be shown for f T in terms of V BE only.However, the same analysis are applicable to both f T and f max in terms of V BE or I C .

Impact of OSC Mobility in f T and f max
The estimated low field mobility μ 0 = 0.006 cm 2 V −1 s −1 of C 60 in the fabricated OPBT based on the simulations shows good agreement with the experimental data (Figure 1c).This mobility value is reasonable compared to the previously reported mobility μ 0 = 0.06 cm 2 V −1 s −1 for the same devices. [21]The experimental value has been determined in the space-charge-limited current (SCLC) regime with full occupation of tail states, while TCAD aims to cover the full range of operation by providing a mean value of mobility that include the lower mobility of the tail states.
Figure 6a shows the achievable f T as function of applied V BE at V CE = 1.54 V for different mobilities up to μ 0 = 60 cm 2 V −1 s −1 .A mobility of up to μ 0 = 60 cm 2 V −1 s −1 in organic semiconductors is feasible, considering that some reported organic semiconductor mobilities exceed even 100 cm 2 V −1 s −1 . [31]Therefore, there is a big room to improve the f T of fabricated OPBTs with mobility.Figure 6b shows the peak f T and the static power dissipation density P S as a function of mobility at V CE = 1.54 V.
Therefore, by improving the carrier mobility of the OSC in an OPBT up to a feasible value of μ 0 = 6 cm 2 V −1 s −1 , [32] the f T of the fabricated devices will be increased up to 110 times as shown in Figure 6a.The generated power per unit area approaches up to the P S ≈ 150 W cm −2 at higher mobility where self-heating effects are still negligible. [33]function of V BE is shown at C Par-Ex = 2 pF, C Par-Ex = 0, and V CE = 1.54 V.In an ideal case of C Par-Ex = 0 the f T of the fabricated OPBT would increase by almost two times, as seen in Figure 7a).On the other hand, reducing the OSC thickness to 10nm could potentially increase the f T of the fabricated device by almost eight times, as shown in Figure 7b.

Impact of C
Reducing the thickness of OSC will increase the parasitic capacitances.However, it will also reduce the parasitic access resistance, increase the electric field which in turn will increase the current and f T in the OPBT.In fact, according to Figure 7b, the dominant part comes from lower parasitic access resistance and higher electrostatic rather than parasitic capacitances.
Quantifying the impact of various parameters on the f T performance helps to identify and prioritize the areas of device design and optimization that need to be carefully considered.

Impact of Pinhole Diameter and R E/C in f T and f max
The pinhole diameters and contact resistances (emitter and collector) can vary either intentionally or unintentionally.To quantify the effect of these variations on the f T of the fabricated device, we examine how the pinhole diameter and contact resistance influence the f T versus V BE at V CE = 1.54 V. shows the results of this analysis.details regarding the impact of pinhole diameter on OPBT DC performance has been reported in Ref. [24].
Figure 8a shows that the pinhole diameter has a minor effect on the f T .Therefore, pinhole diameter is not a suitable parameter for improving f T of OPBTs as it can not be accurately controlled through experiment.However, it also indicates the sensitivity of f T to an undesired variation of pinhole diameter.For example, if the target pinhole diameter is 8 nm, the expected peak f T is f T = 2.2 MHz.A 50% variation in pinhole diameter down to 4 nm would result in a less than 10% decrease in peak f T to f T = 2 MHz.A 100% increase in pinhole diameter to 16 nm would cause a maximum increase in peak f T to f T = 2.6 MHz.
The peak f T of the fabricated device is f T = 2 MHz at R E/C = 2 × 10 7 Ω.Reducing the contact resistance would slightly increase the f T to f T = 2.3 MHz, as Figure 8b.This implies that the unwanted variation in pinhole diameter and/or contact resistances has a small impact on the f T , depending on the operation point and V BE value.This would lead to a more stable AC performance of OPBTs.
By simulating the fabricated device with the predicted specific parameters: L D = 25 nm, T OSC = 10 nm, and μ 0 = 6 cm 2 V −1 s −1 , we can reach a voltage-normalized f T of over 10 GHz V −2 in OPBTs.Figure 9a shows the current gain |h 21 | versus frequency at V BE = 0.54 V, and V CE = 1.54 V. Figure 9b shows the transit frequency in terms of V BE at V CE = 1 V.Further analysis is needed to find an even better operating point for the device in terms of achieving a higher f T for this OPBT.However, depending on the feasibility of fabricating OPBTs with the mentioned dimensions and parameters, the f T could move toward the GHz region by fabricated actual devices and experimentally.In fact, this simulation study, which is calibrated to the fabricated OPBT and experimental data, demonstrates how to optimize the design of OPBTs and serves as a roadmap for pushing organic devices toward the GHz regime.
The same analysis of f T and peak f T for the different parameters can be applied to f max and peak f max .

Conclusion
This paper has demonstrated, based on TCAD simulations, the feasibility of achieving GHz range for both f T and f max in organic transistors with optimized device design.We have revealed that the intrinsic transit frequency f T, i of the fabricated OPBTs is unaffected by the number of pinholes, which facilitates the analysis, optimization, design, development, simulation, modeling and application of OPBTs.We have addressed the factors that limit the frequency response of OPBTs and also established how f T and f max vary and can be enhanced with different material and structural parameters.
By reducing the internal parasitic capacitance, increasing the mobility up to μ 0 = 6 cm 2 V −1 s −1 , as well as decreasing the OSC thickness down to T OSC = 10 nm, the AC performance of fabricated OPBTs can be improved by 38, 110, and 8 times, respectively.This results in a voltage-normalized f T over 10 GHz V −2 of OPBTs.The gap to silicon technology is mainly due to the relatively low actual mobility of OSCs.The intensive high mobilities reported for OSCs may require more detailed investigation, precise re-characterization, and accurate re-extraction for verification.

Figure 1 .
Figure 1.Organic permeable-base transistor OPBT a) 3D OPBT structure, showing electrostatic potential at V BE = V CE = 2 V, b) schematic crosssection of the fabricated and simulated OPBT, c) experimental current as a function of V BE data (symbols) and TCAD simulation results (solid lines) for an OPBT, d) measured (symbols) small-signal current gain |h 21 | versus frequency () compared with TCAD simulation results (dash-line at C Par-Ex = 0 and solid line at C Par-Ex = 2 pF at I C = 1 mA (V BE = 0.54 V, V CE = 1.54 V, and the static power dissipation density P S = 3.8 W cm −2 ).The device dimensions and material parameters are given in Table1.

Figure
Figure 2a illustrates the components of external parasitic capacitance (C Par-Ex ) and internal parasitic capacitance (C Par-In ). Figure 2b depicts the simulated small-signal current gain |h 21 | versus frequency, considering different numbers of pinholes while maintaining a fixed pinhole density (D ph = 50 μm −2 ) and setting external parasitic capacitance to zero (C Par-Ex= 0), V BE = 0.54 V and V CE = 1.54 V.Remarkably, the simulation results based on Equation (4) shown in Figure2breveal that f T, i remains independent and unaffected by the number of pinholes.Hence, we can conclude that the OPBT operates like multiple parallel transistors formed by a single pinhole.Using these simulation results, we can formulate and develop our understanding and elucidate the underlying physics as follows.The extrinsic transit frequency f T-Ex for an OPBT can be defined as follows, taking into account the impact of external parasitic capacitance:[28] Figure 2a illustrates the components of external parasitic capacitance (C Par-Ex ) and internal parasitic capacitance (C Par-In ). Figure 2b depicts the simulated small-signal current gain |h 21 | versus frequency, considering different numbers of pinholes while maintaining a fixed pinhole density (D ph = 50 μm −2 ) and setting external parasitic capacitance to zero (C Par-Ex= 0), V BE = 0.54 V and V CE = 1.54 V.Remarkably, the simulation results based on Equation (4) shown in Figure2breveal that f T, i remains independent and unaffected by the number of pinholes.Hence, we can conclude that the OPBT operates like multiple parallel transistors formed by a single pinhole.Using these simulation results, we can formulate and develop our understanding and elucidate the underlying physics as follows.The extrinsic transit frequency f T-Ex for an OPBT can be defined as follows, taking into account the impact of external parasitic capacitance:[28]

Figure 2 .
Figure 2. a) The components of external C Par-Ex and internal C Par-In parasitic capacitance and b) the simulated small-signal current gain h 21 versus frequency () for different numbers of pinholes (as indicated in the legend) but fixed density of pinholes D ph = 50 μm −2 at C Par-Ex = 0, V BE = 0.54 V and V CE = 1.54 V.

Figure 3 .
Figure 3.The simulated f T and f max versus a) V BE and b) log I C at V CE = 1.54 V of an OPBT with one single pinhole.

Figure 4 .
Figure 4.The simulated f T versus V BE using the spot frequency method at different V CE biases as indicated in the legend.

Figure 5 .
Figure 5. a) Simulated f T as a function of V BE for different device lengths L D as indicated in the legend.b) Peak f T and f max as a function of L D at V CE = 1.54 V for an OPBT with a single pinhole.The L D represents the device length of a single pinhole and determines the density of pinholes and internal parasitic capacitance.The fabricated OPBT has a device length of L D = 150 nm.
Par-Ex and T OSC in f T and f max The impact of external parasitic capacitance C Par-Ex and OSC thickness T OSC on f T are illustrated in Figure 7.The f T as a

Figure 6 .
Figure 6.a) Simulated f T as a function of V BE for different carrier mobilities in the OSC (see the legend).b) Peak f T and power per unit area P S as a function of mobility at V CE = 1.54 V for an OPBT with a single pinhole and L D = 150 nm.

Figure 7 .
Figure 7.The effect of a) external parasitic capacitance C Par-Ex and b) organic semiconductor thickness T OSC on the simulated T versus V BE of an OPBT with a single pinhole at V CE = 1.54 V.

Figure 8 .
Figure 8.The impact of a) pinhole diameter L Pin and b) contact resistance (Emitter and Collector) R E/C on the simulated f T versus V BE of an OPBT with a single pinhole at V CE = 1.54 V.

Figure 9 .
Figure 9. Simulated fabricated OPBT with a single pinhole and predicted specific parameters (L D = 25 nm, T OSC 10 nm, and μ 0 = 6 cm 2 V −1 s −1 ) for a) current gain h 21 versus frequency () at V BE = 0.54 V, and V CE = 1.54 V. b) f T versus V BE at V CE = 1 V.

Table 1 .
OPBT dimensions and material parameters.