Graphene‐Based Lateral Heterojunctions for 2D Integrated Circuits

A method for patterning single‐layer graphene (SLG) and single‐layer oxidized graphene (SOG) within a continuous atomic layer to form lateral heterojunctions is presented. Raman spectroscopy is employed to investigate the evolution of defect‐related Raman peaks during excimer‐UV irradiation, facilitating the identification of structural changes and defect formation processes. Electrical transport measurements reveal that SOG‐patterned field‐effect transistors (FETs) exhibit varying characteristics depending on the degree of oxidation, thus offering the potential to tailor the electrical properties of graphene devices for specific requirements. Scanning Kelvin probe microscopy measurements reveal the surface potential and work function of the SOG regions compared with those of SLG. The effective functionality of the SOG pattern to operate as a resistor, allowing control of the electrical conductivity in the SOG‐patterned SLG channels, is demonstrated. This capability restricts the current flow while preserving the pristine electrical properties of the graphene channel. Moreover, the SOG pattern can serve as a potential barrier to constructing SLG‐SOG‐patterned integrated circuits, providing exciting opportunities for engineering advanced electronic components. This breakthrough in graphene devices simplifies the fabrication process of graphene‐based FETs and provides the foundation for developing atomically thin integrated circuits for a wide range of applications.


Introduction
Graphene, a 2D layer of carbon atoms, possesses exceptional electrical, thermal, and mechanical properties, making it a promising material for a wide range of electronic applications. [1]However, its inherent semi-metallic nature limits its versatility, [2][3][4][5] preventing the simultaneous creation of both conductive and insulating components within a single device, thus making it imperative to enable precise control over its electrical conductivity to fully exploit its potential.Lateral heterojunctions formed within atomically layered 2D materials present an exciting avenue for advancing integrated circuit technology [6][7][8][9] as they allow for developing devices with distinct electronic properties within a single 2D layer, potentially leading to improved functionality.[12][13][14] There is also a need for scalable synthetic methods to prepare 2D materials with tunable properties, structures, and functions for industrial applications of lateral heterostructures. [15]his study introduces a controlled method for creating lateral junctions between single-layer graphene (SLG) and single-layer oxidized graphene (SOG).SOG synthesis involves the oxidation of as-prepared SLG using excimer UV-irradiation under ambient conditions.Unlike heterojunctions involving graphene and other 2D materials (e.g., graphene-TMDs), [16] SLG-SOG junctions do not require pre-patterning or regrowth processes, avoiding edge imperfections and contaminations.These heterojunctions are particularly intriguing because the SOG shares the SLG structure with continuity, ensuring perfect edge alignment between the two materials.[18] Our previous work has demonstrated the utility of SOG for doping SLG in vertically stacked heterostructures. [19]ere, we present a lateral heterojunction involving SLG and SOG patterns within an atomic layer sheet.In field effect transistors (FETs), a homogeneous SOG sheet exhibits a resistance difference of more than two orders of magnitude compared to the SLG, establishing a lateral heterojunction that can be used to limit the current flow through the SLG channel.Also, scanning Kelvin probe microscopy demonstrated that the SOG pattern can effectively function as a locally formed potential barrier.These findings represent a significant advancement in the development of atomically thin integrated circuits, offering potential applications.

Fabrication Process of Field Effect Transistors
We fabricated two distinct types of graphene-based FET devices, as shown in Figure 1, to investigate the controlled formation of lateral junctions between SLG and SOG.The fabrication of graphene FETs typically involves electron-beam lithography (EBL).In this process, conventional O 2 -plasma etching is used to define the FET channel and create confined structures. [21]owever, the effectiveness of this approach in producing welldefined edge states within graphene FETs remains debatable.High plasma energy does not guarantee the formation of clean edge states in an atomic layer of graphene; instead, it can introduce issues such as charging effects, generation of carbon vacancies, and formation of impurities at dangling sites. [21]These edge states can significantly affect the electrical transport properties of graphene FETs, and their importance becomes more pronounced as the FET channel size decreases, [22] thus highlighting the need for a reliable confinement method capable of defining the graphene channel while simultaneously providing clear and well-defined edge states.Moreover, this confinement approach should be compatible with conventional EBL processes.
For the proposed SLG FET, the fabrication process involved the application of a conventional EBL to create the desired graphene FET device.This process typically includes two O 2 -plasma etching steps: isolate the channel and define the intricate structure within the device.In contrast, a different approach is employed for fabricating SOG-patterned FETs, wherein excimer-UV oxidation is utilized to define the intricate structure within the isolated graphene channel.The key distinction between these two methodologies is the modification of the edge states.In the preparation of SOG-patterned FETs, the edge states are modified through the excimer-UV oxidation, whereas for SLG FETs, edge states are eliminated via the O 2 -plasma etching.The devices were designed for use in a six-channel transfer-length-method (TLM) measurements, with each channel length ranging between 5-30 μm, incremented at 5 μm intervals.For reference, two conventional SLG FETs were prepared using O 2 -plasma etching, with channel widths of 5 and 15 μm.In the initial phase of channel definition, all FET devices were configured with a uniform width of 15 μm, using O 2 -plasma etching to isolate the channel area.To create SOG-patterned FET devices, a 5-μm section at the center of the device was covered by a polymethyl methacrylate (PMMA) layer as an electron-beam resistor (ER).Subsequently, the sample was subjected to excimer-UV irradiation with varying irradiation times (t UV ) to create an SOG-SLG-SOG lateral heterostructure.(A more detailed fabrication process can be found in, Figure S1, Supporting Information)

Raman Analysis of Excimer-UV-Irradiated SLG and SOG-Patterned Channels
Raman spectroscopy was employed to investigate the physicochemical changes occurring on the surface of SLG during excimer-UV irradiation.As shown in Figure 2a, the as-fabricated graphene channel (t UV = 0s) exhibits distinct G and 2D peaks at ≈1586 and ≈2675 cm −1 , respectively, confirming its singlelayer nature. [23]Additionally, a small D peak at ≈1350 cm −1 , commonly associated with grain boundaries or point defects, is observed in the initial state. [24]During excimer-UV irradiation, the D peak significantly increases, accompanied by the emergence of additional features, including a minor D' peak at ≈1620 cm −1 and a (D+D') peak at ≈2950 cm −1 .These new peaks represent defect-related Raman features, specifically D, D', and (D+D'), directly related to the species and concentration of defects. [25]hus, the changes in the Raman peak intensities provide insight into the structural alterations and defect formation processes in SLG under excimer-UV irradiation.The Raman peaks of SLG evolve rapidly when excimer-UV irradiation is applied to fully ER-uncovered SLG devices.After 50 s of t UV , the SLG Raman spectrum transforms into that of a homogeneous SOG layer, indicating the complete oxidation of the SLG.At t UV > 60 s, the Raman spectrum corresponds to a highly defective graphene lattice, and at t UV = 120 s, the graphene layer is eliminated.The changes in Raman peak intensities are shown in the second panel of Figure 2a.I D increases rapidly with t UV until it reaches its maximum value at t UV = 50 s, attributed to the adsorption of the epoxy groups on the graphene sheet. [26]Subsequently, I D decreases sharply and disappears, owing to the carbon vacancy proliferation and sequential etching processes.In the third panel of Figure 2a, the normalized Raman intensities of the other peaks are shown after dividing by I G .The I D /I G increases from 0.3 (at t UV = 0 s; pristine SLG) to a maximum of 3 (at t UV = 50 s), further confirming the homogeneous SOG condition.
Figure 2b shows the evolution of the Raman spectra as t UV increases in the partially ER-uncovered region of the SOGpatterned FETs.The polymer-based ER layer effectively protects the underlying SLG region from oxidation and allows continued chemical reactions to occur on the remaining ER surface.Consequently, the rate of increase of I D in the ER-uncovered SLG regions of the SOG-patterned devices decreases compared to that in Figure 2a, saturating with increasing t UV rather than declining abruptly after reaching the maximum intensity value.Additionally, I G remains almost constant throughout the excimer-UV irradiation time, further confirming the homogeneous SOG condition with graphene lattice preservation, thus suggesting the occurrence of self-limiting oxidation in patterned devices with minimized lattice-defect formation (Figure S2, Supporting Information).The UV light is absorbed by the ER film because the UV energy (7.2 eV) is significantly higher than the C─C (3.6 eV) and C─H (3.4 eV) bonding energies of the ER (PMMA A6 in this experiment). [27]Moreover, the ER exhibits a high absorption coefficient for short-wavelength UV light (<300 nm), allowing the use of excimer-UV energy for polymer chain scission.Consequently, unlike the previous results shown in Figure 2a, the violent photochemical reaction caused by the direct excimer-UV lamp irradiation of SLG is suppressed, and homogeneous SOG is formed and maintained.As the excimer-UV irradiation continues, the ER pattern decomposes and becomes thinner (Figure S3, Supporting Information).In contrast, all Raman peaks of the ER-covered region in the SOG-patterned devices remain almost unchanged even after extended UV irradiation, as shown in Figure 2c.

Electrical Transport Characteristics of SLG-Only and SOG-Patterned Channels
Figure 3a presents a comparison of the two types of FET devices prepared.The top panels correspond to devices comprising only an SLG channel (width = 5 μm), while the bottom panels correspond to devices comprising an SOG-patterned channel (width = 5-5-5 μm corresponding to an SOG-SLG-SOG structure).Notably, optical microscopy cannot differentiate the SLG and SOG regions in the patterned device because of the absence of significant differences in their optical transmittances (Figures S4 and S5a, Supporting Information).Furthermore, the Raman mapping image reveals that the SOG region-oxidized via excimer-UV exposure-maintains the same G-peak intensity as SLG because only epoxy groups are adsorbed onto the preserved graphene lattice.However, the Dpeak intensity mapping image reveals distinct differences between the SLG and SOG regions owing to the high sensitivity of the D band of graphene to structural disorders induced by oxidation.These results highlight the effective protection of the graphene region by the ER coating film and the simultaneous uniform formation of SOG during excimer-UV irradiation in the general EBL process (Figure S4, Supporting Information provides more detailed information on the changes in optical microscopy and Raman mapping images).The rightmost panel of Figure 3a presents a schematic illustrating the edges of the SLG channel etched by O 2 plasma, with the SLG channel confined by the SOG patterns.The edge of the O 2 -plasma-cleaved SLG channel creates dangling bonds that serve as adsorption sites for multiple functional groups, including hydroxyl, carbonyl, and carboxyl. [28]Conversely, oxidation induced by the excimer-UV irradiation serves as a bar-rier, confining the carrier current within the graphene channelachieved without disrupting the continuous graphene structure formed by the adsorption of epoxy groups onto the graphene surface.Figure 3b presents a comparison of the gate-sweep-dependent electrical transport characteristics of the SOG-patterned devices and the reference SLG FETs.Notably, all SOG-patterned channels had a total width of 15 μm, consisting of 1/3 of SLG and 2/3 of SOG.The reference FETs, with widths of 15 and 5 μm for the SLG-only devices, exhibit decreases in current levels from ≈0.36 to ≈0.13 μA at the charge-neutral point (CNP) with V DS = 1 mV, while their resistances at the CNP remain at ≈8275 and ≈8010 Ω, respectively.Furthermore, the electrical mobilities of the 15-and 5-μm-wide SLG-only devices are 1600 and 1620 cm 2 Vs −1 , respectively.Interestingly, the current levels at the CNPs of the SOG-patterned devices vary gradually from the 15-to the 5-μm-wide SLG-only FETs, depending on the degree of oxidation.The current levels and mobilities of the SOG-patterned devices with homogeneous SOG regions for t UV > 80 s are compa-rable to those of the 5-μm-wide SLG-only FET devices, attributed to a marked increase in the resistance (more than two orders of magnitude between the SLG and homogeneous SOG) of the oxidized region with increasing t UV (Figure S5, Supporting Information).More details on the t UV -dependent electrical property changes of the SOG-patterned devices, such as the carrier density, resistance, and mobility, are shown in Figure S6 (Supporting Information).

Surface Potentials of SLG and SOG-Patterned Channels
We conducted scanning Kelvin probe microscopy (SKPM) measurements to confirm the effectiveness of SOG-patterning for various electronic applications.SKPM, a noncontact mode of atomic force microscopy, allows the measurement of the local contact potential difference (CPD) between a metallic tip and the sample surface.The CPD is related to the surface potential variation (V CPD ) of the sample through the equation V CPD = (Φ tip − Φ sample ) / (−q), with q representing the elementary charge. [29]igure 4a presents the evolution of the surface potentials of the SLG, SOG, and SiO 2 substrates within the SOG-patterned channels.Notably, all surface potential values for the SLG were used as references and aligned to 0 mV.Although Au electrodes (having a work function of ≈5.1 eV) are commonly used as references in SKPM, [30] excimer-UV exposure affects the surface potential of Au. [31] Therefore, Au pads in the SLG-only sample were used to calibrate the SKPM tip and determine the surface potential of SLG.Since the SLG region is the only area unaffected by excimer UV irradiation, we used SLG as a reference point for calculating the potential differences for other excimer UV-irradiated samples.For t UV ≤ 40 s, a slight difference in ΔV CPD between the SLG and SOG is noticeable compared to the line profile of the 15-μmwide SLG-only sample.However, for t UV > 40 s, ΔV CPD between the SLG and SOG experiences an abrupt increase, which then remains constant.Remarkably, for t UV > 50 s, the surface potential of the SiO 2 substrate is significantly increased, attributed to the formation of charged entities, including (≡Si─OH), (≡Si─O)─, and (O 3 ≡Si (+)), on the UV-exposed Au and SiO 2 surfaces. [32]igure 4b presents the work function (Φ) within the SLG, SOG, and SiO 2 regions as a function of t UV .We used SLG as a reference and calculated the work function of SLG (Φ SLG ) using the formula Φ SLG = Φ Au-electrode (5.1 eV) − eΔV CPD , based on measurements taken from the SLG-only sample.Subsequently, we assessed the work function values of the SOG and SiO 2 in the SOG-patterned devices using Φ SLG (4.948 eV) as the reference value.As confirmed by Raman analysis, the protective ER layer ensures consistent stability of the SLG throughout the entire excimer-UV irradiation process.In contrast, the work function of the SiO 2 substrate is discernibly reduced, persisting until t UV = 120 s, resulting in an inversion of the work function order between the SOG and SiO 2 .Nevertheless, this transition in the work function does not affect the electrical current within the SLG channel of the SOG-patterned device, as shown in Figure 3b. Figure 4c presents three SKPM images that exhibit the distinct features described earlier and shown in Figure 4a,b.Although the decreasing trend in work function difference between SOG and SiO 2 surfaces does not affect the electrical properties in a single FET device, when considering patterned array devices, t UV may need to be limited to within a certain time to prevent interference between constituent elements.
These results highlight the potential for controlling and manipulating the electrical characteristics of graphene devices using excimer-UV-patterned potential barriers.This approach simplifies the fabrication process of conventional graphene FETs and offers an efficient technique for defining graphene channels without material-design constraints.In addition, excimer-UV oxidation can complement conventional O 2 -plasma etching in 2Ddevice fabrication, providing more precise control over the electrical properties of graphene devices via SOG patterning.

Conclusion
In this paper, we introduced an innovative fabrication strategy for manufacturing lateral junctions between SLG and SOG in FET devices.This method combines excimer-UV oxidation with conventional O 2 -plasma etching, enabling effective currentcontrolled patterning within FET channels.Raman spectroscopy results demonstrate the dependence of the oxidation process on t UV and the surface environment of graphene channels.For uncovered graphene surfaces, a uniform SOG is produced within 60 s of t UV , leading to full graphene layer etching at t UV = 120 s.Meanwhile, for patterned graphene surfaces with partially ERcovering, the oxidation process results in the formation of a homogeneous SOG in uncovered regions, with a self-limiting oxidation process preventing the etching of the graphene layer.We also emphasize the effectiveness of a protective ER layer in protecting SLG from oxidation during excimer-UV irradiation.This protective layer ensures the optical and electrical properties of the SLG channels without any observed degradation or mobility loss.The ER layer also plays a crucial role in the self-limiting oxidation process in SOG-patterned devices, facilitating a uniform saturation of oxidation and forming a homogeneous SOG sheet.FET measurements confirm the tunability of electrical properties in SOG-patterned devices by adjusting t UV .The resistance of SOG regions increased by two orders of magnitude compared to SLG regions, effectively limiting the current flow to the SLG channels.SKPM results also confirm the formation of a potential barrier in oxidized regions by increasing work function of SOGs as t UV increases.Hence, this facile and scalable approach holds great promise for the large-scale fabrication of intricate lateral and vertical heterostructures with tunable properties for graphene-based 2D integrated circuits.

Experimental Section
SLG Preparation: SLG was synthesized via chemical vapor deposition using Cu foil as the catalyst.Subsequently, the prepared SLG was transferred onto a SiO 2 /Si substrate using a wet transfer method.During the transfer process, a supportive PMMA layer was coated onto the SLG, with a copper etchant solution of ammonium persulfate (APS) employed for Cu-foil etching.After etching the Cu foil, the SLG sheets were rinsed multiple times with DI water before being transferred onto thermally oxidized SiO 2 (300 nm)/Si substrates.Finally, the supporting PMMA layer was removed using acetone and isopropyl alcohol.
SOG Preparation: SOG was produced by Xe 2 excimer-UV irradiation (wavelength = 172 nm) at an illumination power density of 18 mW cm −2 under ambient conditions, with variations in the duration on SLGtransferred SiO 2 substrates.
Device Fabrication: FET devices were fabricated on SLG, SOG, and SOG-SLG-SOG channels, as defined by electron-beam lithography and O 2 -plasma etching.The detailed fabrication process is shown in Figure S1 (Supporting Information).
Raman Spectroscopy: Raman spectra were acquired using a confocal spectrometer (alpha300 R, Witec) with a 532-nm wavelength laser.A 100x objective was used, which provided a laser spot size of ≈2 μm.A laser power of <1 mW was employed to prevent alterations in the chemisorption of unintended functional groups or the induction of structural defects in graphene.The fitting of Raman spectra was achieved using a combination of Gaussian and Lorentzian peaks (Voigt function).
Electrical Property Measurements: The I-V characteristics of the FET devices were investigated using a vacuum-probe station and a Keithley 4200-SCS parameter analyzer under low-vacuum conditions of ≈10 −4 Torr.
SKPM: SKPM measurements were conducted using an NX10 instrument from Park Systems.A cantilever (NCSTAu) with a force constant of k = 7.4 N m −1 and a resonant frequency of ≈160 Hz was employed for the scanning.

Figure 1 .
Figure 1.Schematic diagram illustrating the fabrication process of graphene-based field-effect transistors using conventional O 2 -plasma etching and excimer-UV oxidation for SOG patterning.

Figure 2 .
Figure 2. Raman analysis of SLG and SOG as a function of t UV .Excimer-UV irradiation on fully ER-uncovered SLG devices a), partially ER-uncovered SLGs b), and ER-pattern-covered SLGs c) in SOG-patterned FET devices.(a), (b), and (c) correspond to regions (i), (ii), and (iii) indicated in Figure 1.Partially ER-uncovered and ER-pattern-covered SLGs designate the ER-removed and ER-remained patterns after development in the EBL process, respectively.Intensities of the D, G, D', and 2D peaks are denoted as I D , I G , I D' , and I 2D , respectively.Blue and red background colors correspond to the SLG and SOG regimes, respectively.All Raman spectra were analyzed after fitting using a combination of Gaussian and Lorentzian peaks (Voigt function).

Figure 3 .
Figure 3. Electrical transport characteristics of SOG-patterned FETs compared to SLG FETs.a) Left panels show schematics of an SLG-only channel (top) and an SOG-patterned channel (bottom) in the FET devices.Blue and red dots represent carbon and oxygen atoms, respectively.Blue and red background colors correspond to SLG and SOG areas, respectively.The second panels from the left display optical microscopy (O.M.) images of the channels of the as-fabricated devices.The third and fourth panels show Raman G-and D-peak mapping images corresponding to the square dashed areas in the second panel.The last panel schematically illustrates the edges and surface areas of the channels in SLG and SOG in the respective devices.b) Drain-source current (I DS ) as a function of gate voltage (ranging from −20 to +80 V) of SOG-patterned devices compared to two reference SLG FETs with widths of 15 and 5 μm.Each device comprises six channels with varying lengths (5-30 μm).

Figure 4 .
Figure 4. Surface potential and work function analysis of SOG-patterned FETs as a function of t UV using scanning Kelvin probe microscopy (SKPM).a) Line profiles of surface potential across the SOG-SLG-SOG width direction compared to SLG-only channels.Blue and red background colors indicate SLG and SOG areas, respectively.b) Work function (Φ) as a function of t UV calculated from the SKPM surface potential for the surfaces of SLG and SOG channels and SiO 2 substrates in the SOG-patterned devices.c) SKPM surface potential results for t UV of 40, 50, and 120 s.