Bidirectional Synaptic Operations of Triple‐Gated Silicon Nanosheet Transistors with Reconfigurable Memory Characteristics

In this study, a triple‐gated transistor with a p+‐i‐n+ silicon nanosheet (NS) is proposed as a single synaptic device, and bidirectional synaptic functions are realized using reconfigurable memory characteristics. The triple‐gated NS transistor features steep switching and bistable characteristics with a subthreshold swing below 5 mV dec−1 and an ON/OFF current ratio of ≈5 × 106 for both the n‐ and p‐channel modes. This transistor exhibits electrically symmetric reconfigurable memory characteristics with an ON current ratio of 1.02 for the n‐ and p‐channel modes. Moreover, the bidirectional synaptic weight updates of binarized spike‐timing‐dependent plasticity learning are successfully performed in a single transistor. This study demonstrates the potential of a triple‐gated NS transistor for achieving compact synaptic arrays in large‐scale silicon‐based neuromorphic computing systems.


Introduction
[8] In SNNs, spike-timing-dependent plasticity (STDP) learning originally mimicked that of biological synapses, where the synaptic weight update depends on the time DOI: 10.1002/aelm.202300764difference between the presynaptic and the postsynaptic spike events.10] For the efficient implementation of these backpropagation learning algorithms with the bidirectional synaptic functions, transposable memory operations are essential for synaptic devices.[19] Moreover, in SRAM-based SNNs, STDP can be implemented using stochastic learning rules with binarized synaptic weights. [15,20]However, transposable SRAMs require at least six transistors per synaptic cell.This results in a complicated cell structure as well as area inefficiency of neuromorphic computing systems.Therefore, for a high-level integrated silicon-based neuromorphic computing system, bidirectional synaptic functions must be implemented on a single device.
28][29] Hence, in this study, a triple-gated transistor with a p + -i-n + silicon nanosheet (NS) is proposed as a single synaptic device, and bidirectional synaptic functions are implemented in a single transistor.The triple-gated NS transistor can reconfigure the channel mode via electrostatic doping, exhibiting steep switching and bistable characteristics in both the n-and p-channel modes owing to its PF loop.Bidirectional synaptic functions can be realized in a single transistor using reconfigurable memory characteristics.Hence, our triple-gated NS transistor can be utilized as a compact synaptic device that embodies the backpropagation operations in the array with functional scaling.

Results and Discussion
The optical and transmission electron microscopy (TEM) images of a triple-gated NS transistor are shown in Figure 1a, where three polysilicon gate electrodes are arranged side-by-side on the intrinsic channel region of the p + -i-n + silicon NS layer; one control gate (CG) electrode is located between two program gate (PG) electrodes.As shown in the cross-section TEM image of the gate stacks, the Ω-shaped 400-nm thick poly-silicon gate electrode and 25-nm thick SiO 2 gate oxide layer surround the intrinsic channel region of the NS layer on the buried oxide layer that enhances the gate controllability and effective electrostatic doping.The width and height of the NS layer are 180 and 80 nm, respectively.The schematic and energy band diagram of the transistor are shown in Figure 1b.Two PG electrodes are connected to each other.The PG voltage (V PG ) reconfigures the channel mode of the transistor through electrostatic doping in the intrinsic channel region.The CG voltage (V CG ) controls the carrier injection into the intrinsic channel region by modulating the potential barrier heights.Electrostatic doping and barrier-height modulation in the intrinsic channel by V PG and V CG are essential for the PF loop, and the operating mechanism allows the transistor to have steep switching and bistable characteristics.
In the drain-source current (I DS ) versus voltage (V DS ) characteristics of a triple-gated NS transistor (Figure 2a), for V CG = 3 V (−3 V) and V PG = −3 V (3 V), I DS abruptly increases at V DS = 2.5 V (3.5 V) and decreases at V DS = 0.9 V (1.1 V).Latch-up (latchdown) is attributed to the generation (elimination) of the PF loop.The overlapped memory window (that is, V DS ranging from 1.1 to 2.5 V) is the operation range of V DS for the reconfigurable memory operation.The V DS differences of 1.0 V in the latch-up and of 0.2 V in the latch-down originate from the different electrostatic doping by the different gate voltages and the corresponding energy band structure.The operation principles of the transistor are illustrated in Figure 2b with schematics and energy band dia-grams.The n*(p*) region is an electrostatically n(p)-doped region of the intrinsic channel at a gate voltage of 3 V (−3 V).For V CG = 3 V and V PG = −3 V, the band structure of the p + -i-n + layer is changed to p + -p*-n*-p*-n + , in which the PF loop is generated in the n*-p* region beneath the CG and right-side PG electrodes as V DS increases.In the opposite case (V CG = −3 V and V PG = 3 V), the energy band structure is p + -n*-p*-n*-n + ; the PF loop is generated in the n*-p* region beneath the left-side PG and CG electrodes as V DS increases.Thus, the triple-gated NS transistor reconfigures both the channel mode and the channel region where the PF loop is generated.Furthermore, the symmetric V CG and V PG have similar height of the potential barriers in the intrinsic channel through electrostatic doping, which enables the triple-gated NS transistor to perform the bidirectional synaptic operations itself with the highly overlapped memory window.The operation principles with the energy band diagrams of the triple-gated NS transistor in Figure 2b are analyzed in details using a commercial technology-aided design (TCAD) simulator (Synopsys, Sentaurus version O_2018.06)(Figure S1, Supporting information). [30]igure 3a,b shows the I DS -V CG characteristics of the triplegated NS transistor in the n-and p-channel modes, respectively.The corresponding schematics and band diagrams of the transistor for the n-and p-channel modes are depicted in Figure 3c,d, respectively.For the n-channel mode (Figure 3a,c), the intrinsic channel region initially has the n*-p*-n* band structure owing to the electrostatic doping by V PG = 3 V and V CG = −3 V.As V CG sweeps toward the positive voltage region, the potential barrier in the p* region decreases, and electrons are injected from the n + source and accumulated in the n* region near the p + drain region.Thereafter, the PF loop is generated in the n*-p* region beneath the left-side PG and CG electrodes, and the transistor is rapidly turned on at V CG = 0.25 V with an extremely low SS below 5 mV dec −1 .Once the PF loop is generated, despite the reverse sweep of V CG , I DS flows owing to the excess charge carriers In the n-channel mode (V PG = 3 V), during the Write 1 (W1) operation, the excess charge carrier injections and the generation of the PF loop are induced at V DS = 2.4 V and V CG = 3 V; the transistor is in State 1 (Figure 4a).After the W1 operation, applying V DS = 1.2 V maintains the carrier injections and the PF loop during the Hold 1 (H1) operation; the hold current magnitude is ≈3 μA (Figure 2a).Under the Read condition (V DS = 2.4 V and V CG = −3 V), the I DS magnitude is ≈80 μA.A Write 0 (W0) operation is performed at V DS = 0 V and V CG = 3 V, where the accumulated charge carriers in the potential wells are removed.Thus, the PF loop is eliminated, and the transistor is in State 0. During the Hold 0 (H0) operation, the absence of excess charge carriers in the potential wells increases the potential barrier; thus, the charge carriers cannot flow into the channel region.Hence, the I DS magnitude is relatively low under the Read condition, indicating that the transistor is in State 0. The applied V DS for each memory operation in the p-channel mode is the same as that in the n-channel mode; however, the polarities of V PG and V CG are opposite to those in the n-channel mode (Figure 4b), and the absolute V PG and V CG magnitudes are the same for these modes.However, the memory operation mechanisms and timing diagrams of the I DS for the p-channel mode are equivalent to those for the n-channel mode.Consequently, the symmetry of V CG and V PG for the memory operations in the n-and p-channel modes (that is, 3 and −3 V) enables to embody the transposable memory operations.Furthermore, the triple-gated NS transistor in the n-and p-channel modes has a long retention time of ≈1000 s owing to the PF loop mechanism for both State 1 and 0. Also, our transistor maintains State 1 and 0 after 10 6 cycles (see Figure S3, Supporting Information).Considering these criteria, our triple-gated NS transistor can be considered a reliable memory device.
The binarized STDP curve and voltage pulse schemes for the STDP learning rule are shown in Figure 5a,b, respectively, to describe the synaptic weight update of the triple-gated NS transistor.In the binarized STDP curve (Figure 5a), the binarized synaptic weight is decreased (increased) by long-term depression (LTD) (long-term potentiation (LTP)), depending on whether a postsynaptic spike precedes a presynaptic spike.The synaptic weight is updated only when the time difference is shorter than the time window (t w ).Typically, the t w width is 10 ms in biological synapses. [31,32]For a transistor, t w can be controlled by varying the pulse width.In this study, a pulse width of 100 μs is chosen as an instance.The binarized STDP learning curve is further investigated with the change in the conductance of the triple-gated NS transistor for consecutive LTP and LTD pulses (Figure S4, Supporting Information).In Figure 5b, the presynaptic spike (V pre ) is the gate voltage pulse shaping from −3 to 3 V to −3 V with a pulse width of 100 μs, and the postsynaptic spike (V post ) is the gate voltage pulse shaping from 3 to −3 V to 3 V with a pulse width of 100 μs; the V DS pulse is applied at the same time when the presynaptic spike is triggered.V post and V pre are applied to the CG and PG electrodes, respectively, and vice versa.The synaptic weight updates can occur only when the V pre and V post are equally applied at 3 V or −3 V (that is, the Write conditions in Figure 4).When the V post pulse precedes the V pre pulse, the LTD operation is performed, in which V post = 3 V and V pre = 3 V are applied with V DS = 0 V (red region).When the V pre pulse is applied before the V post pulse, the LTP operation is performed, in which V post = −3 V and V pre = −3 V are applied with V DS = 2.4 V (blue region).The applied voltages for LTD and LTP are similar to those of the W0 and W1 operations shown in Figure 4, respectively.Before and after the synaptic weight updates, the transistor maintains the synaptic weight with the applied voltages (V DS = 1.2 V, V pre = −3 V, and V post = 3 V); the operating voltage conditions are similar to those of the Hold operations shown in Figure 4.
Figure 6 shows the transposable synaptic weight update of the triple-gated NS transistor following the binarized STDP.First, the presynaptic spike triggers a V CG pulse, whereas the postsynaptic spike triggers a V PG pulse.When the V PG pulse pre-cedes the V CG pulse, the LTP operation is performed, in which both V CG and V PG are applied at −3 V with V DS = 2.4 V; the applied voltages are similar to those of W1 operation in the pchannel mode.Thus, the transistor is in State 1, and the I DS magnitude is ≈80 μA.After the LTP operation, the transistor maintains the synaptic weight during the hold operation.Thereafter, for the Read operation, the I DS magnitude is ≈80 μA.When the V CG pulse precedes the V PG pulse, LTD is performed, in which both V CG and V PG are applied at 3 V with V DS = 0 V; the applied voltages are similar to those of the W0 operation in the n-channel mode.Hence, the transistor is in State 0, and the I DS magnitude is relatively low.Subsequently, the transistor transposes the synaptic spikes, and the V CG and V PG pulses are triggered by the presynaptic and postsynaptic spikes, respectively.As before, the LTP and LTD operations are successfully performed according to the STDP learning rule, as shown in Figure 5b.
We demonstrate, for the first time, the bidirectional synaptic functionality in a single device by utilizing the reconfigurable memory characteristics of a triple-gated NS transistor.Although a single transistor performs binarized STDP operations owing to its bistable characteristics, multilevel synapses can be implemented by composing a single synaptic cell of several triplegated NS transistors. [11,21]Furthermore, the proposed triple-gated NS transistors can provide compact synaptic arrays for siliconbased SNNs compared to conventional transposable SRAMs because they enable transposable synaptic functions in a single device. [15,20]

Conclusion
In this study, we proposed a triple-gated transistor with a p + -i-n + silicon NS as a single synaptic device and demonstrated its bidirectional synaptic operation.The transistor exhibited steep switching and bistable characteristics in both the n-and p-channel modes owing to the PF loop mechanism.Moreover, the transistor reconfigured both the channel modes and the channel region where the PF loop was generated.This unique reconfiguration mechanism enabled transposable memory operation with binarized STDP in a single transistor.This transistor has significant potential for use in bidirectional synaptic devices for large-scale neuromorphic computing systems.

Experimental
Device Fabrication: The triple-gated NS transistors were fabricated using full CMOS processes from a p-type (100)-oriented SOI wafer with a 100 nm thick top silicon active layer (with a doping concentration of ≈10 16 cm −3 ) and a 2-μm thick buried oxide layer.First, an NS layer with a width of 180 nm and height of 80 nm was formed via photolithography and dry etching.And then three poly-silicon gate electrodes (400 nm thick and 2 μm wide) were formed with each 1 μm gap by low-pressure chemical vapor deposition (LPCVD) on a 25-nm thick SiO 2 gate oxide layer that was thermally grown on the intrinsic channel region at 850 °C.The p + drain and CG regions were heavily doped with BF + 2 ions at a dose of 3 × 10 15 cm −2 and at an ion energy of 30 keV.The n+ source and PG regions were heavily doped with P + ions at a dose of 3 × 10 15 cm −2 and at an ion energy of 50 keV.Rapid thermal annealing was then performed at 1050 °C for 30 s to activate the implanted dopants.Finally, a Ti/TiN/Al/TiN metal alloy was deposited in the drain, source, and gate contact regions after interlayer dielectric deposition using LPCVD-based tetraethyl orthosilicate, followed by an alloying process at 400 °C for 30 min.
Measurement: All electrical data were measured using a semiconductor parameter analyzer (HP4155C, Agilent), a Tektronix AFG 31102 and an AFG 3101C arbitrary function generator, and a Tektronix MDO3054 mixeddomain oscilloscope at 20 °C.The morphology was observed using TEM (JEOL JEM-2100F, FEG).

Figure 1 .
Figure 1.a) Optical and TEM images of a triple-gated transistor with a p + -i-n + NS. b) Device schematics and energy band diagram.

Figure 2 .
Figure 2. a) I DS versus V DS characteristics of the triple-gated NS transistor and b) operation principles with schematics and energy band diagrams.

Figure 3 .
Figure 3.I DS -V CG characteristics, schematics, and energy band diagrams of the triple-gated NS transistor in the (a,c) n-channel and (b,d) p-channel modes.

Figure 4 .
Figure 4. Memory operations of the triple-gated NS transistor in the a) nand b) p-channel modes.

Figure 5 .
Figure 5. a) Binarized STDP curve and b) voltage pulse schemes for the STDP learning rule.

Figure 6 .
Figure 6.Transposable synaptic weight update operations of the triple-gated NS transistor.