Transferrable Alumina Membranes as High‐Performance Dielectric for Flexible 2D Materials Devices

2D materials have shown great promise for novel electronic functionality. A common challenge for 2D materials‐based transistors is forming a high‐performance gate terminal due to the challenges of depositing a dielectric of sufficient quality and controllable thickness. Herein the van‐der‐Waals integration of a free‐standing Al2O3 dielectric membrane is demonstrated as a facile, scalable, and powerful gate dielectric. A process is developed that permits the wet transfer of an amorphous alumina layer with a finely adjustable equivalent oxide thickness (EOT) in the single nanometer range. Electrical characterization demonstrates the high breakdown field and low leakage of the dielectric and integration into 2D materials transistors reveals a high performance. The wafer‐scale uniformity of the dielectric membrane permits the formation of large‐scale flexible devices that exhibit good robustness and long‐term stability.


Introduction
With the advancement and miniaturization of microelectronics toward the single-nanometer scale, surface scattering becomes a limiting factor for silicon electronics.2D materials, a group of atomically thin layered crystals, are considered a promising alternative due to their saturated out-of-plane bonds.However, the absence of dangling bonds causes significant problems for the integration of 2D materials into realistic transistors.
For efficient control of charge carrier movement in a transistor, a gate contact is required that resides on a dielectric layer DOI: 10.1002/aelm.202300783   whose thickness has to be in the nanometer range to achieve high gate control.While back-gating through a conductive substrate is a convenient method for research, integration of multiple 2D field effect transistors into a circuit requires the assembly of a gate dielectric on top of the 2D material channel.Unfortunately, conventional direct integration schemes, such as atomic layer deposition and chemical vapor deposition, [1] that are employed in silicon-based electronics, are not compatible with 2D materials.The anisotropic bonding nature of 2D materials imparts them with an inertness to out-of-plane adhesion and conventional dielectrics exhibit quality issues such as pinholes, which decrease the breakdown voltage and increase the gate leakage. [2,3]ignificant effort has been invested in improving the deposition process of gate dielectrics on 2D materials.Several methods, such as plasma-enhanced atomic-layer deposition, deposition of seeding layers, and in situ oxidation of 2D materials regions have been proposed toward enhancing the uniformity and quality of dielectrics on 2D materials. [1]However, the increase in fabrication complexity, issues with materials compatibility, and observed decreases in dielectric performance limit their applicability.
To overcome these issues, recent research has focused on vander-Waals (vdW) dielectrics where dielectrics with inert surfaces are brought in close contact with a 2D semiconductor through vdW forces. [1]The absence of bonding between the materials leads to an enhanced transistor performance compared to previous approaches. [4,5]hile these approaches have demonstrated the potential of vdW dielectrics, several issues prevent their utilization in practical devices.Most studies have focused on single-layer vdW dielectrics, but the low thickness enhances the severity of gate leakage through tunneling.Moreover, the choice of vdW materials that exhibit a layered structure and suitable dielectric properties is limited.Finally, the scalability of vdW dielectric synthesis to wafer size has yet to be demonstrated.
We here demonstrate the potential of nanometer-thin, freestanding alumina membranes as attractive vdW dielectrics.The combination of an innovative transfer process and established atomic layer deposition (ALD) enables the scalable formation of membranes with finely tunable properties and promising electronic performance.Integration of the membranes into 2D materials-based devices demonstrates uniform coverage with high dielectric constant, good breakdown strength, and low leakage even at EOTs in the single nanometer range.Upon integration into 2D FETs, we observe high carrier mobility, low leakage currents, and low doping of the graphene channel.Finally, our approach was applied to producing flexible electronics that exhibit lower complexity, high performance, and good mechanical stability.Our results not only provide a route for the scalable realization of high-performance dielectrics for future 2D electronics but also open up exciting applications as wearable devices and tailored neuromorphics.

Results and Discussion
Atomic layer deposition (ALD) is a key process in conventional semiconductor fabrication due to several unique advantages. [6,7]irst, ALD growth is self-limiting, enabling atomic control of the film thickness.Moreover, ALD coating is highly conformal, [8,9] which is important to obtain pinhole and defect-free ultrathin dielectric films.Finally, the ALD process has demonstrated compatibility with a multitude of precursors, permitting the realization of diverse nanostructure. [10]We focus on the application of aluminum oxide layers due to their suitability for the envisioned application.First, alumina has shown good electrical performance, such as low leakage and high breakdown fields. [11]Moreover, even in its amorphous state, alumina exhibits high mechanical strength. [12]Finally, we have recently demonstrated the ability of alumina to suppress Fermi-level pinning in 2D materials channels and recover their intrinsic response. [13]igure 1a illustrates the steps of our approach toward producing freestanding alumina membranes.In our experiment, we used a silicon wafer (p-type) as the growth substrate.Subsequently, a polyvinyl alcohol (PVA) hydrogel is deposited as a functional layer.For this purpose, 5% PVA solution was spin-coated on Si/SiO 2 .Then the sample was dried on heater at 90 °C for 10 min.
Atomic layer deposition was employed to produce alumina with a predetermined thickness onto the PVA hydrogel.Once the ALD deposition was completed, the sample was spin-coated with a thin PMMA polymer as a supporting layer.Then, the sample was baked at 65 °C for 1 h.
To release the alumina membrane, we soaked the stack in deionized water.Due to the swelling of the PVA hydrogel, the alumina film delaminated within minutes, floating in the water as a freestanding dielectric material (Figure 1b).The alumina membrane can be transferred onto arbitrary substrates using techniques developed for 2D materials.
Ti conduct detailed characterization of the membrane's morphology , we initially deposited it onto a graphene-covered Si substrate.After transferring it was baked at 65 °C for 1 h.The sample was washed with acetone to remove the PMMA support.
Scanning electron microscopy (SEM) was employed to investigate the morphology of the deposited alumina membrane.It can be seen from Figure 2a that the membrane is continuous over large distances which agrees with results from optical microscopy (Figure 2c).Only at the boundary of the membrane, cracks are observed that are due to transfer-induced damage that has been observed for 2D materials, as well (Figure 2c).The discontinuity allows us to establish the thickness of the membrane by atomic force microscopy (Figure 2d).The extracted step height is separated into the contributions from the graphene layer thickness (1 nm) [14] and alumina (14 nm) which is close to the expected thickness after 100 ALD cycles. [15,16]ith the morphology of the membrane established, we turn to characterize its dielectric performance.For this purpose, a capacitor structure was produced that utilizes a graphene bottom electrode and an evaporated gold top electrode (Figure 3a).Force-resolved microprobing [17] was employed to avoid mechanical damage during electrical characterization.
Figure 3a shows the current-voltage characteristics of the capacitor structure under forward and reverse voltage sweeps.It can be seen that capacitive charging dominates the response and the ohmic component is found to be only 0.25% (For details see Figure S1, Supporting Information).This observation indicates the limited leakage current of 3.33 × 10 −12 A cm −2 in the device.Furthermore, the area of the hysteretic curve can be used to calculate the capacitance and the extracted value (10 −10 F) agrees with the expected value for a dielectric with a relative dielectric constant of 11.41.This value matches well with the literature reports [18] and indicates that the equivalent oxide thickness (EOT) of the membrane is 5 nm.
Moreover, the current-voltage characteristic demonstrates the absence of dielectric breakdown even at 50 V.(More details on the breakdown strength are provided in Figure S2, Supporting Information).Thus, the lower bound of the dielectric breakdown field strength is 3GV m −1 , this high performance is thought to originate from the van-der-Waals interface between graphene and the dielectric that decreases the effect of electromigration and produces superior dielectric membranes (see Table 1 for a comparison). [3]This enhancement demonstrates the high quality of the dielectric and the potential for novel electronic devices.

Comparison of Dielectric Quality
We integrate the dielectric membrane into flexible, top-gated graphene field effect transistors (Figure 3b).For this purpose, a graphene layer was transferred onto a PET substrate using a wet transfer process.We limit the effect of photoresist contamination [29] and mechanical delamination [30] by employing shadow masks for the deposition of electrodes and gate contact.
(more details about the fabrication process are provided in the Experimental Section and Figure S3, Supporting Information).
To investigate the effect of this integration process on the 2D material , we characterize the graphene channel by Raman spectroscopy.Figure 3c demonstrates the retention of the Raman G-band and 2D-band features and the absence of the defectinduced D-band.These observations indicate that the structural properties of the graphene are not affected by the integration process and its quality remains high.Closer inspection of the peak position shows an upshift of the G-band which suggests charge transfer from the graphene to alumina. [31]o confirm this hypothesis, we investigate the response of the GFET to gating.Figure 3d shows the transfer characteristics of top-gated GFET at V d = 1 V while the gate voltage was swept from −20 to 20 V (more details of electrical characterization measurements of the device are provided in Figures S4 and   S5, Supporting Information).The charge neutrality point occurs at V indicating the graphene channel is p-type doped.Calculations indicate a p-type doping concentration of 3.7 × 10 12 cm −2 which is lower than the intrinsic doping concentration extracted by Hall-effect measurements (6.29 × 10 12 cm −2 ).This observation confirms that the integration of the alumina membrane decreases the intrinsic doping of graphene.Future work will have to confirm our hypothesis that the observed decreased charge transfer is due to the transfer of oxygen adsorbates from graphene transferring to surface oxygen vacancies in the alumina membrane. [32]The high on-current and high extracted field effect mobility of 5.2 × 10 3 cm 2 Vs −1 demonstrate the potential of our approach for future electronics and are compared to previous work in Table 2.This performance could be further enhanced by increasing the gated area ratio and modifying the contact composition to improve the off-current at the charge neutrality point.

Comparison of Device Performance
In addition to enhancing the performance of current 2D materials transistors, our transferrable dielectric enables novel functionality in electronic devices.To illustrate this ability, we strain the graphene channel by bending of the PET substrate.Contacting of the flexible device during bending deformation was achieved through large external electrodes (Figure 4a). Figure 4b illustrates that the Al 2 O 3 /graphene device consistently retains its ohmic behavior even under large mechanical strain.
The fabricated sample was subjected to uniform uniaxial tensile strain by bending the Al 2 O 3 /graphene-coated PET substrates to a defined radius.[40] Figure 4c represents a typical curve of the relative change in resistance Δ R/R in response to mechanical strain .A clear linear increase in device resistance is observed with increasing mechanical strain.The slope of the resistance-strain curve represents the gauge factor, a crucial metric for electrical strain sensors. [41]The observed gauge factor of 14 is consistent with previous reports on graphenebased sensors, [42] indicating the device's suitability for precise strain measurements.Moreover, reliability tests were carried out to evaluate the long-term stability of the devices involved subjecting the device to 6000 deformation cycles without  detecting any systematic change in resistance (Figure 4d). Figure 4e further confirms the device's consistent and reproducible performance throughout repeated deformations.

Conclusion
In summary, we report on a versatile fabrication method that produces freestanding alumina membranes for van-der-Waals integration with 2D materials.Through delamination from a hydrogel, uniform, and nanometer-thick alumina layers could be produced.The dielectric layer showed good dielectric performance and high breakdown field strengths.An established transfer process permitted the fabrication of graphene field-effect transistors with high mobility and low intrinsic doping.Our results open up new routes to high-performance flexible devices with good mechanical robustness.

Experimental Section
ALD Growth of Al 2 O 3 : For the deposition of Al 2 O 3 , trimethylaluminum (TMA) was employed as the precursor with H 2 O reactant as the oxidant.Each cycle consists of the TMA exposure of 0.1s, water vapor exposure of 1s, and continuous Ar purging in sequence at the room temperature. [43]Total of 100 cycles was performed.
Fabrication of Top-Gate Graphene FET on Flexible PET Substrate: For top-gate GFET devices, graphene was synthesized using a low pressure chemical vapor deposition method as reported previously . [44]Briefly, copper foil (JX corp., 99.9% purity, 35 μm thickness) was inserted into a 25 mm quartz tube and heated in a clamshell furnace underflow of 10 sccm H 2 to 1020 °C.Graphene growth was initiated by introducing 10 sccm of CH 4 and stopped after 6 h before cooling the sample to room temperature.
The LPCVD-grown graphene was transferred to the PET substrate by using a wet transfer method.First, a layer of PMMA was spin-coated over graphene on copper foil.Then the PMMA/graphene/Copper foil was immersed into a copper etchant (FeCl 3 ) solution to etch away the graphene.The PMMA/graphene layer was transferred from the etchant solution to DI water to remove any remaining etchant residue.The PMMA/graphene was then transferred to PET substrate and dried in a hotplate at 65 ˚C temperature for 1 h followed by removal of PMMA using hot acetone and Isopropyl alcohol leaving a graphene layer on the PET substrate. [45]he fabrication of top-gate GFET on PET substrate used three steps.a) Source and drain electrode were deposited onto the graphene using a shadow mask.A 5 nm layer of chromium (Cr) followed by a 30 nm layer of gold (Au) was deposited.The lift-off process was used to define the electrode pattern.b) An Al 2 O 3 dielectric layer, grown using atomic layer deposition (ALD), was transferred onto the graphene using the PMMA transfer method as shown in Figure 1a,c.Finally, the top gate electrode was deposited over the Al 2 O 3 dielectric layer using a shadow mask.This involved deposition of 5 nm Cr and 30 nm Au followed by lift-off process (more details about the fabrication process are provided in Figure S3, Supporting Information).
Material Characterization: Atomic force microscopy (AFM) was conducted on a Nanosurf FlexAFM to measure the thickness of Al 2 O 3 film deposited with Atomic Layer Deposition (ALD).Scanning Electron Microscopy (SEM) on a Phenom ProX was used to study the uniform, continuous, and high quality of the Al 2 O 3 film over graphene.Raman spectroscopy was conducted in a home-built Micro-Raman system with an excitation energy of 532 nm.Raman suggested that the quality of graphene remains high even after transfer of ALD-Al 2 O 3 dielectric layer.
Electrical Transport Measurements: The current-voltage (IV) characteristics were measured using a Keysight B2912A.The IV data were recorded by sweeping gate voltage from negative to positive voltages.For recording gating curves, the source-drain voltage was set to 1 V.The Arduino software was used to set rpm values during strain reliability tests.

Figure 1 .
Figure 1.a) Schematic representation of the tunable thin Al 2 O 3 dielectric oxide film transfer process, b) photograph of floating alumina membrane.

Figure 2 .
Figure 2. a) Top-view SEM images of the alumina membrane on grapheneSi, b) SEM image of cracked edge, c) optical micrograph of Al 2 O 3 membrane on grapheneSi showing the presence of multilayers in the underlying graphene, d) AFM image of edge region of Al 2 O 3 transferred on graphene with imperfections originating from wrinkled graphene, e) cross-sectional step height corresponding to line in (d).

Figure 3 .
Figure 3. a) Schematic of the vdW dielectric-integration into a capacitor structure with a graphene and an Au electrode (inset) device schematics and Leakage current versus voltage characteristic fabricated using optimal ALD condition for 14 nm Al 2 O 3, b) Photograph and schematic of graphene FET, c) representative Raman spectra of the same graphene region before and after the transfer of ALD Al 2 O 3 , d) Transconductance plot of graphene FET.

Figure 4 .
Figure 4. a) Photograph of bending apparatus.b) Representative current−voltage response with and without applied strain, c) Plot of normalized change in electrical resistance versus strain for graphene.d) Resistance versus strain/release cycle between 0.3% and 0.4%, e) Representative plot of resistance versus strain-release for 15 cycles.

Table 1 .
Comparison of previous reports on alumina dielectrics to our work.