Stateful In‐Memory Logic System and Its Practical Implementation in a TaOx‐Based Bipolar‐Type Memristive Crossbar Array

Memristive stateful logic enables energy‐ and cost‐efficient in‐memory computing, which is desirable for edge computing in the coming Internet of Things  (IoT) era. Researchers have recently developed various stateful logic gates and have shown viable computing applications based on ideal memristive characteristics. However, few studies have demonstrated a system‐level in‐memory computing operation that can address the practical issues affecting device realization. Herein, a practically viable stateful logic device based on a 1‐transistor−1‐memristor (1T1M) array structure is proposed, considering the inherently stochastic memristor characteristics. Details on how to select the viable stateful logic gates in a given memristor are shown, and as an example of logic cascading, they are implemented in a device to operate a multibit carry look‐ahead adder. Then, an in‐memory computing layout that can perform all of the computing functions—data storing, transferring, and executing—inside the memory, addressing data traffic issues, is suggested. Finally, a software/hardware mixed stateful logic emulator that can virtually mimic array‐level in‐memory computing hardware based on cell‐level memristive characteristics is demonstrated.

DOI: 10.1002/aisy.201900156 Memristive stateful logic enables energy-and cost-efficient in-memory computing, which is desirable for edge computing in the coming Internet of Things (IoT) era. Researchers have recently developed various stateful logic gates and have shown viable computing applications based on ideal memristive characteristics. However, few studies have demonstrated a system-level in-memory computing operation that can address the practical issues affecting device realization. Herein, a practically viable stateful logic device based on a 1-transistorÀ1-memristor (1T1M) array structure is proposed, considering the inherently stochastic memristor characteristics. Details on how to select the viable stateful logic gates in a given memristor are shown, and as an example of logic cascading, they are implemented in a device to operate a multibit carry look-ahead adder. Then, an in-memory computing layout that can perform all of the computing functions-data storing, transferring, and executing-inside the memory, addressing data traffic issues, is suggested. Finally, a software/ hardware mixed stateful logic emulator that can virtually mimic array-level in-memory computing hardware based on cell-level memristive characteristics is demonstrated.
in a memory operation. If the variation in the programming voltage of a certain gate is more severe than the required operating voltage margin, the gate will not be practically available. Nevertheless, there have been few studies that consider the switching voltage variation into the logic operation.
Second, a compact and viable data manipulation method is required. In previous studies of cascading logic gates, it was assumed that the inputs were well aligned to the designed gate operation. [18,19,33] However, in a 2D or 3D array, the data may exist at any location on the array. Furthermore, the target address of the output may be occupied by other data. In such cases, the data first have to be relocated before performing the specific logic gate, which is possible via a data copy or transfer manipulation.
In this study, we propose a practically viable in-memory logic device and system. We first collect all possible stateful logic gates and systematically evaluate their practical validity, considering the device variations from experiments. We present a detailed methodology for evaluating the validity of the logic gates. The results showed that only five gates (NOT, NOR, IMP, OR, and BUFFER) were valid in our TaO x -based 1-transistorÀ1-memirstor (1T1M) array device, considering its statistical variation. Then, we show a compact multibit carry look-ahead adder (CLA) operation, utilizing the practically available gates, enhanced by parallel logic operation. As a demonstration, we develop an in-memory computing emulator, where a software-based controller is used to operate the 1T1M array hardware, and successfully demonstrate the CLA operation. Finally, we propose a crossbar array layout composed of memory, bus, and logic sections for organized data manipulation, to implement in-memory computing. Figure 1a shows a conceptual schematic of the stateful neural network using the McCulloch-Pitts neuron model proposed by Sun et al. [19,34] In the schematic, the inputs are conductance (G i ), which represents the state of the memristor cells (i ¼ A, B, and C), and a series resistor (i ¼ R). Then, the weight values (W i ) go into the machine. In the crossbar array device, the form of the weight value is a voltage, where a current value is G i times the applied voltage (V i ). Inside the machine, the currents are summed by Kirchhoff 's current law, and the actual voltage potential across each memristor cell (ν i ¼ V i -V NODE ) is determined accordingly, where V NODE is a node potential of the opposite terminal of V i which can be expressed [19] by Then, if any ν i on the memristor exceeds the switching threshold voltage (θ), the corresponding memristor cell is switched, and its conductance is updated as a logical output. Here, the logic gates can be categorized depending on whether the cell is set switched or reset switched, into SET-logic gates and RESET logic gates. Figure 1a shows the initial "0" state (or false) of C, which is updated to the "1" state (or true) by the SET-logic gates. Figure 1. Logic-gate evaluation procedure considering the variation of memristor. a) A conventional stateful neural network model that does not consider the variation in switching threshold voltage (upper panel) and a proposed model that considers (lower panel). b) Typical switching voltage distribution for bipolar memristors. c) Switching voltage distributions normalized to V SET,Max for SET-logic and to V RES,Min for RESET-logic. The unit values are highlighted in yellow. d) Definition of parameters given in part (c). e) Voltage conditions need to be considered for possible cases in SET-logic and RESET-logic. f ) Schematic of circuit for implementing IMP gate. States P and Q refer the logical values of two memristors. g) Truth tables and required voltage conditions corresponding to each case in the truth tables before and after the IMP gate operation.
www.advancedsciencenews.com www.advintellsyst.com In the conventional scheme (top panel of Figure 1a), the switching voltage is assumed to be a constant value; therefore, the logical output is deterministic once ν i is obtained. However, in reality, the switching voltages are inherently stochastic. [35][36][37][38] In this regard, the bottom panel in Figure 1a is more realistic. The θ is distributed and the output is a problematic function of the degree of θ variation. [19,39] Then, for guaranteed gate operation, v i should be higher than the maximum amplitude of θ variation. Therefore, for deterministic gate operation, the acceptable value of θ variation should be systemically examined for practical use in the stateful logic gate.
Here, we establish a procedure to evaluate the degree of immunity of the logic gates against θ variation. To accomplish that, we first redefine several parameters related to the switching voltages and their distribution. Figure 1b shows the switching voltage distribution of a typical bipolar memristor. It also corresponds to the characteristic of the device used in this study. Here, the set voltage (V SET ) is the threshold voltage needed to change a high resistance state (HRS) to a low resistance state (LRS) where the HRS and LRS represent logical "0" and "1" values, respectively. The set switching is drastic, so an applied voltage exceeding V SET can directly change the HRS to the LRS. The reset voltage (V RES ) is the threshold voltage needed to change the LRS to the HRS. Unlike the set switching, the reset switching of our device is gradual, so a complete reset switching is possible by applying a clear voltage (V CLR ), which is lower than the V RES . If the reset switching is abrupt in other memristors, V CLR is simply equal to V RES . In different types of memristors, other cases are possible; either the set switching can be gradual or the reset switching can be drastic. In those cases, the distribution model can be applied with a simple modification. The maximum and minimum values and their distribution are shown for each switching voltage.
For further simplification and generalization, the switching voltages are normalized to the V SET,max and the V RES,min for the SET-and RESET-logic gates evaluation, respectively, and only the important parameters are shown in Figure 1d. For example, in the SET-logic (the upper panel in Figure 1c), Δ SET is defined by [(V SET,max -V SET,min )/V SET,max ], and ρ RES is by (-V RES,max / V SET,max ). Similarly, in the RESET-logic (the lower panel in Figure 1c), Δ RES and ρ SET are defined by [(V RES,min -V RES, max )/V RES,min ] and (-V SET,min /V RES,min ), respectively. In addition, χ CLR is defined by (V CLR,min /V RES,min ). These parameters are shown in Figure 1d.
For a successful logic operation, the following conditions should be satisfied. In the SET-logic, 1) for the cells maintaining the 0 state, the normalized potential on them (ν M ) should be lower than (1 -Δ SET ) (i.e., ν M < 1 -Δ SET for 0 ! 0); 2) for the cells maintaining the 1 state, the ν M should be higher than (-ρ RES ) (i.e., ν M > -ρ RES for 1 ! 1); and 3) for the output cell changing from 0 to 1, ν M should be higher than 1 (i.e., ν M > 1 for 0 ! 1). The case for the state changing from 1 to 0 can be neglected because there is no such case in the SET-logic. In the RESET-logic, 1) for the cells maintaining the 0 state, ν M should be lower than ρ SET (i.e., ν M < ρ SET for 0 ! 0); 2) for the cells maintaining the 1 state, ν M should be higher than (-1 þ Δ RES ) (i.e., ν M > -1 þ Δ RES for 1 ! 1); and 3) for the output changing from 1 to 0, ν M should be lower than (-1) before switching, and it should be lower than (-χ CLR ) after switching (i.e., ν M < -1 before switching and ν M < -χ CLR after switching for 1 ! 0). The case for the state changing from 0 to 1 can be neglected. These conditions are shown in Figure 1e.
Then, the voltage condition rules in Figure 1e can be applied to each gate. Figure 1f,g shows an example of the application of the logic rules in Figure 1e to the IMP gate by Borghetti et al. [6] Figure 1f shows the logic unit with two memristors. Here, ν P and ν Q are the actual voltage potentials on two memristors, M P and M Q . Figure 1g shows 16 voltage conditions for every possible input and output case during the IMP gate operation. For successful IMP gate operation, all 16 conditions should be satisfied. If the duplicated inequalities are neglected, only eight conditions (yellow-colored cells) have to be considered.
In the inequalities, there are two variables (Δ SET and ρ RES ) in the SET-logic and three (Δ RES, ρ SET , and χ CLR ) in the RESET-logic. To solve the inequalities, the maximum value of Δ SET (or Δ RES ) is calculated as a function of ρ RES (or ρ SET and χ CLR ). Once the maximum value of Δ SET (or Δ RES ) is obtained, the required V P and V Q can be obtained accordingly. (A more detailed calculation process is shown in Supplementary Note I and Figure S1 and S5, Supporting Information.) Here, the maximum value of Δ SET (or Δ RES ) is defined as a "variation tolerance factor" (VTF) which shows how much the logic gate is tolerant against variation in switching voltage. For example, in a specific SET-logic gate, the logic gate is practically viable only if the experimentally obtained Δ SET of a certain memristor is smaller than the VTF of the logic gate. As such, by comparing the VTF value and the experimentally obtained Δ SET for the SET-logic (or Δ RES for the RESET-logic), the viability of the logic gates can be intuitively determined. Taking the IMP gate, for example, the solution indicates that VTF is 0.333, and is independent of ρ RES . Therefore, the gate is viable if the device has a Δ SET lower than 0.333.
In this way, the VTF values of all logic gates can be obtained. The lists of SET-logic and RESET-logic gates are shown in Figure 2a,e, respectively. [6,7,[17][18][19][20][21][22] The first digit in the gate name refers to the number of cells required to execute the gate.
The "-f" at the ending refers to the floating of V R during gate operation. At "2IMP" gate, for example, two cells are inputs, and one of them is an output cell, which is set switched only if both cells are in the HRS. At "3NOR" gate, for another example, two cells are inputs, and another cell is assigned to the output, which is set switched only if all input cells are in the HRS. Truth tables of all logic gates are shown in Figure S6, Supporting Information. The listed logic gates can be executed in a single step in the bipolar memristor array. The ρ RES dependence suggests that the memristor with the higher ρ RES can synthesize more gates at a given Δ SET . Similarly, Figure 2f-h shows the VTF values for the RESET-logic gates for ρ SET ¼ 2 and χ CLR ¼ 1, ρ SET ¼ 1 and χ CLR ¼ 1, and ρ SET ¼ 2 and χ CLR ¼ 2, respectively. The insets also show the corresponding I-V curve shapes. The results show that a higher ρ SET and a smaller χ CLR are desirable to obtain an additional number of RESET-logic gates.
The aforementioned methodology was applied to our device, and the VTF values were calculated. Figure 3a shows a part of 128 Â 64 sizes of 1T1M per cell crossbar array device used in this study. The 1T1M device was adopted to eliminate the sneak current problem. The details of the device fabrication can be found in the Experimental Section and previous studies. [40,41] For stateful logic operation, multiple cells can be accessed in two ways. First, the memristors along one-word line can be accessed together by selecting one shared gate line (the blue square in Figure 3a). Once the shared gate is open, the array size can be equivalent to (n Â 1), where n is the number of rows of the array, as shown in Figure 3b. This is the most optimum configuration against the sneak current. Second, the memristors along the selected bit line can be accessed together by selecting multiple gate lines (the red square in Figure 3a), whose unit circuit is shown in Figure 3c. In this case, the effective array size can be (n Â m), where m is the number of selected gate lines. This configuration is useful for executing some logic gates in parallel. [39,42,43] In both configurations, by applying appropriate voltages on the word and bit lines, a specific gate operation is possible without disturbing other cells, when the gate is closed. Also, in the 1T1M structure, the transistor acts as a current limiter (i.e., a series resistor) so that the reliability of the device is ensured. [44] Moreover, the transistor can work as an in-cell series resistor component that can increase the absolute value of V RES , and, thus, it is beneficial for the SET-logic gates but harmful to the RESET-logic gates. Figure 3d shows our 1T1M device structure with a Ta/TaO x /Pt memristor. The inset shows a top-view SEM image of the device. Figure 3e   www.advancedsciencenews.com www.advintellsyst.com caused the lower switching voltage amplitude and the higher voltage variation. [45,46] Therefore, the selection of the sweep rate is crucial for the practical stateful logic operation. The abrupt set switching and the gradual reset switching shown in Figure 3e are representative characteristics of TaO x -based devices. [47,48] Then, to enhance the statistical reliability of the data from a limited number of datasets, V RES and the V CLR were fitted with the Weibull distribution, [49] and V SET with normal distribution. The details of the distribution fitting are shown in Figure S8, Supporting Information. From the distribution fitting, 99.5% confidence intervals were [-2.406, -0.871] for the V CLR , [-1.086, -0.888] for the V RES , and [1.338, 1.986] for the V SET . These intervals were set to the maximum and minimum switching voltages shown in Figure 1b, which gave Δ SET and Δ RES of 0.326 and 0.182, respectively. Also, the normalized parameters were ρ RES ¼ 0.447, ρ SET ¼ 1.232, and χ CLR ¼ 2.216. From these parameters, the VTF values of the SET-and RESET-logic gates can be obtained, which are shown in Figure 3f,g, respectively. By comparing the VTF value and Δ SET in the SET-logic (or Δ RES for the RESET-logic), the viable logic gates in our device are 2NOT, 3NOR, and 2IMP gates in the SET-logic and 3OR and 2BUFFER gates in the RESET-logic.
The theoretical successful gate operation rate (shortly a success rate) from the VTF value was confirmed by experiments, by executing two logic gates, 3NOR and 3NAND. The two gates are representative SET-logic gates whose VTF values were 0.333 and 0.143 independent on ρ RES . In the demonstration, the devices with the Δ SET of 0.383 and 0.340 were used to verify the success rate accurately under imperfect conditions. Figure 3h compares the success rate of the gate operation in theory and from experiments for two gates. The inset schematics show the circuit configuration and biasing conditions for the operation. In executing the 3NOR gate, Δ SET is higher than the VTF indicating that the 3NOR gate operation from the given device cannot be a zero error. The calculated theoretical success rate for changing the (000) state to the (001) was 99.79%, and for keeping the (010 or 100) and (110) states, it was 97.82% and 99.99%, respectively. The experiments showed 100%, 98%, and 100% success rates in each case from 50 trials, respectively, which reproduced the theoretical values accurately.
In executing the 3NAND gate, the 0.340 of Δ SET was far higher than 0.143 of VTF. In that case, the theoretical success rate of changing the (000) and (010 or 100) states to the (001) and (011 or 101) were 100% and 99.81%, respectively. Meanwhile, the theoretical success rate for keeping the (110) state was 29.98%, which is a problematic operation related to a malfunction of the 3NAND gate. The experiments also reproduced 100%, 100%, and 30% of the theoretical success rates for each case. The raw data from the experiments are shown in Figure S9 and S10, Supporting Information. Figure 4a shows the CLA, one of the multibit adder types developed, to provide a faster and more efficient operation than a ripple carry adder (RCA). [50,51] Unlike the RCA, where the carry and sum bits are calculated sequentially, the CLA carries out the calculation in parallel; the carry-out values of all bits are obtained first, and then, the sum values are calculated later. For the CLA operation, the circuit requires a carry look-ahead generator to calculate the carry-out values at the same time. This is complicated but can improve the calculation speed dramatically. The parallel operating capability of the stateful logic gate makes it capable of implementing the CLA without any additional circuits.
To execute the n-bit CLA operation (where n ¼ 4), a 5 Â 13 crossbar matrix was prepared and the cells were programmed, as shown in Figure 4b, which corresponds to the initialization step. Here, the dashed vertical lines, solid vertical lines, and horizontal lines refer to the gate, word, and bit lines, respectively. In the matrix, four sets (n ¼ 1, 2, 3, 4) of addend and augend (A n , B n ) are located at a 4 Â 2 crossbar matrix at the left side of the array. Then, the carry-in input (C in ) is located at the top of the third column. Other cells in the third column were initialized to the LRS where the carry-out values were to be programmed by the RESET-logic. All other cells from the fourth column to the end were initialized to the HRS. This data arrangement allows the most efficient CLA operation, fulfilled by a parallel gate operation.
Once the cells are ready to process, the first step is to calculate all carry-out values. Figure 4c shows the most optimized carry look-ahead generator designed for the stateful logic operation. It utilizes three practically available gates: the 2NOT and 3NOR gates of SET logic, and the 2BUFFER gate of the RESET logic. In the carry look-ahead generator, the carry-out values (C nþ1 ) of the inputs (A n , B n , and C n ) are stored at the (3, n þ 1) position in the (x, y)-coordinate, where the left-top corner is defined as (1,1). For that, the first step is to calculate C 2 and store the datum at (4, 1). The C 2 is equal to

and, thus, it can be expanded to
Because the 3NOR gate can store the output of A 1 Â B 1 to any cell and the summation (þ) of the logic can be simply achieved by overwriting the data on the same cell, the C 2 output can be recorded at the (4, 1) position by executing the 3NOR gate three times: C 2 00 ←3NORðA 1 , B 1 Þ, C 2 0 ←3NORðB 1 , C 1 Þ, and C 2 ←3NORðC 1 , A 1 Þ: Detailed explanations of the solving process and overwriting are shown in Figure S11, Supporting Information. Then, C 2 can be stored at the (4, 2) position by flipping the datum in (4, 1) using the 2NOT gate. Finally, C 2 can be copied from the (4, 2) position to the (3, 2) position by executing the 2BUFFER gate. Consequently, the A 2 , B 2 , and www.advancedsciencenews.com www.advintellsyst.com C 2 values can be lined up in the second row with five steps. In this way, the carry-out value can be consecutively stored in the next column, and 5n steps are required to store all of the carry-out values of the n-bit CLA.
Once the carry-out values are lined up in the third column, the sum values can be calculated in parallel. Figure 4d shows the sum generator. The sum calculation is equal to (A ⊕ B) ⊕ C and it can be re-expressed to (A ⊙ B) ⊙ C, where A ⊙ B is equal to ðA þ A þ BÞ þ ðB þ A þ BÞ (⊕: XOR gate, ⊙: XNOR gate). The solving process is also shown in Figure S11, Supporting Information. Consequently, the sum calculation is possible by repeating the 3NOR gate eight times. Also, the 3NOR gate can be performed over multiple rows in parallel because the biasing of every bit line allows every row to work independently. Therefore, the sum values of n inputs can be calculated together.
In the sum generator, steps 1-4 correspond to the first XNOR operation and steps 5-8 to the second XNOR operation. As a result, the sum results are stored at the last columns in eight steps.
Combining the carry-out and sum calculation, n-bit CLA requires 5n þ 8 steps. Table S1, Supporting Information, shows the number of cells and steps for executing n-bit full adder compared with previous technologies. Although our work is not the most efficient, it is the only practically feasible one among the technologies.
The aforementioned n-bit CLA operation assumed that the input data were well-organized, as shown in Figure 4b, before performing the designed sequence. However, because the data are physically scattered over the memory array, they need to be physically relocated to the designed location. In this regard, we suggest a new in-memory computing device layout design. Figure 5a schematically shows the proposed crossbar layout. The array is composed of memory, logic, and bus sections. All of the sections are physically identical, but their roles are distinguishable. In the memory section, the data are stored permanently. In the logic section, the data are not used for permanent data recording but are used temporally as a cache memory only for the logic operation. Also, considering that the stateful logic operation is executed along a 1D direction, a bus section is assigned to buffer the data during data manipulation. Then, the original data at any location in the memory section can be copied to the bus section along the vertical direction first and to the target column along the horizontal direction inside the bus section. In the end, they are copied to the final position in the logic section. Once the data are copied to the defined location, the n-bit CLA calculation can be executed. Afterward, the output can be returned to the memory section in reverse sequence.
To conduct a hardware-based CLA demonstration, it requires at least 51 individual voltage sources for basing the gate, bit, and word lines of the 5 Â 13 size of the 1T1M array independently. Due to a lack of hardware resources, instead, we developed a software-assisted in-memory computing emulator. Figure 5b  shows an emulating algorithm for one gate operation. The emulator is virtually mimicking the 1T1M crossbar structure and makes it possible to apply any voltage on the gate, bit, and word lines of the crossbar. Once the array is biased, the emulator calculates all the voltage potentials on the memristors (ν (i,j) where i ¼ [1:5] and j ¼ [1 :13]) in the array. Then, ν (i,j) is applied to the memristor hardware and the response by ν (i,j) is obtained. Then, the outputs are returned to the emulator and updated, and ν (i,j) is recalculated. This process is repeated until every cell reaches a nonswitching condition. Once the steady state is obtained, one logical step is finished. Figure 5c shows an initialized bitmap for a 4-bit CLA operation where the digital inputs are 1101 and 1001 and the carry-in is 0. Here, the darker cell and brighter cell refer to the HRS and LRS, respectively. Figure 5d shows the bitmap after performing the voltage sequence shown in Figure 4. A detailed step-by-step snapshot of the procedure can be found in Figure S12 and S13, Supporting Information. A full video of the 4-bit CLA operation procedure from the emulator can also be found in the Supporting Information.
In this study, we demonstrated a 4-bit CLA operation using a 1T1M array with the help of a software-based logic controller. For the successful demonstration, we systematically selected practically viable stateful logic gates that would stochastically guarantee a complete logic operation. Although our device was not commercially optimized in that device uniformity was not highly assured, we found that five gates were executable, and this allowed n-bit CLA operation in 5n þ 8 computational steps with a (n þ 1) Â 13 size array. To implement the stateful logic system, we proposed a new memory layout concept composed of memory, bus, and logic sections which were physically identical but functionally divided. This allowed effective data manipulation, avoiding the data traffic issue.
For the next advance of the stateful logic technology, some issues should be addressed. First, improving switching uniformity was found to be the most crucial factor for better energy and time efficiency. If the device uniformity can be improved so that 5SUM and 4CARRY gates become possible, the total number of steps for the full adder execution can be reduced to 2n. Second, an unwanted switching of memristor can occur after a long time due to the accumulation of the voltage stress or the nonlinear switching dynamics of the memrsitor. [52] For resolving the problem, one may insert a periodic refresh step that can eliminate the lurking error factor. Third, the increase in line resistance in the high-density device may cause deviceto-device variation and worsen the success rate of the gate operation. The line resistance is a serial parasitic resistance component such that it can be compensated if R S is controllable. Moreover, the control of R S itself can enhance the functionality of the stateful logic. [20] Therefore, the next stateful logic technology should find a way on how to control the R S value systematically.
The proposed in-memory computing system is not the most energy efficient, nor has the highest computing performance. The first virtue of the device is its low cost and small size, which is desirable for the cost-cutting computing of the IoT era, rather than performance-oriented computing. Considering the structural similarity between 1T1M and DRAM, whose price is about <1 dollar per 1 GB, we expect that a fully functional computing device can be integrated on a chip for less than a dollar, which would open a new computing market in the future.

Experimental Section
Device Fabrication: A device with a minimum 2.8 μm transistor channel width with two levels of metallization for the gate, source, drain, and ground contacts was fabricated using a commercial foundry. A memristor cell with a Ta/TaO x /Pt structure was integrated at the top of the device in a lab. Its top (50 nm-thick Ta) and bottom (55 nm-thick Pt) electrodes were evaporated and patterned by e-beam lithography followed by a lift-off, and the 15 nm-thick TaO x layer was sputtered at Ar and O 2 mixed ambient with 75% of O 2 partial pressure.
Electrical Measurement: Each device was measured using a probe station and semiconductor parameter analyzer (Keithley 4200A-SCS).
To measure the characteristics of the 1T1M device, 1.2 V was applied to the transistor gate, and the current was obtained by sweeping the voltage on the top electrode, which was directly connected to the memristor. At this time, the bottom electrode and transistor body were connected to ground.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.