Versatile Thin‐Film Transistor with Independent Control of Charge Injection and Transport for Mixed Signal and Analog Computation

New materials and optimized fabrication techniques have led to steady evolution in large area electronics, yet significant advances come only with new approaches to fundamental device design. The multimodal thin‐film transistor introduced here offers broad functionality resulting from separate control of charge injection and transport, essentially using distinct regions of the active material layer for two complementary device functions, and is material agnostic. The initial implementation uses mature processes to focus on the device's fundamental benefits. A tenfold increase in switching speed, linear input–output dependence, and tolerance to process variations enable low‐distortion amplifiers and signal converters with reduced complexity. Floating gate designs eliminate deleterious drain voltage coupling for superior analog memory or computing. This versatile device introduces major new opportunities for thin‐film technologies, including compact circuits for integrated processing at the edge and energy‐efficient analog computation.

DOI: 10.1002/aisy.202000199 New materials and optimized fabrication techniques have led to steady evolution in large area electronics, yet significant advances come only with new approaches to fundamental device design. The multimodal thin-film transistor introduced here offers broad functionality resulting from separate control of charge injection and transport, essentially using distinct regions of the active material layer for two complementary device functions, and is material agnostic. The initial implementation uses mature processes to focus on the device's fundamental benefits. A tenfold increase in switching speed, linear input-output dependence, and tolerance to process variations enable low-distortion amplifiers and signal converters with reduced complexity. Floating gate designs eliminate deleterious drain voltage coupling for superior analog memory or computing. This versatile device introduces major new opportunities for thin-film technologies, including compact circuits for integrated processing at the edge and energy-efficient analog computation.
minimal, low-distortion gain stages and compact, multilevel digital-to-analog converters. Finally, we describe the advantages of the MMT's FG variant in suppressing deleterious capacitive coupling effects for facile analog processing, as a stepping-stone toward robust, efficient LAE neuromorphic systems. [9] In its basic structure, the staggered-electrode MMT (Figure 1b) has the typical source and drain contacting a semiconductor with multiple control gates separated by insulating layers. There have been several ingenious applications of auxiliary gates in transistor structures, designed to preferentially select for one charge carrier type in ambipolar materials, or to increase the effective mobility. [14,18] Although structurally similar, the MMT contains a deliberately-engineered energy barrier at the source contact [16,[22][23][24][25][26] as the foundation of the current control process involving one or more injection control gates (CG1). Situated opposite the source, CG1 provides the means for controlling the quantity of charge injected into the device. The channel control gate (CG2), situated above the source-drain gap, toggles the conduction state of the semiconductor between the source and drain. As such, CG1 exclusively controls the current level, whereas CG2 halts or permits the flow of current without affecting its magnitude. The combined "analog" injection and "digital" switching ( Figure S2, Supporting Information) make possible the device's exceptional versatility, enabled by modulating contact properties as its prime input.
To illustrate the operating principle of an n-type MMT, we refer to the schematic cross-sections in Figure 1d, in which the drain is positively biased. All analyses were performed in common-source configuration, and therefore we refer to node potentials relative to the grounded source. Positive CG1 potential V CG1 accumulates the semiconductor-insulator interface, but charge transport to the drain is restricted by the highly resistive source-drain gap (Figure 1d, left). Similarly, an accumulated "channel" via CG2 positive bias V CG2 produces no current flow in the absence of CG1 potential (Figure 1d, center). The simultaneous application of CG1 and CG2 bias allows charge injection at the source and transport to the drain (Figure 1d, right). The shaded area within the semiconductor indicates the depletion region created when the source energy barrier is reverse biased by the applied drain voltage, pinching-off the accumulation layer and resulting in low-voltage saturation of electrical characteristics. [22,[27][28][29] Figure 1. Multimodal transistors (MMTs). a) New design philosophies produce large steps in development, in contrast to incremental performance gains, due to material advances or process optimization. b) Schematic representation of a MMT showing the four electrical terminals: source (S), drain (D), and control gates (CG1 and CG2). c) Diagrammatic application of MMT gain and signal-processing stages in a multisensor integrated system. d) Schematic cross-sections indicating the separate injection and conduction processes within an n-type MMT, where CG1 exclusively controls magnitude of drain current and CG2 provides a conductive path without influencing charge injection. e) Schematic representations of conduction band profile under various bias conditions. f ) Top view of a typical microcrystalline silicon (μ-Si) MMT. g) Measured MMT output curves. h) Measured MMT transfer curves with varying CG2 voltage show the ability to turn off current flow, and the independence of drain current on CG2 input when the device is on. i) Measured MMT transfer characteristic with varying CG1 voltage.
www.advancedsciencenews.com www.advintellsyst.com Band diagrams extracted from simulation are discussed in Figure S3, Supporting Information, while a qualitative conduction band energy profile is shown in Figure 1e. In the left panel, the device is conducting and in saturation. Drain voltage variations translate exclusively into changes in channel potential. As the magnitude of the current is solely controlled at the source by CG1, drain current is practically independent of both drain bias and of source-drain gap. Increasing the CG1 voltage (solid line; Figure 1e, center) boosts injection from the source area via two overlapping mechanisms discussed elsewhere. [22,[27][28][29][30] Finally, the effect of CG2 voltage is shown in the right panel. The device is "off" when no potential is applied. When channel conductance increases above a minimum value, applied CG2 voltage does not play a role in controlling drain current magnitude. Figure 1f shows a typical microcrystalline silicon (μ-Si) MMT, denoting the source-drain gap (d), and source-CG1 overlap (S). As these devices have two control terminals, one set of output and two sets of transfer characteristics are measured to study device behavior. Output characteristics (Figure 1g) show the expected signs of purposeful contact-controlled injection: low dependence of drain current I D on drain voltage V D and low saturation voltage, V DSAT . The saturation coefficient γ ¼ dV DSAT / dV CG1 is estimated at 0.18, much smaller than the unity value of conventional TFTs, indicating low series voltage operation capability. [27,28] Next, Figure 1h shows the effect of CG2 bias for a range of V CG1 . As expected, when the channel is "on", the current is largely independent of CG2 voltage, except for the presence of a moderate kink effect, [31,32] discussed later. Devices in this batch have a negative threshold, therefore turning "off" the channel requires negative V CG2 . Lastly, the CG1 transfer curve in Figure 1i confirms the expected modulation of drain current over several orders of magnitude with applied CG1 bias. Although I D magnitude is low, these initial results confirm MMT operation. With optimization, MMTs should match the current density seen in other contact-controlled devices, [22,29] and improve with advancements in materials and techniques ( Figure 1a).
Further electrical data are included in Figure S4 and S5, Supporting Information.
Charge control at the source of the MMT closely resembles that in source-gated transistors (SGTs). [27][28][29]33] As such, the analysis in the study by J. Zhang et al. [29] applies in the first order. In saturation, we can describe the fundamental operation of an ideal MMT device by the following equation.
where g m ¼ dI D /dV CG1 is the transconductance associated with CG1 and V th2 is the value of V CG2 above which it has no influence on I D .
It is essential to design the device so that electric fields generated by CG2 do not penetrate to the source. Optimized MMTs should show significant tolerance to gross misalignments ( Figure S6 and S7, Supporting Information).
We now demonstrate the practical consequences of the independent MMT control processes via TCAD simulation of prototypical devices, focusing first on performance, and subsequently on functionality. The injection of charge at the source follows the behavior of SGTs. [22,29] These extensively studied devices produce excellent d.c. characteristics, but an exceedingly long response time, arising from the low transconductance afforded by the rectifying contact, combined with the large gate-source overlap capacitance necessary for optimal injection. [34] MMT construction allows the separation of the "slow" injection from the "fast" channel switching. Figure 2a shows the comparative transient response time for TFT, SGT and MMT devices. An extremely fast initial transient is observed for the MMT. The settling time to 1% of final output voltage also reduces with V CG2 , eventually outperforming the equivalent TFT (Figure 2b). This preloading effect of V CG1 eliminates the time required to accumulate the insulator interface in the source region. The CG1-CG2 interplay ( Figure 2c) is studied further in Figure S8, Supporting Information. High V CG2 , which may be expected to reduce transient time, could degrade the output conductance in certain semiconductors (Figure 2d), in which high electric fields seen at the channel extremities ( Figure 2e) lead to hot-carrier effects [31,32] depending on the biasing condition. Where possible, the lowest value should be chosen for V CG2 , while ensuring that the channel: 1) is sufficiently conductive so that it does not impede the current flow set by V CG1 and 2) is never strongly pinched-off at the drain end.
Since MMT operation has the intrinsic ability to switch significantly faster than the SGT, in logic applications, connecting CG1 to the relevant power rail would lead to improved switching speed, at the same time preserving the noise margin, gain, and energy efficiency shared with SGTs. Thus, the MMT marks an order-of-magnitude performance gain in the transient capability of contact-controlled transistors.
As to the expansion of functionality granted by the distinct controls, CG2 can be conceived of as an "enable" signal. A compact multipurpose application is MMT-based digital-to-analog conversion (DAC). Several CG1 electrodes ( Figure 2f and Figure S11, Supporting Information) act as inputs taking binary-coded values. Their contact areas A i are such that A i ¼ A 0 · i, where i is the respective power of 2 and A 0 is the area corresponding to the least significant bit (LSB). CG2 is connected to a sample-and-hold (S/H) signal, thereby realizing an extremely compact circuit (Figure 2g), which produces an output voltage deflection proportional to the input digital value (Figure 2h).
The MMT DAC is a typical example of the device's ability to provide complex functionality while significantly reducing component count, a paramount consideration for the success of LAE fabricated with extremely low-cost methods. [11] For example, wirelessly powered, fully printed functional tags (Figure 2i) containing minimal circuitry for power management and digital data handling would only require this compact and robust DAC to produce, with low distortion, analog signals required by a display, alarm, or actuator module.
Up to this point, we have focused on device operation using CG2 as the main functional input. The following analysis concentrates on CG1, specifically on its role in attaining constant transconductance, g m ¼ dI D /dV CG1 . A linear input-output relationship is highly desirable for many signal-processing applications, but typically requires large linearization circuits. Achieving this behavior with a minimal set of components is essential in LAE technologies. [11] The source area of the MMT can be analyzed similarly to SGTs, [22,27] observing that the injection along the length of the source can be ohmic and directly proportional to applied CG1 bias. To obtain close to linear dependence of total drain current on CG1 voltage, the contribution from the high field region at the edge of the source (x ¼ 0 in Figure 1d) needs to be reduced. [22] In the MMT, this is assisted by the opportunity to keep the source-drain gap highly conductive regardless of the input signal on CG1. As such, MMTs can achieve constant g m , confirmed by measurements on initial μ-Si devices. Output curves (Figure 3a) have γ % 0.16 and good saturation, indicating contact-controlled operation. The transfer plot in Figure 3b shows remarkable linearity (constant g m ), with a 0 V abscissa intercept (direct proportionality).
We note that both linear behavior and direct proportionality result from the correct design of the transistor, and manifest in saturation, unlike in conventional TFTs, adding to the application versatility. Usual threshold control techniques can translate the transfer curve horizontally, while optimizing device electrostatics attains constant g m over a wide span of V CG1 . Simulated transfer curves (Figure 3c) show normalized I D and its dependence on insulator thickness t i , with direct proportionality at low V CG1 for t i ¼ 20 nm.
Cut-lines along Cut 2 of Figure 1d indicate that the region of linearity in the transfer curve correlates to the range of V CG1 for which potential traces are parallel and equally spaced (Figure 3d,e, Figure S9 and S10, Supporting Information).
This region starts at V CG1 for which the whole source length contributes to charge injection, a value which depends on the electrostatics and conductivities of essential regions of the device.
As linearity and saturation are affected by the properties and sizing of the semiconductor and insulator, a trade-off emerges ( Figure 3f ). With the present choice of materials, t s ¼ 40 nm and t i ¼ 20 nm result in the optimum linear transfer curve for lowest V CG1 operation. The corresponding γ % 0.39 is comparable with the value of %0.32 extracted from output characteristics ( Figure S9c and S9d, Supporting Information) allowing low V DSAT .
A direct application of these findings is in low distortion amplifiers, where gain stage non-linearity produces unwanted frequency components in the output signal (Figure 3g). We simulated a common-source MMT amplifier in which the channel was fully open, focusing exclusively on the performance of the drive transistor by choosing a purely resistive load. In this application, a zero-intercept of the MMT transfer curve is not required, but the amplifier output must not saturate. Low distortion is observed for relatively large input excursion, improving when reducing t i . This is evidenced in the gain profile ( Figure 3h) and the spectral analysis of the output signal obtained for a pure sinusoidal input (Figure 3i). The linearity of the transfer characteristic arises as a trade-off against maximum g m , and consequently, the measured and simulated gain achievable in the current batch of devices is around 6-10. However, MMTs can be realized with higher g m at the expense of linearity, and output www.advancedsciencenews.com www.advintellsyst.com conductance, g d ¼ dI D /dV D , can be improved via the usual field relief strategies, for improved overall gain, A V ¼ g m /g d . [35] Similar benefits could be derived in certain pixel circuit designs where, for example, optical feedback may be used to create a simple means of compensating local pixel aging or large area non-uniformities (Figure 3j).
Yet another efficient use of constant g m is in the DAC circuits of Figure 2f-h. By generating drain currents that are simultaneously proportional to CG1 width and CG1 voltage, multilevel digital signals can readily be converted with minimal error. Figure 3k shows the output waveform of a 3-bit 3-level DAC, and the error of output current I out expressed as a percentage of I LSB . The optimum design for the current setup is S ¼ 4 μm with t i ¼ t s ¼ 40 nm, which offers low output error (%1.2% of I LSB ) for moderate to high input voltages. For digital data coded with lower voltage levels, t i ¼ 20 nm is optimal ( Figure S12, Supporting Information), correlated with the improved lowvoltage linearity (Figure 3c).
Leveraging the two control mechanisms and constant g m , conceivably the most attractive long-term application of MMTs is in the field of energy-efficient analog and neuromorphic computation ( Figure 3l). Compact circuits with complex functionality can be realized, in line with the immediate benefits of TFT-based edge computing for sensors. One additional advantage of MMT operation emerges in the FG embodiment. Discussed next are the facile implementation of analog operations and the analog memory capability (Figure 3m), with enormous potential for learning and reconfigurability in neuromorphic thin-film circuits.
As with the control method separation, we will analyze floating gate MMTs (FGMMTs) from both performance and functionality standpoints.
FG transistor architectures are widely used, typically for highdensity non-volatile memory and analog signal processing. [36,37] In particular, scaled, thin-film devices, in which the gate coupling region does not extend significantly beyond the device active area, suffer a loss of intrinsic gain due to parasitic capacitive coupling of the channel and drain potential to the FG. For these devices to be effectively used in emerging non-von Neumann approaches to computing based on neuromorphic or analog Figure 3. Linear input-output dependence and its applications. a) Measured output and b) transfer curves of a μ-Si MMT indicating constant transconductance g m , providing linear behavior in saturation. c) Simulated transfer characteristics. d) Simulated electron current density and e) potential plots confirming the mechanism for constant g m . f ) Saturation voltage and g m both depend on semiconductor and insulator electrostatics (simulated). g) Schematic illustration of amplifier distortion. h) Simulated MMT amplifier output and gain curves with total harmonic distortion (THD) values in the inset. i) Spectral analysis of the simulated amplifier output for a pure sine input. j) Conceptual application of the MMT as an emissive pixel driver, which exploits its linear response for facile local calibration via a feedback network. k) Simulated waveforms for a 3-bit 3-level high accuracy multilevel logic DAC exploiting constant g m . l) Conceptual diagram of a MMT-based multilayer perceptron, as a highly effective potential MMT application. m) In a FG design, the linear transfer curve of the MMT can be shifted by FG programming, resulting in proportional scaling of the current at a given voltage.
www.advancedsciencenews.com www.advintellsyst.com strategies, inherent limitations need to be addressed. This is especially true in thin-film devices, which suffer from variability, bias effects, and non-linearity. [2,11,36] For example, SGTs offer superior intrinsic gain [29,38] and robustness [39] when compared to conventional TFTs, but their gain characteristics suffer drastically in FG designs. FGMMTs are immune to gain reduction by design, having potential for greatly expanding the applicability of FG devices to advanced, energy efficient analog circuits.
The first FGMMT design (Figure 4a) has a single control gate, CG, and two FGs: FG1 overlapping the source and FG2 spanning the source-drain gap. μ-Si devices (Figure 4b and Figure S11a, Supporting Information) show low-voltage saturation with γ % 0.29, quasi-constant transconductance, and flat output characteristics (Figure 4c) indicative of low output conductance, g d and thereby retaining suitable gain.
TCAD simulations provide insight into gain loss in contact controlled floating gate SGTs (FGSGTs) and validate the superior behavior of MMTs.
In FGSGTs, the capacitive coupling of the FG to the channel (C GCh ) and drain (C GD ) ( Figure S14, Supporting Information) results in an increase of FG potential with V D , promoting injection at the source and deteriorating g d and A V (Figure 4d and Figure S15, Supporting Information). This is further discussed in Figure S16 and S17, Supporting Information.
FGMMTs with separate FG1 and FG2 show no g d degradation ( Figure S18, Supporting Information). Although the potential in the channel increases with V D (Figure S19a, Supporting www.advancedsciencenews.com www.advintellsyst.com Information), the potential in the accumulation region along the source contact (denoted V CH in Figure S14, Supporting Information, and primarily responsible for charge injection [22] ), remains constant, unlike in the FGSGT ( Figure S19b, Supporting Information). Essentially, in the FGMMT, the channel and drain (see Figure S14c, Supporting Information) capacitively couple exclusively to FG2, which has the effect of shielding FG1 from drain-induced potential variations (Figure 4e). Since the conductance of the source-drain gap does not play a role in regulating current in contact-controlled transistors, a large change in FG2 induced by V D produces no change in I D .
Specifically, the FGMMT's A V is maintained by keeping an extremely low g d (Figure 4f ). Naturally, charge trapping on FG1 can be exploited in the usual ways, [40] creating threshold shifts (Figure 3m), which allow operation as analog memory. Although programming experiments do not form part of the present study, this behavior is important, as it applies to a large range of widely used functional blocks, e.g., ultra-low power voltage references (Figure 4g), in which the low g d of the FGMMT would provide precision in a minimal layout.
A second FGMMT design (Figure 4h and Figure S13b, Supporting Information) takes advantage of the constant g m and low g d to allow linear addition of analog signals using two inputs, CG1 A and CG1 B in a compact design. Figure 4i illustrates μ-Si FGMMT drain current when voltages are asserted on either or both inputs, while Figure 4j depicts the results of summing two waveforms of different frequencies. As a strategy for producing decisions based on the concurrent behavior of multiple continuous signals, this approach improves on conventional designs through the low dependence on power supply fluctuations (low g d ) and the extremely compact implementation.
More generally, and with disruptive implications, the FGMMT can function as an analog/neuromorphic processing element [9] in a thin-film artificial neural network implementation. With multiple inputs, each with its own synaptic weight represented by FG charge programming, MMT neurons can readily emulate rectified linear unit (ReLU) [37] (Figure 3b,c) or logistic-like functions (Figure 3h). Powerful decision and classifier circuits could be imagined with this approach, relying entirely on energyefficient, highly linear FGMMTs with a compact layout.
In summary, we have presented a low-complexity, highly versatile new transistor structure with material agnostic operation. Its standardized fabrication process makes it well suited for integration in large-area circuits, side-by-side with conventional TFTs.
The current study is not intended as a performance benchmark. Rather, it is a demonstration, using an accessible and mature technology, of the MMT's potential. Notably, high-speed switching, constant transconductance, and immunity to drain coupling in analog FG designs complement the desirable features that make contact-controlled devices attractive: energy efficiency in saturation and tolerance to both bias stress and geometrical variability.
Immediate applications are in display and imager array compensation, and data conversion. The architecture also holds the ingredients for medium-term implementation in powerful classification and event detection for fully integrated, low-cost autonomous sensors. Uniting the presented characteristics with usual analog memory functions would confer MMT circuits the ability to retrain and "learn" at runtime, a potential to be fully realized by highly multidisciplinary cooperation in a variety of material systems.

Experimental Section
MMT Fabrication and Characterization: To demonstrate the capability of MMTs, bottom gate top contact (BGTC) devices were realized in Si using very low temperature technology (<200 C). This technology was based on microcrystalline silicon (μ-Si) [19,20] which presents 20-30 nm grain size, associated with a global crystalline fraction reaching 75%. With this low thermal budget, this technology could fit with a large range of flexible substrates and was based on plasma-enhanced chemical vapour deposition (PECVD) or inductively coupled plasma-CVD (ICP-CVD) equipment, as demonstrated in this study. ICP-CVD was capable of providing both μ-Si and oxide layers, however, the main interest of this method was to perform the CVD process at low temperature and low pressure using the huge chemical density of its plasma, without applying bias voltage. Therefore, bombing effect and voids inside layers were minimized. Devices could thus be fabricated on Si wafers, borosilicate glass, or polyimide films (e.g., kapton). In the following work, Si wafers covered by insulator had been used for practical reasons, to fit with all micro machining equipment.
The first step consisted of a 150 nm Al deposition, realized by electron beam deposition (EBD, Alliance Concept EVA-450). This layer was then patterned by photolithography and etched by Cl 2 inductively coupled plasma reactive ion etching (ICP-RIE, Corial 200IL) to create the CG1 bottom gate. This gate was then covered by a 100 nm ICP-CVD oxide layer (Corial 210D) formed using a SiH 4 /O 2 /Ar mixture at 70 C. The oxide was baked at 180 C under N 2 for 3 h to increase density and breakdown voltage. Contacts were opened by photolithography with oxide etching by CF 4 plasma (Corial 200IL). The same process was used to define a 150 nm CG2 Al gate, which was also insulated with a similar 100 nm ICP-CVD oxide layer. This second oxide was opened by CF 4 plasma etching at the location of the contacts. Following the second gate oxide, a 50 nm ICP-CVD (Corial 210D) μ-Si active layer was deposited. The μ-Si layer was formed using a SiH 4 gas precursor with Ar and H 2 at 180 C. The active layer was etched with SF 6 plasma (Corial 200IL) before being covered by a third 20 nm ICP-CVD oxide layer for the formation of a field plate at the source edge, which provides relief from the lateral electric field at the drain. [32] This field plate oxide was etched by SF 6 plasma to intentionally decrease the etching rate of oxide, and increase the interferometric etch rate control contrast with respect to the active layer. Drain and source steps consisted of a Ni deposition by EBD and patterned by lift-off in acetone, assisted by ultrasonication. The final step was a 200 nm Al EBD deposition, which was etched in Cl 2 plasma (Corial 200IL) for pads and metal path realization. An ohmic drain could be realized, but required additional processing steps.
Electrical characterization of the MMTs and FGMMTs was performed on a Wentworth probe station. Measurements were taken using a Keysight B2902A source/measure unit (SMU) controlled by Keysight Quick IV Measurement Software v.4.0.1648.5970 with an additional Weir 413D voltage source as a constant voltage supply for either CG1 or CG2, depending on which variable was being swept. For the summing FGMMT with two CG1 inputs (CG1 A and CG1 B ), two Keysight B2902A SMUs were used to supply sine waves of different frequencies on each CG1.
Measurements of Figure 1g-i were obtained from a μ-Si MMT with dimensions: W ¼ 50 μm; S ¼ 6 μm; and d ¼ 6 μm. The μ-Si MMT in Figure 3a www.advancedsciencenews.com www.advintellsyst.com All MMTs and the summing FGMMT included a 2 μm CG1/CG2 overlap; 2 μm field plate extension; and 20 nm field plate insulator. From previous studies, the field plate would be more effective if made somewhat shorter, as a proportion of the source-drain gap, and brought closer to the semiconductor surface. [32] A conservative approach was adopted in this design to promote prototyping yield.
It should be noted that the schematic cross sections and 3D drawings of MMTs in Figure 1, 2, 4, Figure S6 and S14, Supporting Information, show bottom contact, top gate (BCTG) devices. This was preferred for clarity of presentation and consistency, facilitating the comparison between the various multi-input device implementations. Naturally, the MMT could be implemented in either BCTG or BGTC configuration.
Device and Circuit Simulation: Simulations provided insight into device operation and were not intended to match the fabricated devices. Silvaco Atlas v.5.24.1.R. was used, including its mixed-mode capability for exploring circuit behavior.
We had chosen materials with known limitations to provide challenging conditions for the various studies. For example, polysilicon (poly-Si) devices would usually suffer from significant kink effect, [31] which would degrade the attainable gain, although amorphous silicon was chosen to illustrate the significant improvement in transient response. Table S1, Supporting Information, contains device geometries and parameters for all TCAD simulation studies with the majority performed using a-Si unless otherwise stated. The CG1-CG2 gap for all devices was 1 μm and overhang height was 30 nm for all simulations. For the poly-Si MMT, a source field plate was included to provide drain relief. Field plate extension and height were 0.5 μm and 20 nm, respectively. Table S2, Supporting Information, contains additional simulation parameters pertaining to the materials used. MMT and SGT devices in a-Si included 3 Â 10 20 cm À3 n-type doping at the drain. The MMT in poly-Si used intrinsic material parameters. Conventional TFTs were doped 3 Â 10 20 cm À3 n-type under both source and drain to create ohmic contacts.
Mixed-mode simulations of the switching transient of CG2, the DAC, and the low distortion amplifier circuits contain additional components or specific geometries. All devices in the CG2 switching transient study (Figure 2a-c and Figure S8, Supporting Information) have W ¼ 1 μm; S ¼ 1; d ¼ 4 μm; and t s ¼ t i ¼ 40 nm. The common source circuit configuration included R L ¼ 100 MΩ and, to aid convergence, C ¼ 1 fF.
The low distortion common source amplifier (Figure 3h,i) device width was W ¼ 100 μm. The load resistor value for t i ¼ 40 nm was R L ¼ 4 MΩ and for t i ¼ 80 nm, R L ¼ 8.5 MΩ to provide similar circuit transfer characteristics and gain.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.