Efficient Defect Identification via Oxide Memristive Crossbar Array Based Morphological Image Processing

Defect identification has been a significant task in various fields to prevent the potential problems caused by imperfection. There is great attention for developing technology to accurately extract defect information from the image using a computing system without human error. However, image analysis using conventional computing technology based on Von Neumann structure is facing bottlenecks to efficiently process the huge volume of input data at low power and high speed. Herein efficient defect identification is demonstrated via a morphological image process with minimal power consumption using an oxide transistor and a memristor‐based crossbar array that can be applied to neuromorphic computing. Using a hardware and software codesigned neuromorphic system combined with a dynamic Gaussian blur kernel operation, an enhanced defect detection performance is successfully demonstrated with about 104 times more power‐efficient computation compared to the conventional complementary metal‐oxide semiconductor (CMOS)‐based digital implementation. It is believed the back end of line (BEOL)‐compatible all‐oxide‐based memristive crossbar array provides the unique potential toward universal artificial intelligence of things (AIoT) applications where conventional hardware can hardly be used.

Defect identification has been a significant task in various fields to prevent the potential problems caused by imperfection. There is great attention for developing technology to accurately extract defect information from the image using a computing system without human error. However, image analysis using conventional computing technology based on Von Neumann structure is facing bottlenecks to efficiently process the huge volume of input data at low power and high speed. Herein efficient defect identification is demonstrated via a morphological image process with minimal power consumption using an oxide transistor and a memristor-based crossbar array that can be applied to neuromorphic computing. Using a hardware and software codesigned neuromorphic system combined with a dynamic Gaussian blur kernel operation, an enhanced defect detection performance is successfully demonstrated with about 10 4 times more power-efficient computation compared to the conventional complementary metal-oxide semiconductor (CMOS)-based digital implementation. It is believed the back end of line (BEOL)-compatible all-oxide-based memristive crossbar array provides the unique potential toward universal artificial intelligence of things (AIoT) applications where conventional hardware can hardly be used.
selectable input electric field controlled by the transistor gate without the cell-to-cell interferences. However, applications of Si-MOSFET-based 1T1R crossbar array systems are limited for the heterogeneously integrated artificial intelligence of things (AIoT) system due to the back end of line (BEOL) process incompatibility. [24,25] Although there are various alternative BEOLcompatible thin-film transistors (TFTs) such as oxide/organic TFTs that can fulfill large-area and flexible fabrication, they have yet to be demonstrated in neuromorphic system applications due to the insufficient electrical performance and poor reliability to operate the huge volume of artificial synapses in a neural network. [26] Here, to provide reliable and sufficient current-driving performance, we have used an indium (In)-rich indium zinc oxide (IZO)-based TFT [27][28][29][30] exhibiting high μ FE of 50 cm 2 (Vs) À1 as a selector that is BEOL process compatible in the memristive crossbar array. Then, hafnium oxide (HfO 2 ) [31,32] based memristors are integrated with IZO TFTs as a 1T1R pixel for the memristive crossbar array. The HfO 2 used as the active switching medium of the memristor also functions as a passivation layer of the IZO active channel; thus, the reliability of TFTs has been significantly improved without increasing the structural complexity of the 1T1R system. Moreover, the low leakage current (I OFF ) of the IZO TFT (two orders of magnitude lower than Si-TFT) in the 1T1R system can allow the potential availability for low-power computing applications requiring low leakage power consumption in unselected lines under heavy training operation.
Using the fabricated memristive crossbar array combined with a morphological image process algorithm, [33,34] we demonstrated a defect identification with about 10 4 times more power-efficient computation compared to an identical conventional central processing unit (CPU)-based process. Particularly, we complemented a unique hardware-based dynamic Gaussian blur kernel [35,36] operation with the defect identification process algorithm that allows us to vary the sigma value of a 2D Gaussian curve to precisely generate defect information. By combining neuromorphic hardware and software algorithms, we have demonstrated a power-efficient and accurate defect identification performance using morphological image processing. Successful identification performance has been confirmed by detecting the presence of defects from the various image sets, including fabric, brain tumor, graphene, and cupric oxide (CuO) thin film. Furthermore, our system is BEOL process compatible; thus, it provides the potential to be adapted in various applications that require limited fabrication conditions, including low temperature, large scale, and flexibility, which the conventional hardware cannot fulfill, toward universal AIoT applications.

Defect Detection Process
Morphological image processing is an image analysis technique that allows the detection of defects by identifying key shape characteristics while removing irrelevant background information. Through the image process, the unintentionally existing defect information can be extracted from the noisy background by thresholding the pixel intensity of the preprocessed image according to the size and shape based on the morphology. [33,34] However, the conventional morphological image operation has limitations in the perspective of accuracy because it usually only uses a single filter for the background segmentation process. Figure 1a schematically illustrates a flowchart of the conventional morphological image process (left) and our process (right). In the preprocessing stage, the input image was adjusted by applying denoising operations and by converting the full-color image into binary data. To achieve further accurate defect information, we used an averaging operation in addition to the conventional process by applying 3 Â 3 dynamic Gaussian blur kernels as filters. We applied nine types of Gaussian blur kernels with a sigma value ranging from 0.7 to 1.1 using the programable memristive crossbar array. Weight values of each pixel in a Gaussian blur kernel was discretized into integers between 1 and 64 to match the available programing resolution of fabricated memristors that is discussed in a later section, as shown in Figure 1b. By performing the matrix convolution of a converted image with each kernel, nine denoised images were acquired. Then, to distinguish the defects from the background, the binarization process was subsequently performed by applying a threshold on the grayscale images through Otsu's algorithm. [37] Following the preprocess stage described previously, we used the morphological image operations for defect identification. Detection of the defect areas can be achieved through a morphological image process via matrix multiplication of pixel information of the target image and a structuring element. [34] The structuring element is a diamond-shaped disk matrix consisting of 0s and 1s (shown in Figure 1a) that allows us to remove any details or regions smaller than the size of it through matrix multiplication. The results of this process confirm the existence of defects regardless of the shape and size of the defective area by varying the structuring matrix and the type of morphological operation. Specifically, we have used the morphological operations of dilation, erosion, opening, and closing, which are commonly used in defect detection (see Experimental Section and Supporting Information Note 2). The combination of these mathematical operations with the application of structuring elements can be used to identify defects from the images. The erosion and dilation operations are processed using kernel convolutions [38] via Boolean operations of XOR and. Here, we have used memristors to implement binary state kernels as the structuring elements to perform the erosion and dilation operations. Two types of diamond-shaped disks (shown in Figure 1a) were used as structuring elements. Figure 1c shows a comparison of the estimated power consumption of performing inference mode kernel operations with analog and digital implementations using the fabricated 1T1R system and a hypothetical digital circuit, respectively. Figure S1, Supporting Information, shows the approximated power consumption of the morphological image process using kernel operations with structuring elements for the analog and digital implementations. The kernel operation can be computed based on the multiply-accumulate (MAC) operation with a matrix convolution process. The digital implementation has been modeled as a system executing a sequential programming code using CPU and dynamic random-access memory. Then, we calculated the total CPU cycles required for MAC operation for each kernel by multiplying the basic unit cycle. For the analog implementation, we assumed the 1T1R memristive crossbar array based system operates at 1 MHz, output memristor current of 1 μA at low V G , and input V read of 0.2 V. The structuring element, realized by binary states of the memristor corresponding to the input voltage, was applied to each pixel of the image to process vector-matrix convolution for the MAC operation. Particularly, the digital-to-analog conversion (DAC) and multibit analog-to-digital conversion (ADC) units are not required for both cases because the kernel operations only have digital inputs and binarized outputs. As a result, the approximated inference mode power consumption shows that our memristive crossbar array based analog system enables about 10 4 times more power-efficient computing than conventional digital-circuit-based computing, regardless of the disk size, due to its computing-in memory architecture. [39] (See in Figure S1, Supporting Information, for details.) In the postprocessing stage, an averaging schema was used to improve identification accuracy. The element-wise-averaging method [40] was used to combine the distributed intensity of extracted binary images using the following equation: where I i is ith image matrix, and n is the number of detected distributions. Figure 1b shows the process example of the fabric defect detected by the previously described method using the fabricated memristive crossbar array combined with software operation. We have applied the kernel operation using nine types of dynamic Gaussian blur kernels with varied sigma values ranging from 0.7 to 1.1 to the input image. (The sigma values higher than 1.1 have shown no significant difference in the output for the application of defect detection with the given size of our kernel.) The individual pixel weight value of kernels was discretized by 6 bits of information through the 1T1R memristor array. To program the kernel to the targeted sigma value, each pixel of the memristive crossbar array was set by a calibrated input voltage. Each output processed through programmed kernels with varied sigma values shows defect information. The segmentation process removes uninformative variations, and then the output is combined to provide an averaged value. The nine outputs processed by the blur kernels using the fabricated memristor array are shown in Figure 1d. Figure 1e shows the comparison of identified defects processed by conventional means and our method, respectively. The result Figure 1. Scheme of the defect identification process. a) Schematic flowcharts of the conventional morphological image process (left) and our process (right). Our process consists of a preprocessing stage where the input image is processed by using a dynamic Gaussian blur kernel, a defect detection stage using morphological operations, and a postprocessing stage where the results are processed via an averaging schema that provides a gradient image of the defects. b) Dynamic Gaussian blur kernels with various sigma values, discretized into integers between 1 and 64. c) Schematic diagrams of analog (above) and digital (below) implementation performed using a fabricated 1T1R system and a hypothetical digital circuit, respectively. d) The nine outputs generated from the processes with nine types of Gaussian blur kernels. e) Comparison of detected defects processed by the conventional process (left) and our process (right).
processed by conventional operation using a fixed sigma value of 0.7 was insufficient to provide accurate defect information due to the difficulty in extracting the defective area from the background. In contrast, the defect information more effectively reconstructed the defect information using multiple sigma values by updating the weight value of each memristor in the array. The extracted grayscale output image in Figure 1e exhibits the defect information.

Structural and Electrical Properties of the 1T1R Pixel
To precisely modulate the resistance of individual memristors in the array for the kernel operation in the defect detection process, we fabricated a 1T1R memristive crossbar array. The 1T1R pixel in the crossbar array consists of a series connection of an IZO TFT and a HfO 2 memristor. The optical microscope image of the 5 Â 5 1T1R pixel array integrated on a sapphire substrate is shown in Figure 2a. All pixels are interconnected as a matrix in the array to operate parallel convolution computing. To enhance the driving current through the oxide TFT, we applied an interdigitated design [41] of the source (S)/drain (D) electrodes with the channel width/length (W/L) ratio of 50/5 (see zoomed scanning electron microscope (SEM) image of Figure 2a). The pixels in the same row share the gate electrodes of TFTs, while the parallel column lines connect the top electrode (TE) and bottom electrode (BE) of each memristor, respectively. Figure 2b schematically illustrates the device structure of the fabricated 1T1R single pixel. The IZO oxide TFT was designed as an inverted staggered structure [42] with an Al 2 O 3 gate insulator and a bottom-gate electrode. A 5 nm thick HfO 2 layer was deposited simultaneously using the atomic layer deposition (ALD) process on top of both the IZO TFT back-channel and the 25 nm Pt/3 nm Ti BE as a passivation layer and as an active medium of the memristor, respectively. As shown in the inset of Figure 2b, the HfO 2 layer covered on the IZO back-channel can effectively prevent the oxygen-related atomic diffusion that can cause degradation issues in oxide semiconductors. In this structure, the Pt/Ti is used as a common electrode which forms the drain contact of the IZO TFT and the BE of the HfO 2 memristor in series. The current compliance of the memristor is controlled by the applied gate voltage of the connected IZO TFT to precisely tune the weight values of the memristor. Figure 2c shows the transfer characteristics (drain current (I D ) versus gate voltage (V G ) measured at drain voltages (V D ) of 0.1 and 1 V) of the single IZO TFT. To enhance the carrier mobility, we deposited the In-rich IZO (In 2 O 3 -10 wt% ZnO) as the active channel layer of the n-type oxide TFT by using a DC magnetron sputter at room temperature. As shown in the inset of Figure 2c, the IZO TFT exhibited high μ FE of 50 cm 2 (Vs) À1 at V D of 0.1 V, which is approximately five times higher than that of commonly used oxide TFTs based on an indium gallium zinc oxide (IGZO) [43] and zinc oxide (ZnO) [23] TFTs. The 1T1R system based on such oxide semiconductors can hardly operate the memristor due to its insufficient driving current. [23,43] The IZO TFT shows high enough I D of 0.1 to 10 mA at V D of 1 V depending on V G ranging from À5 to 10 V, which is sufficiently high to program the resistance of the HfO 2 memristor. Furthermore, the IZO TFT shows a low subthreshold gate swing, an enhancement mode threshold voltage (V th ), and a low off-current (I OFF ) of 0.15 V dec À1 , 0.8 V, and %10 À13 A, respectively. (details are shown in Supporting Information Note 1) In particular, transformation of the TFT property from the depletion mode to enhancement mode was achieved by applying O 2 plasma treatment on the back channel of the IZO active layer to effectively compensate for the free electrons that are unintentionally generated from the In-rich composition of IZOs (see Experimental Section and Figure S2, Supporting Information).
The current-voltage characteristics of a HfO 2 memristor fabricated on top of the Pt/Ti drain electrode of the TFT is shown in Figure 2d. Before measurement, an electroforming process was performed to obtain reliable bipolar resistive switching behavior of memristors by applying a 5 V DC bias to the TE of Ta as shown in the dotted line of Figure 2d. The electroforming in oxide-based memristors is driven by induced conducting paths via migration of oxygen atoms. [44,45] The fabricated memristor exhibited a typical resistive switching I-V behavior, where the device is switched from a high-resistance state (HRS) to a low-resistance state (LRS) by applying a positive bias over the SET voltage (V SET ). The programmed LRS is retained during the voltage sweep back in a negative direction and switched to the HRS by applying the RESET voltage (V RESET ).
Moreover, the HfO 2 oxide layer coated on top of the TFT channel significantly improves the reliability of the oxide TFT. The external bias stress and ambient air conditions usually cause the conductance instabilities of oxide TFTs. [46,47] Under the bias stress conditions with constant V G and V D to turn on the transistor, an oxide TFT's performance is generally degraded by the gate electric field induced chemical reaction between ambient air and the back-channel surface of an oxide semiconductor. Especially, the degradation becomes more serious in a highmobility oxide channel such as IZO. [47] Therefore, an effective passivation layer for the stable operation of an oxide TFT is essential to protect the chemical reaction and to precisely control the conductance state of a 1T1R system. In the 1T1R system, the 5 nm thick HfO 2 acts as the passivation layer to protect the back-channel surface of the IZO TFT as well as the active layer of the memristor. To confirm the effectiveness of HfO 2 passivation, the DC bias stress induced I D degradation characteristic of the fabricated IZO TFT with and without the HfO 2 protecting layer was measured under ambient air conditions at the positive bias stress conditions (V G and V D were set to 10 and 1 V, respectively, at room temperature, and the stress duration was 10 4 s), as shown in Figure 2e. As the stress time increased, the I D level of the IZO TFT without the HfO 2 passivation layer continuously degraded over two orders of magnitude, whereas the degradation behavior was dramatically improved by using the HfO 2 passivation layer to cover the back-channel surface of the oxide TFT. The measured results clearly indicate that the HfO 2 layer could enhance the stability of oxide TFTs.
The I-V characteristic of the 1T1R system, consisting of the HfO 2 memristor and IZO TFT in series, was measured under the application of 10 V gate bias, as shown in Figure 2f. The electroforming process was performed by doing a DC bias sweep from À3 to 3 V of the TE of the memristor (V mem ) before the measurement, as shown in inset curve of Figure 2f. The current flow to the memristor (I mem ) in the 1T1R pixel at the forwardbiased regime is controlled by the driving current of the IZO www.advancedsciencenews.com www.advintellsyst.com TFT tuned via V G . The measured I mem of the 1T1R system shows the I-V loop with two branches corresponding to the HRS and the LRS of the memristor, indicating that the fabricated IZO TFTs provide sufficient current to set the conductance of the connected memristor. To examine the repeatability of the 1T1R system, multiple cycling measurements were implemented. The I-V characteristics of the 1T1R pixel showed uniform SET and RESET operations during repeated DC voltage sweep cycles from À3 to 3 V of V mem with a fixed V G of 10 V (see Figure S3a, Supporting Information). Figure 2g shows the histogram of the SET and RESET voltage obtained from the I-V curves of the 200 repetitive switching cycles. The statistical study of the SET and RESET voltage on the 1T1R pixel exhibited a general Gaussian distribution with a standard deviation sigma of 0.2 at 2.35 and À2.25 V, respectively, indicating a uniform operation. As shown in Figure S3b, Supporting www.advancedsciencenews.com www.advintellsyst.com Information, we also used endurance-cycling performance test with AC voltage pulses (500 ns width with fixed V G of 2 V for SET, À2 V for RESET, and a read voltage of 0.2 V) for 10 3 cycles. The variation of HRS and LRS was consistent without remarkable degradation during the switching cycles. In addition, we demonstrated the I-V measurement of the 1T1R consisting of the bias-stressed IZO TFT without the HfO 2 layer to examine the effect of the HfO 2 passivation layer, as shown in Figure 2h. The electrical behavior of the 1T1R with the HfO 2 -passivated TFTs was well preserved, showing the typical switching curve after 10 4 s bias stress time. However, in case of the 1T1R system with unpassivated TFTs, the memristor could not be completely reset after electroforming due to the degraded field effect mobility of the active layer.

Gate-Induced Current Modulation toward Kernel Operation
We have experimentally demonstrated precise control over the resistance state of the individual memristor in the 1T1R crossbar array by using the gate-induced current modulation of the integrated TFTs. Figure 3a shows I D -V G curves of the 1T1R pixel at a reading voltage of 0.2 V along with the resistance states set by V G of the IZO TFT. Before the demonstration, the resistances of the memristor were programmed by set and reset processes with the IZO TFT using target V G of 10 and 2 V. The I D curve indicates distinct programmable current states of the HRS at V G of 10 V and LRSs at V G of 10 and 2 V, respectively. As the I OFF of the fabricated IZO TFT is lower than 10 À12 A, the oxide-based 1T1R system is capable of providing a wide operation window of programable weight values. The low leakage power consumption of oxide TFTs also makes it suitable for a wide range of low-power applications. The demonstrated all-oxide-based 1T1R system allows a hundred times more power-efficient computing compared to a Si-TFT-based system for the applications due to the low I OFF and the high energy efficiency, which is even more effective when the size of the crossbar is large along with the heavy training operation (see Figure S4, Supporting Information). To confirm the feasibility of the current modulation of the oxide-based 1T1R system, we demonstrated continuous electrical tuning of the current states as shown in Figure 3b. By driving the IZO TFT with V G ranging from the subthreshold to the high-electric-field regime (2-10 V), we were able to precisely select and modulate the 64 current levels (6 bits) through the memristor. Therefore, the on-off current ratio window of %10 3 was achieved via the gate-induced modulation. The discretized current levels exhibited linearity over the applied V G regime, as shown in Figure 3c. The linearly modulated behavior confirms that the resistance state of the memristor can be accurately tuned by an IZO TFT for dynamic kernel operation used in this work for the defect identification. Furthermore, analog switching behavior was demonstrated by applying electrical pulses, similar to the weight update of biological synapses through potentiation and depression. [48,49] Figure 3d-f shows the incremental weight update characteristics of a fabricated 1T1R pixel measured by applying potentiation (rising) and depression (falling) pulses. We have applied both constant and incremental external bias pulse schemes to demonstrate the incrementally updated resistance properties of a 1T1R pixel. As shown in Figure 3d, the constant pulse scheme is a pulse sequence with a fixed set voltage in amplitude and frequency, while the incremental pulse scheme uses progressively increasing set voltage amplitudes at a fixed frequency. [48] The current value was monitored with a 0.2 V read pulse after each set or reset pulse. As shown in Figure 3e, when the constant pulse with 2 V amplitude and 500 ns width was applied, the current levels abruptly changed during both potentiation and depression processes. By contrast, the current levels changed almost linearly during weight updates when applying incremental bias pulses with 150 consecutive positive and negative pulses changed from 1.8 to 2 V and from À1.9 to À2.1 V, respectively, indicative of an ideal analog switching behavior as shown in Figure 3f. Furthermore, the gate-induced current modulation technique enables us to precisely tune the weight value window of the 1T1R device through the compliance current controlled by applying V G of TFTs ranging from 2 to 10 V. The linear weight value update behaviors indicate that our 1T1R system based on oxide TFTs is a promising candidate for an electronic synapse for future analog computing applications that require a BEOL-compatible process.
For the demonstration of dynamic Gaussian blur kernel, we fabricated a 3 Â 3 1T1R memristive crossbar array. Figure 3g shows the fabricated 3 Â 3 1T1R array connected in series with IZO TFTs and HfO 2 memristors ( Figure S5, Supporting Information, shows the I-V curves of all pixels in the array). To implement the dynamic Gaussian blur kernel operation, each pixel of the array was programmed by applying a targeted input V G . Figure 3h shows one of the Gaussian blur kernels with a sigma value of 1.1 under reset and set conditions. The bottom graph of Figure 3h exhibits the measured current values of the 3 Â 3 array based on the 64 linearly discretized states. As shown in the graph, the target current states could be precisely selected by set V G with narrow distribution that allows accurate kernel operation. Figure 3i shows the in situ monitoring of the 1T1R array programming process, while measurement was performed with fixed read V D and V G of 0.2 and 5 V, respectively. Unit memristors in each pixel were programmed to the distinct resistive states for the target kernel operation using the biasing history described in Figure 3h. The read current, which is the accumulated current value obtained from each unit pixel's TE line, was increased stepwise and followed the used time domain bias scheme. This operation can be effectively expressed as the convolution process based on Ohm's law for vector-matrix multiplication and Kirchhoff 's current law for summation. [50] This characteristic confirms the feasibility of the all-oxide-based memristive crossbar array for analog computing.

Demonstrations of the Defect Identification Process
We demonstrated the image filtering process via dynamic Gaussian blur kernel operation for the defect identification using the fabricated memristive crossbar array. To demonstrate the nine types of 3 Â 3 Gaussian blur kernels varied by the sigma value, we simulated and measured the kernel maps based on the 6 bits programmed current states ranging from 10 À7 to 10 À4 A, as shown in Figure 4a. The nine types of Gaussian www.advancedsciencenews.com www.advintellsyst.com kernels mapped by the experimental readout current matrix accurately matched with the targeted sigma values of the simulated kernels ( Figure S6, Supporting Information, shows all the experimental readout currents of kernels). Precisely tuned weight values of the blur kernel based on a memristor array confirmed the resistance modulation performance of the fabricated oxide-based 1T1R system for accurate kernel operation. We also demonstrated a 5 Â 5 diamond-shaped disk consisting of binary components using the on and off operation of the 1T1R array for the linear opening and closing process, as shown in Figure 4b, showing a precise operation similar to the simulated matrix. Figure 4c shows the processed output results, extracted from each processing step of the used defect identification process using the memristive crossbar array. The input image of a fabric was filtered by a Gaussian blur kernel to distinguish the defective pattern from the background. The tunable kernels with multiple www.advancedsciencenews.com www.advintellsyst.com sigma values (here, ranging from 0.7 to 1.1) allow us to effectively distinguish the defect information from the background pattern. Then, the image was binarized by applying the thresholding process. The defect area was identified by implementing the morphological image process of dilation and erosion. This process was repeated using nine types of Gaussian blur kernels to yield nine outputs. Following, an element-wise-averaging method was applied to www.advancedsciencenews.com www.advintellsyst.com reconstruct a single complete defect image from these nine outputs.
Our technique can be universally applied to various fields where defect identification is critical. To confirm the generality of the process, we have applied an identical computing process using a memristive crossbar array to medical and microscopic images as well. Figure 4d shows the processed images of brain tumor, [7] skin cancer (called melanoma), [51] chemical vapor deposition (CVD)-grown graphene, [52] and a CuO thin film [53] using the fabricated oxide-based 1T1R memristive crossbar system ( Figure S7, Supporting Information, shows the nine different single output images generated from each demonstration). The processed output images from the various inputs display the identified defect information. These demonstrations indicate that a morphological process using memristive crossbar arrays can be effectively used for various applications, including those in industry, science, and medical areas.

Conclusion
In summary, we have demonstrated efficient defect identification using a morphological image process with low power consumption via a memristive crossbar array. The memristive crossbar array consists of 1T1R pixels fabricated with an In-rich IZO TFT and a HfO 2 memristor. The 1T1R system allows us to modulate the resistance of individual memristors in the array without cell-to-cell interference. The HfO 2 layer is used as the passivation layer for the oxide TFT channel to improve the reliability of IZO TFTs while it serves as an active switching medium of the memristor. Using the fabricated memristive crossbar array system, we have demonstrated defect identification via an analog computation process with lower power consumption compared to digital computation. To generate precise defect information, we have used additional pre-and postimage processing steps using unique hardware-based dynamic Gaussian blur kernels that allow us to extract accurate defect shapes with the gradient pixel information. Based on the approaches, we have successfully demonstrated the defect identification process using images excerpted from various fields including a fabric, brain cancer, CVD-grown graphene, and CuO thin film. We believe that the BEOL-compatible all-oxide-based memristive crossbar array provides a unique opportunity for neuromorphic hardware toward universal AIoT applications, including defect identification, where conventional hardware cannot be easily used.

Experimental Section
Fabrication of 1T1R Pixel Array: The 1T1R array was composed of IZO transistors and a HfO 2 memristor. The cross-section structure of the IZO transistor and Ti/Pt/HfO 2 /Ta fabricated on a sapphire substrate is shown in Figure 2b. Although a sapphire substrate was used for an academic research purpose in this work, the device can be achieved on various substrates, including silicon and glass, without issues due to the high process compatibility of oxide-based semiconductors. For the fabrication of the IZO transistor, the Ti/Au back gate electrode (5/100 nm) was deposited by an e-beam evaporator. Then, a 100 nm thick Al 2 O 3 film as a gate insulator was deposited on the patterned gate metal by ALD. Subsequentially, a 10 nm thick IZO thin film as a channel layer was formed by using DC-magnetron sputtering of In-rich IZO target (In 2 O 3 -10 wt% ZnO; the atomic percentage values of the indium, zinc, and oxygen were 29.01%, 13.74%, and 57.25%, respectively) with a deposition rate of 0.2 nm s À1 , where the gas volume ratio of [O 2 ]/[Ar þ O 2 ] was fixed to 0.2, followed by an annealing process at 250 o C for 1 h in an oven, and the channel layer was defined via photolithography and wet etching process by using a buffered oxide etchant (BOE). After the channel patterning, O 2 plasma treatment for the IZO film was performed at 200 W for 30 s to compensate for the exceeded oxygen vacancy. The 5/25 nm thick Ti/Pt was deposited as source and drain contacts of the transistor and BEs of the memristor by e-beam evaporation. Following the metallization, the 5 nm HfO 2 thin layer was formed by ALD, working as a passivation layer of transistor channel and switching medium for the memristor. The switching area was isolated from the passivation area via photolithography and wet etching process using BOE. Then, a 50 nm Ta metal as a TE of the memristor was formed via DC-magnetron sputtering and lift-off, forming a cross-junction.
Electrical Measurement: The DC electrical performance of the IZO transistor, HfO 2 memristor, and 1T1R array was characterized by using a Keysight B1500A Semiconductor Analyzer. The analog behaviors of the memristor and 1T1R array were measured using the Keysight B1500A, a pulse generator (Keysight 33600A), a transimpedance amplifier (Edmund 59-179), and an oscilloscope (Keysight DSOX3024T). The analog behavior of the 1T1R pixel was characterized using a pulsed signal with two types of bias schemes. The constant pulse modulation was performed at a fixed drain voltage of the transistor at AE2 V. On the other hand, the incremental pulse modulation was performed with linearly increasing drain voltage (with 150 consecutive positive and negative pulses changed from 1.8 to 2 V and from À1.9 to À2.1 V, respectively) for set and reset processes, respectively. All pulse modulation measurements were processed under a gate bias ranging from 2 to 10 V and at a fixed read voltage of 0.2 V.
Defect Detection Algorithm: This algorithm was used to detect defects used in this work.
Algorithm. Defect identification process using dynamic Gaussian blur kernels, morphological image process, and averaging schema. Initialize image and convert to grayscale. Initiate array of sigma values.
Calculate the discretized Gaussian blur kernels using 64 states using the sigma values. Initialize structuring elements SE 1 and SE 2 for the morphological process