In‐Depth Analysis of One Selector–One Resistor Crossbar Array for Its Writing and Reading Operations for Hardware Neural Network with Finite Wire Resistance

This work provides a comprehensive analytical analysis of one‐selector‐one‐resistor (1S1R) crossbar array (CBA) device for hardware neural network (HNN) applications. Simplified analytical device models are prepared from a particular 1S1R device to validate the analysis. The read margin (RM) analysis results show that the V/3 voltage scheme and reduced selector leakage are necessary to maximize the RM and maximum operable size N of the CBA, where N indicates the number of wires (word line or bit line). The write margin (WM) analysis results show that the unwanted switching of the unselected cell during the write operation is unlikely in the 1S1R CBA even with a large N value, despite a voltage drop along the interconnection wire. The analysis of simultaneous multiply‐and‐accumulate operations is conducted using the analytical method to examine the influence of voltage drop according to the wire and memory cells in HNN applications. Reducing the wire resistance and on‐state conductance increases the available N value when the selector operates near the threshold conditions. The proposed analytical model can estimate the maximum accuracy degradation of the HNN through the involvement of the unintentional voltage drop.


Introduction
Modern artificial intelligence (AI) systems using neural network (NN) structures have shown remarkable performance in various tasks from image recognition [1][2][3] to human-beating gameplay. [4,5] A crucial contributor to this recent success is DOI: 10.1002/aisy.202100174 This work provides a comprehensive analytical analysis of one-selector-oneresistor (1S1R) crossbar array (CBA) device for hardware neural network (HNN) applications. Simplified analytical device models are prepared from a particular 1S1R device to validate the analysis. The read margin (RM) analysis results show that the V/3 voltage scheme and reduced selector leakage are necessary to maximize the RM and maximum operable size N of the CBA, where N indicates the number of wires (word line or bit line). The write margin (WM) analysis results show that the unwanted switching of the unselected cell during the write operation is unlikely in the 1S1R CBA even with a large N value, despite a voltage drop along the interconnection wire. The analysis of simultaneous multiply-andaccumulate operations is conducted using the analytical method to examine the influence of voltage drop according to the wire and memory cells in HNN applications. Reducing the wire resistance and on-state conductance increases the available N value when the selector operates near the threshold conditions. The proposed analytical model can estimate the maximum accuracy degradation of the HNN through the involvement of the unintentional voltage drop.
of the ReRAM cell is much higher than the sum of the wire resistances, which diminishes the urgent requirement of an analytical model. However, as the integration density, or CBA size, increases and the critical dimension decreases, the numerical simulation of the circuits takes considerable time. In addition, there can be cases in which the operating current is quite high, as for the filamentary-type ReRAM cell, where the IR drop becomes even more serious. If such an IR drop is not addressed appropriately, the output current can deviate significantly from the correct value during the inference step. In several cases, even unwanted switching can occur during the training step. The highly nonlinear current-voltage (I-V ) characteristics of the selector devices render the experimental results deviating from the simple calculations based on Ohm's law and Kirchhoff 's law.
Several studies have reported the IR drop effects for a feasible operation of ReRAM CBA with selection devices, [23,30] but none of them have estimated these adverse effects (IR drop and selector nonlinearity) simultaneously in a quantitative manner. In addition, these issues have been discussed for applying ReRAM-based CBA to the standard memory, where only a few WLs and BLs are selected and biased. However, they become even more serious when a large-sized CBA is used for HNN applications. This is because the MAC operations in HNN require the simultaneous application of bias voltages, even with different values, at different lines. This results in an even higher IR drop, which can incur an even reversed current flow along the selected path, which seriously undermines the HNN accuracy.
This work provides two critical improvements in this regard. First, an analytical model that calculates the read margin (RM) and write margin (WM) of 1S1R CBA is presented. This reveals the relation between material factors and the maximum operable size of 1S1R CBA. Second, an analytical circuit model is provided, which accurately calculates the deviation of the cell bias voltage from the desired value during the worst-case MAC operations, where different voltages are simultaneously applied to all WLs. This model elucidates the crucial design factors that should be considered when fabricating 1S1R CBA for HNN applications.

Single-Cell RM of 1S1R CBA for Write-and-Verify Scheme
Before discussing the array-level circuit models, the I-V models of the 1S1R device are defined as follows where i 1S1R ðV 1S1R Þ indicates the voltage-dependent current and V 1S1R indicates the voltage applied to the entire 1S1R device. V th is a threshold voltage that corresponds to a specific V 1S1R over which 1S1R shows a useful memory window. When V 1S1R is lower (higher) than V th , the selector (memory) determines i 1S1R ðV 1S1R Þ. For the selector-dominant case, the I-V relation (i 1S1R ðV 1S1R Þ) can be represented by ae bV , where a and b are appropriate constants, with dimensions of current and 1/V, respectively. For the memory-dominant case, i 1S1R ðV 1S1R Þ can be approximated as G Ã ðV À V th Þ, assuming a linear I-V relation for ReRAM, where G Ã is the conductance of ReRAM in the 1S1R device. To represent the multiple conductance levels of ReRAM, G Ã is set as an available conductance of ReRAM. For example, ReRAM with two levels, G Ã , has G 0 and G 1 as the high-and low-resistance state, respectively. ReRAM with four levels, G Ã , has G 0 , G 1/3 , G 2/3 , and G 1 , where G 1/3 and G 2/3 are the intermediate levels between G 0 and G 1 ( When the exponential I-V relation of the 1S device is approximated by a linear function, the following equation can be used. Equation (2) assumes that the selector has a constant conductance G S , where G S << G 0 < G 1 . This work fundamentally assumes offline training and inference, meaning that the memory cell is programmed to the desired weight value following the previously calculated values by software-based simulation. In this case, write-and-verify and cell initialization may be required, depending on the switching mechanism of the ReRAM device. Therefore, only the selected cell within the given CBA must be accessed during the training step (cell writing and reading). In contrast, the simultaneous access of many cells sharing BLs is required during the inference step.
The success of these operations depends on the adopted voltage scheme and CBA size (numbers of WLs and BLs). Note that the same number of WLs and BLs, which is referred to as N, is most effective in suppressing the unwanted sneak current issue. [24] Therefore, this work assumes that N 2 is the total number of memory cells in a CBA and examines the material parameters and optimized voltage scheme to maximize the N value while ensuring the desired operations.
Among the voltage schemes used for the single-cell readout, the floating scheme is selected to investigate how other material factors and circuit designs affect the correctness of the readout. In the floating scheme, floated wires work as a sneak current path, making the readout current deviate from the correct value. [24] The topology of the circuit with possible current paths is shown in Figure 1a. The conductance of the farthest cell from the WL/BL sources (gray cell in Figure 1a) is set to G 0 , and it was attempted to read it to examine the worst case in the floating scheme. The other cells are set as G 1 , maximizing the sneak current. [30] The amount of sneak current is much higher for CBA with ReRAM only (1R CBA) than that for 1S1R CBA. The circuit shown in Figure 1a can be converted into the equivalent circuit shown in Figure 1b, which facilitates the sneak current calculation. For simplicity, no wire resistance is assumed in this case. As shown in Figure 1b, the sneak current of 1 R CBA with the floating scheme is calculated, as shown in Equation (3).
where V s is the voltage applied to WL #1 in Figure 1a. The actual V s is determined to apply the read voltage (V 1R ) to the selected cell. Because no wire resistance is assumed, V s has the same value as V 1R . The RM, defined in Equation (4), is used to estimate the correctness of the readout.
where RM indicates the ratio of the ideal readout current I read,0 , which is free from any spurious effects, including the IR drop and sneak current, other than the value determined by the cell conductance, and the measured readout current I read compared with the specified target current I M . For a two-level ReRAM cell, For a multilevel ReRAM cell, however, it can be the median value of the two neighboring states. For I read ¼ I read,0 , RM ¼ 1, but for the large sneak current, RM approaches 0. In this work, the minimum level of RM is set to 0.1 for a reasonable read operation. From I read,0 ¼ G 0 V 1R and I read ¼ I sneak þ I read,0 , Equation (4) can be rewritten as Equation (5) using the material parameters (G 0 , G 1 ) and circuit design factors (N, I M ).
The analysis in Equation (5) shows that 1R CBA is operable only when N ≤ 2, which means that 1R CBA is impractical, as explained next. For I M ¼ (G 0 þ G 1 )V 1R /2, irrespective of how high the memory window is (G 1 ≫ G 0 ), RM becomes 1 À ðNÀ1Þ 2 NÀ0. 5 . This indicates that the maximum N for a positive RM value is less than 2. Therefore, a selector is inevitable to read a cell state in a CBA irrespective of how small N is.
A similar analysis can be performed for a 1S1R CBA. For this analysis, it is assumed that the high voltage is applied to the selected cell only, so jV 1S1R j > jV th j, whereas all other cells are subjected to low voltage, so jV 1S1R j < jV th j. To apply the desired read voltage V 1S1R to the selected cell, a voltage V s having the same value as V 1S1R is applied to WL #1 in Figure 1a. Under this circumstance, the 1S1R CBA circuit can be converted to the equivalent circuit shown in Figure 1c. Using Figure 1c and the model i 1S1R ðV 1S1R Þ, two equations for the forward-bias V f and reverse-bias V r applied to the 1S1R cells can be built as Equation (6) and (7).
Equation (6) represents Kirchhoff 's voltage law (KVL) through the sneak current path, and Equation (7) shows Kirchhoff 's current law through all sneak current paths, whose schematic diagrams are shown in Figure 1d. Equation (8) and (9) can be derived from Equation (6) and (7), respectively, to determine the unique values of V f and V r for the given material parameters (a f , a r , b f , and b r ) and N.
Using Equation (8) and (9), the RM and maximum N of 1S1R CBA can be written as Equation (10)- (12). www.advancedsciencenews.com www.advintellsyst.com Equation (11) is a rearrangement of Equation (10) to relate N to the given design factors. Equation (12) is the approximated version of Equation (11) when N ≫ 1, showing the independence between N and V f . This approximation originates from the condition that V r > 0, which justifies the presence of the reversebiased cell irrespective of how large the value of N is. This condition requires that the upper bound of V f should be V S /2.
Using Equation (10)- (12), the relation between N and other design factors can be determined. One example is the number of weights per cell (or possible level numbers). Accommodating more data per cell helps maximize the data density and fast MAC operation; however, the gap between the current values of the neighboring states decreases. When a 1S1R device has a total number of linearly split P states, discerning a specific G l from its neighbor G l þ G 1 ÀG 0 PÀ1 is required. This requirement From this, Equation (12) can be rewritten as Equation (13).
Equation (13) indicates that aggressive current scaling is necessary for the multilevel 1S1R CBA to be used in HNN. For example, 1S1R CBA for ternary HNN (P ¼ 3) can accommodate halved N compared with its binary (P ¼ 2) case when the other design factors are the same.
Meanwhile, a similar method can be applied to other voltage schemes, such as the V/n scheme (n ¼ 2, 3). Under this scheme, the sneak current originates from the electrical sources at WL #2 to #N, which can be effectively suppressed when jV th j > j V s n j. Because the total sneak current is ðN À 1Þa f e b f Vs n , RM and N of the V/n scheme can be expressed as Equation (14) and (15), respectively.
The forms of RM and N of the two schemes differ only in the voltage term in the exponent. The comparison between the floating and V/n schemes for the RMs can be found in Equation (16) and (17).
When the floating and V/2 schemes are compared using Equation (16), the RM of the floating scheme is always higher for a given N. Equation (17) shows the upper and lower bounds of the ratio of the RMs between the floating scheme and V/3 scheme, where the upper and lower bounds are determined from Equation (16) and minimum of Equation (8) with N ¼ 2, respectively. The lower bound of Equation (17) shows that the RM of the V/3 scheme mostly exceeds that of the floating scheme. For example, adopting the selector device with symmetric I-V (a f ¼ a r , b f ¼ b r ) makes the lower bound 1. For a particular asymmetric selector, the lower bound of the ratio can be smaller than 1. However, increasing V f for a large N increases the RM ratio, whose upper bound is determined by Equation (17). These analyses show that the V/3 scheme becomes more desirable for the CBA with a larger N for a given RM.
The proposed model was compared with the numerically simulated RM using the HSPICE package to validate the abovementioned analytical RM model. All numerical simulations were based on the experimental I-V curve of the 1S1R device, as shown in Figure 2a. The 1S1R device was fabricated with the HfO 2 -based resistive switching layer and TiO 2 -based nonlinear selector, the details of which are included in the online Supporting Information (SI). The 1S1R device sets and resets in the negative-and positive-bias regions, respectively. Four levels of conductance values were obtained by varying Curve of analytical 1S1R model when |V 1S1R | < |V th |. a f and b f are defined at V 1S1R < 0, and a r and b r are defined at V 1S1R > 0.
www.advancedsciencenews.com www.advintellsyst.com the maximum reset voltage during the reset sweep in the positive-bias direction. In Figure 2a, the thin lines indicate the experimental data, and the thick lines indicate the curves obtained from the numerical model. In the negative-bias region, The nonlinear portion of the I-V curve at À1.3 V < V 1S1R < À0.6 V was fit using i 1S1R % ae bV 1S1R with the parameters shown in Figure 2c for the forward and reverse biases. The linear I-V model of 1R can be constructed with the identical conductance values shown in Figure 2b but with no involvement of V th . Figure 3a shows the calculated RM from the analytical and numerical models with three different voltage schemes. The conductance of the selected cell was set to G 0 , and its current was read, where the read current must follow the black curve shown in Figure 2a if the sneak current effect is minimized. As mentioned previously, the V/3 scheme shows the largest RM compared with the other voltage schemes for the given design factors, suggesting that the V/3 scheme should be used to accurately determine the read current from a larger CBA.
Four virtual numerical models with different selector parameters were built to evaluate the relation between RM and the leakage current of the selector. For these numerical simulations, the parameter that determines the selector leakage current of the original numerical model was varied, and the dotted I-V curves in Figure 3b correspond to the numerical simulation results. Then, the analytical model was used to fit the numerical curves for jV 1S1R j < jV th j by varying the a and b values, whose appropriate values are included in the inset table in Figure 3b. The required applied voltage to WL #1 (V s ) is different for different cases to match the magnitude of the readout current. Figure 3c shows that the calculated RM values from both the analytical and numerical models match well, demonstrating the analytical model's accuracy. The device with a higher leakage current (or larger a f ) has a smaller N value while guaranteeing the desired RM for the given design factors. The relation between a f and N can be explained mathematically by the partial derivative ∂N ∂a f ¼ ÀðN À 1Þ V s n , which can be derived from Equation (14). This value is always negative for all combinations of N, V s , and n, suggesting that the increased sneak current reduces the RM even when a small V s is used. In addition, although decreasing the a f may enhance the RM, a larger V s is required to ensure a sufficient read current, which is necessary for the rapid readout. Therefore, there is an inevitable tradeoff between the achievable RM and the involved energy consumption when modulating the selector parameters.
Three other virtual numerical models with different current variations were built to evaluate the relation between RM and the current variation of the selector. Although the device variation modeling is complicated, the variation of RM can be predicted, and it can be used to control the nonidealities of the 1S1R device and CBA. The detailed simulation methods and results are included in the online Supporting Information.

Single-Cell WM of 1S1R CBA for Write-and-Verify Scheme
The IR drop becomes a much more severe problem for write access. Even single-cell access can be a problem because ReRAM requires a higher operating current during writing than reading. The probable write failure originates from the fact that the V s of the WL connecting the selected cell should be increased to apply the desired switching voltage (V w ) to the selected cell. The difference between V s and V w originates from the IR drop over the wires. When the V s is too large, a bias applied to the unselected cell (ΔV us ) also increases, and if it exceeds the switching voltage (V sw ) of the unselected cell, the cell undergoes unwanted switching. WM can be defined as Equation (18). [30] WM ¼ jV sw j À jΔV us j jV w j When ΔV us approaches V sw , WM approaches 0. To analyze the WM quantitatively, the nonselected cell representing the worst-case circumstance should be focused on. The position of the worst-case unselected cell and the type of V sw depend on the type of voltage scheme used. [23] In this work, the same weight mapping method is used for the RM evaluation case and floating voltage scheme. Under this circumstance, the selected cell is supposed to be set, and the cell at the intersection of WL #N and BL #1 (coordinate (N,1)) is most vulnerable to the unwanted reset switching. [30] Therefore, V w , V sw , and ΔV us correspond to the set voltage, reset voltage, and applied voltage to the cell at coordinate (N,1), respectively. Without the IR drop, the weight mapping and voltage scheme for this circumstance is the same as the settings for Equation (9). ΔV us is the same as V r in Equation (9). ΔV us can be expressed as follows.
It can be understood that ΔV us "decreases" as N increases, which means that the unwanted reset switching becomes less likely with an increasing value of N. The primary reason for the unwanted switching originates from the IR drop, which will be discussed later. When the IR drop is ignored, the worst-case The worst case appears when N ¼ 2 and a f ¼ a r , which correspond to the minimum CBA size and selector with symmetric low-voltage current. Appropriate tuning of b f and b r by adopting an asymmetric selector can decrease the ΔV us ; however, this can increase the risk of an unwanted set of unselected cells during reset switching of the selected cell. As both set and reset switchings are required for an appropriate circuit operation, careful tunings of both b f and b r are required.
When the IR drop exists, V s in Equation (19) must be increased to apply the desired V w value to the selected cell. The process of IR drop calculation used in this work is explained as follows. First, the currents that contribute to the write path are calculated under the r cc ¼ 0 condition, where r cc indicates the wire resistance between the neighboring memory cells. The calculated currents are cumulated to the wire components in the writing path to achieve the final IR drop. The writing path is indicated in Figure 1a by the red arrow. The cell that is supposed to switch (gray cell in Figure 1a) passes a current of G 0 ðV s À V th Þ and contributes to the IR drop through 2N wires, yielding an IR drop of 2Nr cc G 0 ðV s À V th Þ. The other cells (orange and yellow cells in Figure 1a) pass a sneak current of a f e b f V f , where V f is precalculated using Equation (8). The amount of contribution of each cell connected to the writing path depends on its position. Combining the contribution from the selected cell and all unselected cells, a new V 0 s can be derived as follows.
Substituting Equation (20) into Equation (19) results in Equation (21), which can be used to estimate ΔV us by taking into account the IR drop.
Equation (21) indicates that ΔV us will have a minimum value with an increasing value of N, because the increase in V 0 s is proportional to that in the N 2 term shown in Equation (20), which has a more significant influence than the logðNÞ term shown in Equation (21).
To validate the proposed WM model, it was compared with the numerically simulated WM using HSPICE. The settings for all simulations were the same as those for the RM simulations. r cc is set as 0.5 Ω, which is sufficiently large to examine the IR droprelated problems. The r cc is dependent on the type of metal and its thickness. [23,30,31] The set and reset voltages of the 1S1R device were set as À2.8 and 1.8 V, respectively, as determined from the I-V data shown in Figure 2a. Figure 4b shows the variation in the required V s to apply the set voltage of À2.8 V to the selected cell (gray cell in Figure 1a), calculated by both the proposed analytical model (line) and the corresponding numerical model (red squares). The coincidence between the two results validates the proposed analytical model. Figure 4c shows the variation in ΔV us with increasing N (and accompanying V s increment in Figure 4b), calculated using both analytical (line) and numerical (red squares) models. The variation shows the minimum point as expected. This effect originates from the competence between the sneak current effect (decreasing ΔV us ), represented by Equation (19), and increasing V s effect (increasing ΔV us ), represented by Equation (20). As observed, the maximum ΔV us is only %0.53 V, which is much lower than the reset voltage of 1.8 V, even up to N ¼ 1000. Therefore, sufficient WM can be secured under these conditions.

Sneak Current in Fully Biased 1S1R CBA Considering HNN Applications
In the previous discussion, the read and write functions were assumed to be conducted in a cell-by-cell manner, which is appropriate for a standard memory operation and minimizing the IR drop effect. However, this is not the case for inferencing in HNN, where the read voltages must simultaneously be applied to multiple WLs to accomplish the MAC operation. The inference can be accelerated by reading currents through multiple BLs, representing the sum of the multiplications of inputs and optimized weight values. In this case, the IR drop along the wires becomes more serious as the total current increases, which deteriorates the inference accuracy of HNN and even fails the HNN operation if it becomes too large. An analytical model that can calculate the voltage distribution and current flow across the entire 1S1R CBA for such a circumstance is introduced in this section. A representative circumstance is shown in Figure 5a, where the number 5 images are taken as the input. Most images have different intensities of the input signals in each pixel. When an image is converted into a 1D input vector, as shown in the right portion of Figure 5a, the input intensities  Figure 5b shows the worst-case example of the voltage application. In this case, a large voltage V w , representing the intense signal of the input pixel, is applied to WL #2 to #N, while a small voltage V s , representing the background of the input image, is applied to WL #1. V w increases the potential of BL at nodes far from the BL voltage sources (ground). Under this circumstance, the voltages of the cells connected to WL #1 are severely distorted, and the cell at the intersection of WL #1 and BL #N (gray cell at the lower-right corner in Figure 5b) experiences the highest distortion. The distortion can be modeled using the design parameters, including wire resistance, and the model can be used to improve the performance of the CBA-based HNN by optimizing the circuit parameters.
The analytical model used for such circumstances is first settled in 1R CBA to simplify the problem, which is impractical, as stated in the RM analysis section. Then, the analysis is extended to the 1S1R CBA case, which is practical. In this analysis, the current passing through the cell intersecting WL #M and BL #N is defined as I M,N , and all these values are solved using the sets of KVL equations, as shown in Equation (22) and (23).
V s À r cc ðI 1,1 þ I 1,2 þ : : : þ I 1,N Þ À I 1,1 G 1 À r cc ðNI 1,1 þ ðN À 1ÞI 2,1 þ : : : þ 1I N,1 Þ ¼ O Equation (22) represents the KVL of the current path from WL #1 to BL #1, indicated by the red arrow in Figure 5b. Along this path, the sources of the IR drop are the memory cells and wire slices, that is, the term r cc ðI 1,1 þ I 1,2 þ : : : þ I 1,N Þ represents the IR drop through the single WL slice connecting the WL #1 source and top of the cell between WL #1 and BL #1. The term r cc NI 1,1 represents the total IR drop along the entire BL #1 induced by I 1,1 . The term r cc ðN À 1ÞI 2,1 represents the IR drop along the (NÀ1) slices of BL #1 induced by I 2,1 and so on.
Equation (23) is an N-by-1 matrix expression of Equation (22), representing the KVL of all current paths that start from the WL #1 source. For example, the second and last terms of Equation (23) represent the KVL of the path from WL #1 to BL #2 (the green arrow in Figure 5b) and #N (the blue arrow in Figure 5b), respectively. The term X k is an N-by-1 vector, which comprises I k,1 , I k,2 , : : : I k,N ; V s is an N-by-1 vector that comprises only V s ; I is an N-by-N identity matrix; A is an N-by-N matrix defined as A ij ¼ minði, jÞ, representing the IR drop through the WL slices; and O is an N-by-1 zero vector. As mentioned above, all ReRAM cells are assumed to be at G 1 for the worst-case IR drop and calculation simplicity. Other matrix equations for all current paths that start from www.advancedsciencenews.com www.advintellsyst.com the other WLs can be constructed similarly as Equation (24) and (25).
Equation (24) and (25) represent the KVL of all current paths that start from WL #2 and WL #N sources, respectively. Solving the N matrix equations, including Equation (23)- (25), results in the new equation of X N using X 1 , and plugging the approximated solution of X N to the new equation, renders the new equation represented by X 1 without involving X 2 , : : : X N . After that, the desired ΔV 1,N , which is the voltage across the selected cell, can be achieved by dividing X 1 by G 1 . If the calculated ΔV 1,N < 0, the current passing through the cell is reversed, which should be avoided.
The process of deriving ΔV 1,N in the analytic form is explained in detail in the online Supporting Information. The final form of ΔV 1,N is shown in Equation (26).
The term ΔV 1,N for 1S1R CBA under the same circumstance can be derived similarly, considering the nonlinear conductance of the 1S1R device. As all cells in the CBA are applied with a voltage close to the read voltage, the i L,1S1R ðV 1S1R Þ model in Equation (2) is used to reflect the selector behavior near the read voltage. It is assumed that a high V 1S1R voltage with jV 1S1R j > jV th j is applied to the cells intersecting WL #1, whereas www.advancedsciencenews.com www.advintellsyst.com a lower V 1S1R voltage with jV 1S1R j < jV th j is applied to all other cells. These assumptions can be justified by the fact that V s has a smaller magnitude than V w , and V s is sufficiently close to the V th shown in Equation (2). The final form of ΔV 1,N of 1S1R CBA is expressed as follows.
where g ¼ G s G 1 , and all values and functions are equivalent to their counterparts of Equation (26) and (27). The detailed derivation processes of Equation (28) are included in the online Supporting Information.
To validate the calculated ΔV 1,N from Equation (26) and (28), ΔV 1,N was compared with the numerically simulated ΔV 1,N using the HSPICE package. For these calculations, the necessary I-V curves for the 1S1R and 1R devices were depicted by the thick line and dashed line curves, respectively, in Figure 5c. The analytical model was prepared by setting the resistance of 1R to induce the current value of the numerical 1S1R model in Figure 2a. This model was also used for the numerical simulation of 1R CBA. In the case of 1S1R CBA, the analytical model was prepared using Equation (2) with the given parameters. The ReRAM-dominant region was prepared similarly to the analytical 1R model, and the selector-dominant region was represented as G s ¼ 0.01G 1 . For the numerical simulation of 1S1R CBA, the numerical model in Figure 2a was used. Figure 5d,e shows the ΔV 1,N obtained by the calculations performed out using the analytical and numerical models in 1R CBA and 1S1R CBA cases, respectively. Both figures validate the proposed analytical models. In the case of 1R CBA, ΔV 1,N increases from the settled negative V s values (À0.05, À0.1, and À0.2 V) toward the positive values as N increases. When the V s values are À0.05 and À0.1 V, the ΔV 1,N value becomes even positive when N > 60 and 110, respectively. The reversed sign of ΔV 1,N indicates that the read current cannot be flown into the sensing circuit, suggesting a serious malfunction of the circuit.
In the case of 1S1R CBA, however, no such voltage sign reversal is observed for all tested V s values up to N ¼ 200, as shown in Figure 5e. This finding demonstrates the importance of adopting the appropriate selector again. The magnitude of ΔV 1,N variation is similar for both 1R and 1S1R CBA up to N ¼ 200 and decreases with a decrease in V s .
Changing the factors in Equation (26) and (28) reveals how they affect the deviation of ΔV 1,N from the intended value. The most crucial factor is kð¼ ffiffiffiffiffiffiffiffiffiffiffi r cc G 1 p Þ, which frequently appears in both equations. The functional form of k indicates that decreasing the wire resistance and G 1 have similar significance in determining the IR drop. Figure 6a,b shows the relation between N and ΔV 1,N in 1R CBA and 1S1R CBA, respectively. For these calculations, the G 1 and k values included in the inset table of Figure 5c are used. Given the limitation that r cc should be decided by the material of metal wire and design rule, it is convenient to control G 1 to suppress the undesirable IR drop effect.
It can be understood that decreasing G 1 of the ReRAM device is highly beneficial to avoid the increase in ΔV 1,N . However, there can be a limitation of the achievable range of G 1 , depending on the specific ReRAM type. Figure 6c shows ΔV 1,N À V s as a function of N with different b f values of i 1S1R , and a list of b f values is shown in the inset table in Figure 6c. It is expected that ΔV 1,N À V s ¼ 0, when V 1S1R is applied with no circuit artifacts. Under the adverse circuit effect, such as r cc , however, ΔV 1,N becomes smaller than V s . Note that the appropriate V s varies with b f to render the read current identical among 1S1R models with varying b f , as mentioned in the previous section.
The shape of ΔV 1,N À V s graph is independent of the selection of b f when jV 1S1R j > jV th j. This is because the selector parameter, b f , plays a role only for jV 1S1R j < jV th j. For jV 1S1R j > jV th j, the circuit current should be governed by the memory cell and not the selector. Figure 6d shows the variation in ΔV 1,N calculated by Equation (28) when varying the value of G s (thick lines). It also shows that ΔV 1,N becomes similar to the numerical simulation results (black square data) as G s decreases, demonstrating the accuracy of the analytical model. Note that varying the conductance values of 1S and 1R results in an opposite influence on the voltage behavior.
The ΔV 1,N model can be used to quantitatively understand how the design parameter affects the performance of CBA-based HNN, although it can be conjectured that increasing r cc deteriorates the accuracy of the programmed HNN. The next section describes how this model can be used to estimate the accuracy of the MAC operation in the CBA-based HNN.

Application of Analytical ΔV 1,N Model
To demonstrate the usefulness of the analysis, two single-layer CBAs with 196 and 324 WLs, respectively (left and right panels of Figure 7a), were assumed, both of which were programmed with externally trained weights for the Modified National Institute of Standards and Technology Database (MNIST) dataset identification. As the MNIST dataset has only ten classes, the CBA with 196-by-10 or 324-by-10 sizes should be used for the single-layer HNN. However, the developed analytical model assumes N-by-N CBA, so the assumed CBA had a square shape, as shown in Figure 7a. To accommodate the discrepancy, the trained weight values were programmed at the farthest positions (BL #187 to #196 for the former and BL #315 to #324 for the latter) from the WL voltage source, as shown in Figure 7a, which shows the maximum influences of the IR drop and sneak current. In this case, all unprogrammed cells (sharing the BL #1 to #186 for the former and BL #1 to #314 for the latter) were assumed to have the lowest conductance (G 0 ), where the four levels of conductance (G 0 , G 1/3 , G 2/3 , and G 1 in Figure 2b) were selected for the trained weight values.
After that, the HNN inference was simulated using HSPICE with different r cc values to monitor the test accuracy. Figure 7b shows the simulated test accuracy of HNN with the programmed weights in Figure 7a for the different r cc values. When r cc (or k) is zero, the test accuracy is %84% and 87% for the 196 and 324 WL cases, respectively. These values are not sufficiently high because only a single-layer HNN structure is adopted. However, this study focuses on examining the r cc effect, and thus, only the degradation of this value is significant in this study. When r cc increases to %0.3Ω for G 0 of 1.21 Â 10 À5 S (k % 2 Â 10 À3 ), the test accuracy deteriorates significantly by %5%. For these simulations, all input vectors have different V w and V s values in each case, making the quantitative analysis of allowable N complicated and the related understanding difficult.
Therefore, the analytical model for calculating ΔV 1,N discussed in the previous section was used under the assumption that V w ¼ À2.2 V, V s ¼ À1.7 V, and G 0 ¼ 1.038 Â 10 À5 S. This is the worst-case calculation; as such unfavorable WL voltage application rarely occurs. Figure 7c shows the variation in ΔV 1,N as a function of k, where ΔV 1,N is %0.03 V when k % 2 Â 10 À3 , the value at which the accuracy degrades by %5%, as shown in Figure 7b. Therefore, ΔV 1,N of 0.03 V can be used as a criterion for CBA to efficiently conduct the MAC operation without involving a significant performance degradation. Figure 7d,e shows the variation in N with increasing r cc for the different values of G 0 of the memory cell and G s of the selector, respectively, indicated in each figure, when ΔV 1,N is 0.03 V. Figure 7d shows that N > 100 requires r cc < 0.7 Ω for all G 0 values smaller than %10 À5 S, demonstrating www.advancedsciencenews.com www.advintellsyst.com the importance of a low IR drop again. Figure 7e shows that to not hamper the performance improvement by decreasing the memory cell conductance, G s should be <0.1G 0 . It also indicates that the G s influence does not significantly vary once it becomes <0.05G 0 . By comparing the maximum N obtained from the WM and RM of a single cell, the fully biased RM becomes the sizelimiting factor of 1S1R CBA. Other HNN test accuracy analyses were conducted by changing G 0 and b of the 1S1R model. The ΔV 1,N model verifies that the relation between HNN test accuracy and G 0 is equivalent to that between test accuracy and r cc . The ΔV 1,N model can also explain the independence between the test accuracy and b. The detailed simulation methods and results are included in the Supporting Information.

Conclusion
This work presents an analytical circuit model for CBA with a high N value (>100) for an efficient evaluation of the device parameters on the training and inference performances of an HNN composed of 1S1R bipolar ReRAM cells. For offline training, the optimized weight values, represented by the conductance of the ReRAM cell, calculated in the software using backpropagation, are programmed through the write-and-verify method. In this method, evaluations of the WM and RM are necessary for a device model of 1S1R and the given wire resistance. The CBA composed of only 1R memory cells cannot provide any meaningful WM or RM due to the severe interference caused by the unwanted switching and high sneak current. In contrast, 1S1R provides useful device performance, especially when the V/3 scheme is used. In general, a higher source voltage is necessary to render the selected cell voltage reach the desired value when a voltage drop occurs along the wires due to their finite resistance. Interestingly, the WM increases with N because of the higher voltage drop across the wires, which practically decreases the magnitude of the unwanted reverse voltage at the unselected cell, despite the increased source voltage. Therefore, the write-and-verify method can practically be used for weight assignment in a CBA-based HNN.
The concurrent application of the input voltages to all WLs at the inference stage for MAC operation makes the analytical modeling of the CBA-based HNN extremely challenging. Such a problem becomes even more severe as the N value increases beyond 100, rendering the numerical simulation using HSPICE impractical. An analytical model can be used to solve the voltage . b) Simulated test accuracy of the single-layer HNN with weights in (a). G 0 ¼ 1.0384 Â 10 À5 is assumed for the plotting. c) Calculated ΔV 1,N of fully biased 1S1R CBA G 0 ¼ 1.0384 Â 10 À5 and V w ¼ À2.2 V, showing the voltage deviation by different r cc values. d) Calculated maximum N using ΔV 1,N ¼ À1.67V (0.03 V margin) and G s ¼ 0.01G 0 as a function of r cc for different G 0 values. e) Calculated maximum N using ΔV 1,N ¼ À1.67V (0.03 V margin) and G 0 ¼ 1.0384 Â 10 À5 as a function of r cc for different G s values.
www.advancedsciencenews.com www.advintellsyst.com equation at the worst node of the CBA under the given bias condition. Because of the finite voltage drop over the wires, even a reverse bias can be applied to the worst-case node, which severely interferes with the accurate inference. The 1S1R-type device is mandatory in this regard, and lower wire resistance and cell conductance values further help the precise estimation of the sum of the output currents in the CBA with high N numbers. A quantitative analysis of the unwanted voltage effect in the worst-case voltage applications reveals that r cc < 0.7 Ω for a reasonable memory cell conductance of %10 À5 S is required to secure the accurate operation of CBA with N > 100.

Numerical Simulation Method
HSPICE was used as an analog circuit simulator to implement a numerical simulation of the 1S1R device. In the simulator, the numerical simulation of the 1S1R device was expressed as a serial combination of the ReRAM model and selector model. The ReRAM model comprises a single nonlinear resistor to represent the high-range voltage where the memory window appears. The selector model comprises multiple nonlinear resistors to represent the low-and midrange voltages of the 1S1R device. The ReRAM model has a state parameter whose value is set between 0 and 1 to express the intermediate states of the 1S1R model. Curve fitting was conducted in order of selector model and ReRAM model to the numerical simulation to mimic the measurement data in Figure 2a. Two numerical 1S1R models were developed to represent positive-and negative-biased devices, respectively.
The training process of optimized weights for offline HNN training is included in the online Supporting Information.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.