Back-End CMOS Compatible and Flexible Ferroelectric Memories for Neuromorphic Computing and Adaptive Sensing

hungry analog-to-digital or reverse signal conversion in the edge computing devices and lead the way toward realization of a truly bioinspired intelligent systems.

communicate with each other through a sequence and timing of spikes, enabling them to process time-series data. [14] In SNNs, the synapses between two firing neurons show long-term change in weights when the two connecting neurons fire relatively quickly. This long-term potentiation (LTP) or depression (LTD) of synaptic weights, i.e., increase or decrease in conductivity, respectively, emulate the spike-timing-dependent plasticity (STDP) [15,16] that is used for supervised or unsupervised learning. Therefore, realization of neuromorphic computing hardware requires development of nanoelectronic devices that are able to emulate the functions of biological synapses and neurons. [17] Emerging memory devices with analog conductance states, low-voltage operation, fast switching, and possibility of dense integration provides essential features needed for the successful implementation in neuromorphic chips. Recent years saw a significant surge in reports of both two-terminal (2T) and three-terminal (3T) memory devices that can emulate various synaptic functions. [18][19][20] 2T memories such as oxide memristors, phase-change memories (PCMs), ferroelectric tunnel junctions (FTJs), and magnetic tunnel junctions (MTJs) [21,22] and 3T devices including electrochemical transistors, ferroelectric fieldeffect transistors (FeFETs), and charge-trapping transistors showed promising performance as artificial synapses. [17,[22][23][24] Undoubtedly, the advantage of 2T devices arises from their reduced footprints, whereas the 3T devices provide a larger switching ratio, better control of analog conductance states, and improved cell selection within a crossbar array. While considering emulation of the neuronal functionalities for the neural networks, volatile memristors, PCMs, threshold switching devices, FTJs, and FeFETs have shown promising features. [25][26][27][28][29][30] So far, the functions of biological synapses and neurons are successfully demonstrated in individual memory devices or small-scale proof-of-concept arrays; however, their large-scale implementations, needed for real-world applications, are still missing. Several combinations of CMOS with memristive devices have been intensely investigated over recent years. [31][32][33] Broadly, these results indicate that for efficient online network training in hardware, in addition to abovementioned conditions, high linearity in synaptic weight update [11,34] in response to programming pulses as well as endurance of 10 9 cycles or more is essential for continuous set-reset operations of the synapses and integrate-andfire neurons. [5] Other essential features required are: 1) a wide resistance window for accurate continuous learning and multiple distinguishable states, [35] 2) fast training and low-noise retention of conductance for maximizing the network throughput, [36] 3) low programming and standby power [37] to enable sensory information processing for long times even in limited-energy environments, and 4) integration possibility with CMOS processes. [11] These criteria are in accordance with the International Roadmap for Devices and Systems for "Beyond CMOS" memory and information processing. [38] Since the first experimental demonstration of memristor concept, significant amount of work has been done to explore the potential of these devices in mimicking neurobiological sensory data processing tasks. Most of these efforts were concentrated on binary metal oxide 2T resistive random access memories (RRAMs) where conducting filament formation between the two electrodes under electric field determines the device on and off states. Also, electrochemical memories (CBRAM), PCMs, and spin-based memories, like MTJs, have been studied extensively. [17,24,39] All different devices have certain aspects that are promising for energy-efficient in-memory-computing (IMC) architecture. However, most of these devices have a significant off current that makes them more power hungry, even while in standby mode and small resistive switching ratio (R on/off ) or eventual drift of conductance states are challenging. From the energy efficiency, fast operation, and stable data retention perspective, ferroelectric (FE) memory devices can offer unparalleled advantages over RRAMs and PCMs. [20,40,41] Additionally, FeFETs can offer wide conductance window and high bit resolution, properties that are conducive to high-accuracy online learning. Although FE random access memories (FeRAMs), composed of one transistor one capacitor structures (1T1C), is an established technology, implementation of FE-based nonvolatile memories (NVMs) in embedded systems is impeded by the demanding process parameters like high temperature and need for certain lattice-matched substrates for epitaxial growth of the perovskite oxides. Also, maintaining ferroelectricity down to nanometer thickness scale in these conventional perovskite oxide FEs is often challenging that resulted in devices with thicker layer with a high operating voltage (>10 V). Additionally, large footprint of the capacitors is unsuitable for dense integration and destructive readout requires frequent programming. Ongoing development of high-quality, ultrathin FE films and possible low-voltage operation has revitalized the prospect of FE devices in NVM technology landscape in recent years. [42][43][44] For FE-based neuromorphic systems, simulation based on ultralow current FTJ crossbar arrays predicted power efficiencies better than 150 Tera operations per second per watt (TOPS W À1 ) for image classification using a trained ANN [37] while in state-of-the-art oxide RRAMs energy efficiency of 187.62 Giga operations per second per watt (GOPS W À1 ) is reported. [31] The main reason for this enormous difference is that FE devices are voltage-driven instead of current-driven operations like RRAM components. FE components, therefore, offer exciting possibilities for integration into larger-scale memory and IMC arrays.
For application in electronic industry, an important requirement for a material of choice is the CMOS process compatibility. CMOS integration of electronic components and circuits allows monolithic fabrication of devices and circuits that produces a standalone chip, reducing the power loss at the interconnects, yielding more reliable interconnections, and helps minimize the parasitic losses by placing the device components in close proximity. In addition, integrated devices minimize lateral area requirement and unit device cost. As a CMOS compatible FE, doped HfO 2 has already gained considerable attention in recent years. [45,46] However, the high crystallization temperature of the ultrathin films of most doped HfO 2 materials is still a challenge for their integration in post-CMOS processes. In addition, requirement of certain electrodes for proper crystallization of doped HfO 2 poses restriction on the choice of electrode materials. Also, limited endurance and endurance-retention compromise are issues that require further research. Another class of potentially CMOS postprocessing compatible FE materials is the FE polymers. Most studied FE polymers, in terms of memories, are polyvinylidene fluoride (PVDF) and its copolymer polyvinylidene fluoride-trifluoroethylene (PVDF-TrFE). These polymers have been used in post-CMOS processes for MEMS and other piezoresponse applications. [47,48] However, their true potential for CMOS postprocessed FE memory components in neural networks has not been considered and explored yet. For heterogeneous CMOS integration or transferred freestanding device stacks on flexible substrates, perovskite FE devices based on BaTiO 3 (BTO), Pb 1-x Zr x TiO 3 (PZT), LiNbO 3 (LNO) or SrBaTiO 3 (SBT), etc. can offer exciting properties. [49] However, wafer scale, high-quality perovskite oxide FEs are still far from reality and their environmental impact is an issue of concern.
Another field of research, that is gaining tremendous interest in recent years, is smart and adaptive sensing for edge computing. [32,50] Sensing technology has become integral part of our everyday lives with high emphasis on flexible, wearable, and biodegradable technologies. [51][52][53] With the onset of internet of everything (IOE), billions of internet-connected sensors are causing unprecedented amount of data flow to the cloud servers. Processing of this continuous flow of data is challenging and rather unsustainable for the current cloud-based computing platforms. Additionally, continuous data trafficking is a major source of large electrical power consumption that makes the edge devices unviable for operating at limited power environments. Data privacy and security is another additional concern. Computing on or near sensor [54][55][56][57] is therefore the next target for overcoming these challenges. Sensors with embedded memory and IMC would provide the opportunity for data analysis already at the sensor chips and only selected data will be sent to the cloud for further processing. Figure 1 shows the current computational schemes used for edge intelligence and the need for alternate approaches for energy and time-efficient, secure computing and sensing schemes. FE materials can play a big role in this data-driven industry by integrating both sensing and memory functionalities in the same device architecture. [58,59] The current review gives an overview of these two research topics. After this introduction to the field of neuromorphic computing hardware and adaptive sensing, the article will discuss the state-of-the-art of various electronic and ionic devices with required functionalities, advantages and challenges of the FE components, restriction on choice of materials imposed by CMOS BEOL process parameters and flexible and wearable substrate compatibility, material physics of oxides and polymer FE, device physics of 2T FTJs and 3T FeFETs, application of oxide and polymer FTJs and FeFETs in NVM, synapses and neurons, application in DNN, SNNs, circuit integration issues, wafer scale homogeneity and CMOS back-end integration, and finally ending with a future perspective and outlook on the topics.

State-of-the-Art of Emerging Memories
In Table 1, some of the most promising emerging NVM technologies are compared in terms of the required performance matrices like R on/off , switch speed, endurance, retention, write voltage, linearity in weight update, suitability for DNN or SNN applications, etc. with the mainstream CMOS memories. Some data are adapted from refs. [17,60]. For an ideal forward-inference network, a large range of linearity and symmetrically programmable conductance states is preferred. This can ensure blind synaptic weight update during learning and can efficiently perform parallel vector matrix multiplication (VMM). Long data retention time is not always an essential condition, but is preferred in many applications, for instance, train-once inference-only applications require long-term data storage onchip. High endurance and fast operation speeds are essential requirements for most computational tasks. Low power operation and reliability of the programmed states are always preferred. The Figure 1. a) Schematic illustration of the data communication bottleneck faced by conventional computing schemes with the proposed idea of adding intelligence to the edge devices that will perform basic cognitive tasks already at the sensor node, significantly reducing the data overflow to the cloud servers. b) Computing-in-memory in memristive crossbar arrays where each cross section is a memory element capable of storing the information and perform VMM operation through change in conductance states by programmable ferroelectric polarization rotation. c) Capability of FE devices to do analog computation through controllable domain dynamics using cumulative nature of the programming pulses of different magnitude, duration, or interval. For a programming pulse of magnitude higher than the synaptic threshold voltage, a time invariance in output pulses is obtained, as each input pulse turns the device from off to on state, resulting in only postsynaptic amplitude modulation. However, when operated with subthreshold pulses, accumulation of multiple pulses can generate one output pulse, leading to both postsynaptic amplitude and frequency modulation.
reported results indicate that, with current state-of-the-art performance level, no single memory technology is capable of fulfilling all the requirements for IMC tasks. Therefore, based on the most critical functionality for a specific application, different emerging technology solutions can be considered. Nonvolatile nature of the FE polarization makes the FE memories one of the key material for NVMs. Also, the technology has the potential to reach some of the key performance indices (KPIs) indicated in the IRDS, especially the fast operation, high endurance, and possibility for dense integration. Additionally, analog conductance from multidomain FE devices and accumulative nature of switching makes them attractive for both DNN and SNN applications.

Advantages and Challenges of the FE Components
In addition to the above mentioned advantages of fast and energyefficient operation of FE components, there are several other advantages that the FE memories possess that make them attractive. Major advantages include 1) forming free operation, 2) controllable intermediate states through gradual polarization reversal, 3) designing nonvolatile or volatile functionality in the same device through custom-engineered depolarizing field, [29] 4) possibility of adding pressure and temperature sensing property in the memory element using piezo-and pyroelectric properties of the FE, [57] 5) operation stability over a wide temperature range (from 4 K -Curie point of the FE), [61] and under harsh radiation conditions. [62] Other than these, 6) low-temperature processability, structural flexibility, and low production cost of the polymer FE memories make them attractive for smart and adaptive wearable device applications. Additionally, 7) piezo-and triboelectric properties of FE materials can be utilized to generate power from human motion making them self-sustainable systems. [57] However, there are some challenges that need to be overcome for realizing the full potential of these components. 1) Devices at nanoscale: Scaling down and dense integration of NVM components with FE materials converts the device operation from multidomain to single-or few-domain FE phase. Attaining and preserving the intermediate resistance states, arising from coexisting up and down polarized FE domains, is challenging to control in single-or few-domain limit. This affects the achievable number of analog synaptic weight states (bit resolution) leading to loss of classification accuracy. In the later sections of the article, it has been discussed how innovative material and interface engineering together with customized pulsing schemes could circumvent the problem. Also, for densely packed crossbars, FTJs are needed to be scaled drastically that results in low tunneling current and could subsequently increase read noise and readout time. One promising approach in this case could be the 3D vertical stacking of FTJs instead of their aggressive downscaling. 2) High spontaneous and remnant polarization at low voltage range: Most of the earlier studies reported on few hundreds of nm thick FE films where the threshold voltage (V th ) clearly exceeded tens of volts. For minimizing the size of the access transistors on the CMOS chip, it is essential to decrease the drive voltage to less than 3.3 V (for 180 nm technology node). In order to have a FE devices operating at less than 3.3 V or even less, clearly the thickness of the FE layer needs to be in the order of tens of nm or less where interface and pinhole effects can become significant. In order to avoid large gate leakage due to thin FE films, an additional dielectric can be useful, either as a separate layer or as a blend in the polymer FE film. Obviously, an important consideration in this case will be to maintain the effect of FE polarization as much as possible. 3) Energy-speed trade-off: The switching energy and time of the FE domains are inversely proportional and therefore choice of low voltage drive transistors in the CMOS circuit restricts the possibility of highspeed operation of the devices. A trade-off between the parameters Table 1. Comparison of key performance matrices of the CMOS mainstream and emerging memory devices for their implementation in neuromorphic computing hardware. Adapted with permission. [60] Copyright 2020, The Author(s). Published by MDPI, open access Creative Common CC BY license. More detailed data on 2T FTJs are in Table 2 and 3T FeFETs in Table 3  is essential. Some feasible routes to overcome these challenges are discussed in the following sections of the review.

Materials for CMOS BEOL and Flexible Substrate Compatibility
Reported data on FE memories are mostly focused on either perovskite oxide FEs, such as BTO, BiFeO 3 , PbTiO 3 , PZT, etc. or more recently on the doped HfO 2 -based memories. Recent reports showed the promising behavior of polymer FE P(VDF-TrFE)-based electronic synapses and neurons, operating at nanosecond timescales. [63][64][65][66][67] However, before converting them to a technologically matured solution, more research needs to be done, especially at the memory array level. For the doped-HfO 2 based FE memories, majority of reported materials and devices employed a high-temperature rapid thermal annealing to attain the noncentrosymmetric orthorhombic polar phase. [68][69][70] Although for a short time, this high-temperature annealing poses limitation on these materials for integrating in CMOS BEOL processes. However, recently a few studies found that it is possible to bring down the thermal annealing temperature of doped HfO 2 [46,71,72] or even making it annealing-free [73] without compromising their FE properties through implementation of proper growth processes or electrode materials. This review mainly focuses on those results with occasional mentions of high-temperature processes that is compatible with CMOS front-end-of-line (FEOL) or heterogeneous integration. It is important to mention here that oxide perovskite FE devices using PZT, BTO, SBT, etc. have been used on flexible substrates as well, either in form of suspended nanoparticles in PVDF matrix or as transferred freestanding films. [49] These oxides, with their robust FE properties, are definitely promising for certain applications. However, wafer scale uniformity from these complex oxides has not been achieved yet. For flexible and wearable smart systems, P(VDF-TrFE)-based devices are still an excellent choice where under extreme bending and folding conditions devices can perform without any degradation or fatigue and are therefore promising for wearable smart systems and prosthetics. [74]

Origin of Ferroelectricity and Domain Dynamics
The origin of ferroelectricity in doped HfO 2 -and PVDF-based copolymers has been discussed in detail in the literature. [46,75] Here, the polarization switching and relaxation mechanism together with the FE domain dynamics are discussed briefly for correlating the subsequent synaptic and neuronal functionalities of these devices with their transient switching dynamics.
Ferroelectricity arises due to presence of a net electric polarization in certain class of dielectric materials. This net polarization can be controlled and tuned under application of an electric field of certain polarity. The net polarization in a FE material is a nonlinear function of electric field. When an electric field is applied on a FE material, above a certain field value, the material shows a sudden increase in its net polarization. This field is known as the coercive field (E C ). Above E C , the material reaches its saturation polarization (P s ) value. When the applied field is withdrawn, the net polarization is maintained at a nonzero value, called the remnant polarization (P r ). On reversing the polarity of the applied field, the polarization direction rotates to the opposite direction and reaches the negative P s value. P r , P s , and E C are the characteristic parameters for a certain material. During the electric field cycling of a FE material, if the applied field is enough to saturate the polarization, the P-V hysteresis loop opening is broader and the loop is called a FE major loop. However, when the applied field is not enough to saturate the net polarization, the P-V hysteresis loop opening narrows down giving rise to a minor loop. The major and minor loop characteristics are important for designing stable analog operation of the FE memories and can be controlled utilizing a custom-programming scheme. [65] Also, the polarization retention is more stable when a FE major loop is obtained; therefore, a nonvolatile or a volatile memory performance can be expected based on the applied field strength to program a device. Minor loop operation is often associated with irreproducibility owing to randomness of microscopic domain switching and the "history effect," [76] i.e., previous history of electric field cycling on the device, which can impact training accuracy of neural networks. Instead of continuous weight update, a full erase method before programming is able to recover the accuracy, however, at the cost of additional energy and latency. From material and device perspective, a dielectric capping layer for the FE, i.e., a linear voltage regulator in series with a nonlinear one, can improve the abruptness of polarization switching, thus providing better accuracy of analog states.
There are two main mechanisms involved in all FE devices that lead to performance degradation, i.e., imprint and fatigue. When the polarization hysteresis loop becomes asymmetric along the electric field axis, i.e., the þE C and -E C values are different for polarization switching, the FE components are known to have an imprint effect. Asymmetry at the FE-electrode interface and structural defects play a major role in imprint effect. Imprint can affect the symmetric weight update of the synapses using identical positive and negative pulses. Also, imprint effect is associated with a charge accumulation phenomenon that can eventually lead to a device breakdown. Fatigue in FE components is related to loss of P s and P r values over repeated switching cycles arising mainly due to charge trapping, leakage currents, or structural degradation due to bias stress. Memory endurance depends strongly on the FE fatigue properties.
Polarization switching in solid-state devices has been described by different domain-derived switching models. In the Kolmogorov-Avrami-Ishibashi (KAI) model, homogeneous formation of numerous nucleation centers followed by subsequent forward and sideways domain growth was proposed. The normalized change in polarization with time is expressed by the relation where t 0 is the characteristic switching time. The Avrami index, n, depends on the dimensionality of the domains and considered an integer taking a value of 3 for single crystals and 2 for epitaxial thin films. [77] The switching time follows the empirical Merz law, where E is the applied electric field, E a is the activation field proportional to the domain wall energy, and t α is the switching time at infinite applied field. KAI model was able to explain the polarization switching dynamics in FE single crystals and epitaxial thin films; however, in polycrystalline FE films, deviation from KAI model assumptions was observed where a distribution of switching time is observed experimentally. In the nucleation-limited switching (NLS) model, an alternative view of the switching dynamics is proposed, where region-by-region nucleation and domain switching take place. Switching of the entire system in this case is governed by the domain nucleation statistics, rather than the domain expansion model, as proposed in the KAI model.
Depolarization field, E dep , in a FE material arises due to an incomplete compensation of bound polarization charges by the layers adjacent to the FE layers. In FTJs, E dep inside the FE tunnel barrier can be estimated as, E dep ¼ PÀσ D ε 0 ε F , where ε 0 is the vacuum permittivity, P and ε F are the polarization and dielectric constant of the FE, and σ D is the screening charge density of the electrode. E dep can become significant in an ultrathin FE film where the screening length of the electrodes, i.e., the length required for complete screening of bound polarization charges, is comparable to the film thickness. Therefore, for FTJs with <5 nm FE thickness, E dep value can be significant unless the charge carrier density of the electrodes is high. For a FeFET, the expression for depolarization field can be approxi- where C F and C IS are the FE and series capacitance of the interface layer and semiconductor, respectively. [78] From the equation, it becomes clear that for a FeFET, increase in the interface layer thickness and/or decrease in the FE layer thickness will result in higher E dep . This will increase relaxation of the polarized domains and will lead to eventual loss in data retention. Based on these principles, E dep can be utilized in ANNs for custom-designed synaptic potentiation timescales or neuronal firing and recovery actions.

Doped HfO 2
Doped HfO 2 belongs to the class of incipient FEs where ferroelectricity can be induced and stabilized by different conditions such as mechanical confinement, doping, defects, stoichiometry variations, or exchange of (oxygen) isotopes. [79] Doped HfO 2 films consist of tetragonal, orthorhombic, and monoclinic phases ( Figure 2a). The orthorhombic crystalline phase content, responsible for the ferroelectricity in this material, can be induced by doping HfO 2 thin films with atoms of silicon, zirconium, or yttrium followed by an additional annealing step. [80] The abovementioned stabilization conditions affect the thermodynamic free energy and can contribute to a FE phase formation. A theoretical description of this free energy modification is given by Landau-Ginzburg-Devonshire theory. Among the entire hafnia family, only in Hf 0.5 Zr 0.5 O 2 (HZO), <400 C annealing temperature is reported to produce the Reproduced with permission. [89] Copyright 2018, AIP Publishing.
orthorhombic phases, but the crystallization temperature increases with decreasing thickness. [46,80] In a recent report, Jiang et al. [81] showed a cumulative heating approach can lead to FE phase in HZO under 400 C, making them suitable for BEOL processes.
In case of HZO thin films, theoretical calculations showed that a compressive stress along polar c-axis is necessary (in plane >8 GPa) for the monoclinic to orthorhombic phase transformation. [70] In the polar orthorhombic phase, an applied electric field causes displacement of four O ions in the HfO 2 unit cell inducing a large polarization (Figure 2b). Maximum value of P S reported in the literature is 53 μC cm À2 . [82] Distribution and movement of oxygen vacancies under applied electric field play a major role in stabilizing the FE phase [83,84] For Al-and Si-doped HfO 2 , highest FE properties are seen at %5 mol% dopant concentration, while for HZO, a broader dopant range can show FE phase with highest FE properties reported for 50% doped HZO. [85] Under repeated field cycling, the bulk of doped HfO 2 undergoes a phase transformation from monoclinic to orthorhombic phase, and the interfaces show diminishing amount of nonuniform, defectrich, tetragonal HfO 2 layer. The evolution of these structuring aspects contributes to the increase in P r and the opening of the constricted P-V hysteresis that are known to occur with "wake-up." The onset of the fatigue regime is correlated to an increasing concentration of bulk defects, which causes pinning of the domain walls. [86] 4.1.

Domain Dynamics in Doped HfO 2
Dynamics of FE domain structures under an electrical bias has been studied in many doped hafnia systems. By a combination of piezoresponse force microscopy (PFM) and pulse switching techniques, it was shown that the nanoscopic polarization reversal mechanism and the wake-up process in these systems arise due to electrically induced domain depinning. Significant imprint in the doped HfO 2 capacitors is caused by the different interface states that lead to asymmetric switching. It was found that decreasing annealing temperature results in higher amount of interface trap states leading to higher imprint and fatigue. [80] Domain switching kinetics in doped hafnia system is generally described by NLS model characterized by a broad distribution of the local switching times. It is found that the domain velocity varies significantly throughout the switching process, indicating strong interaction with structural defects. The switching times in HZO films of different thicknesses prepared under different O 2 pressure were investigated by Ryu et al. [87] A comparative study based on KAI and NLS switching models showed that NLS model can provide better fitting over the full range of polarization switching. The switching times could be modulated from 0.46 to 1.58 μs by varying the partial O 2 pressure during deposition and film thickness. The activation field for polarization reversal increased with increasing O 2 pressure with the pressure dependence being higher for thinner films. Also in Si-doped HfO 2 based devices, the time, field, and temperature dependence of polarization reversal showed that when a domain is excited in the proximity of its coercive voltage, V C , a probabilistic rather than a deterministic switching occurs. The nanoscale polarization kinetics of hafnia-based FEs reveals that the switching time can be exponentially reduced by increasing the applied bias for high-speed operations and by the correct tailoring of material parameters, like nucleation time and domain wall energy. [88,89]

PVDF-Based Copolymers
In terms of molecular FE, P(VDF-TrFE) with chemical formula [(CH 2 -CF 2 ) n -(CF 2 -CHF) n ] is mainly discussed here as a prototypical member of the family, as it is the most reported system in modern flexible electronics. [90] On the molecular level, FE polarization in P(VDF-TrFE) is a result of alignment of molecular dipoles formed by the difference in electronegativity between the electrpositive hydrogen ions and electronegative fluorine ions attached to both sides of carbon atom. The molecular structure of P(VDF-TrFE), as shown in Figure 2c, consists of -CH 2 -CF 2and -CHF-CF 2units rigidly attached to the main-chain carbon atoms. The all-trans molecular conformation gives rise to molecular dipoles to be oriented perpendicular to the chain axis while the polarization reversal results from the rotation of these dipoles about the molecular chain. In the crystalline β phase, molecules pack parallel to each other forming a quasihexagonal orthorhombic structure with a lattice spacing of %0.5 nm along the polar axis. Permanent electric dipole moments in P(VDF-TrFE), pointing from fluorine to hydrogen, gives rise to a macroscopic polarization of P % 10 μC cm À2 . [91] In an applied electric field, the polarization reverses by rotation of the CH 2 and CF 2 units around the backbone of the polymer chain. Detailed microscopic investigation showed that the FE polarization switching in PVDF-based copolymer process involves a chain of processes starting from the nucleation, forward domain growth, and subsequent sideways growth. [92] The timescale for each process is different resulting in a distribution of timescales for the observed domain switching. The nucleation and forward domain growth is typically very fast (in the range of 1 ps to 1 ns), whereas sideways domain growth could be comparatively slower (from several nanoseconds to seconds or even longer) depending on various intrinsic and extrinsic factors. Defects and structural disorders in the polymer introduced during synthesis can significantly influence the switching dynamics in P(VDF-TrFE) films by acting as nucleation centers and pinning sites for the domain wall motion, further escalating the complexity of the process. For precision computing, a sharp distribution of domain switching is preferable, and thus instead of continuous FE films, patterned nanostructures could be more promising. However, a larger distribution of switching times can be beneficial for probabilistic computing tasks and for hardware security through random number generation.

Domain Dynamics in P(VDF-TrFE)
Domain dynamics in PVDF-based copolymers reveal that depending on the film thickness and morphology, noticeable differences in polarization switching patterns can be obtained. [93] PFM studies in P(VDF-TrFE) films showed at a relatively low thickness/size aspect ratio (<1/10), the average domain size w and film thickness d are related via Kittel relation, w ¼ K d 1/2 (with the constant K describing a balance between the domain wall and electrostatic energies). However, films with rice-like grains with high thickness/grain aspect ratio (>1/5) were found to deviate significantly from this law. For films with high thickness/grain aspect ratio, the www.advancedsciencenews.com www.advintellsyst.com surface energy effects contribute significantly leading to the formation of thermodynamically stable domain structures. Transformation of P(VDF-TrFE) films after annealing was found to be governed by a variation of the surface tension at the filmsubstrate interface. In the high aspect ratio films, an increase in the surface energy led to the formation of additional domain walls that is energetically unfavorable, thus resulting in larger domains.
On the other hand, in lower aspect ratio films, the surface energy is significantly decreased leading to the formation of smaller antiparallel 180 domains. Application of voltage pulses reverses the polarization in the grain. The size of the switched area depends strongly on the parameters of the switching pulse, with the smallest written domain being about 30 nm in size. It was found that PVDF films do not have any significant imprint behavior. [94] The nanoscale features of the switching process include remote domain nucleation and spatially nonuniform wall velocity. Polarization reversal studies, performed with macroscopic dielectric measurements and by local probe techniques, revealed a rather complex switching behavior in the polymers that differs from both KAI and NLS models implying a strong dependence of the switching potential on the polymer defect structures. For a metal-FEsemiconductor (MFS) structure, the FE polarization reversal was shown to occur in close relation to charge compensation in the semiconductor layer. [95] Application of a rectangular high voltage pulse on a n-Si/P(VDF-TrFE)/Au capacitor revealed an asymmetric switching dynamics. Polarization switching on the positive bias side happens rapidly with the loss of the depletion layer due to fast accumulation of majority carriers while switching toward the negative side is markedly impeded by depletion layer formation. In a recent report, it is shown that due to different annealing temperatures and protocols, the morphology of the spin-coated ultrathin copolymer films are modified significantly, thus impacting the switching timescales and threshold fields of the FTJs. The best performing devices showed a projected switching timescale of subnanosecond range. An improvement in switching speed by seven orders of magnitude is achievable in these devices with an increase of the programming voltage by less than a factor of 2. Devices with lesser defects showed a good fit to NLS models over a wide field range where devices with higher amount of defects showed a fit to NLS model only at high field values. [66] The mean domain switching times (t mean ), estimated from the NLS fit, when plotted against inverse field (1/E), gives a linear dependence (Merz law) and extrapolating the fit to infinite field value (1/E ¼ 0), it is possible to calculate the theoretical limit of switching speed. For PVDF based systems, tens of picosecond of theoretical speed limit is calculated. This value is consistent with estimation from PFM results. [92] 5. FTJs and FeFETs 5.1. Device Physics

FTJs
The rich physics of FE polarization switching, polarization retention, and relaxation in FTJ and FeFET architectures opens up an avenue for designing low-power, analog spiking neurons and synapses, similar to their biological counterparts. Figure 3 shows schematic illustrations of different device architectures and their working principles. In a traditional FeRAM, a FE capacitor stores the charge while a MOS transistor, connected in series, acts like a switch. Although robust in operation, high operating voltage and  www.advancedsciencenews.com www.advintellsyst.com large footprint of FeRAMs impeded their application in dense memory structures. In an FTJ, two different metal or semiconducting electrodes sandwich an ultrathin layer (1-5 nm) of FE barrier. In a varying electric field, the FE polarization switches between two perpendicular directions (up or down). Depending on the orientation of polarization in the tunnel barrier, charge carriers do either accumulate in or deplete from the interface layers of the electrodes to screen the bound polarization charges. For junctions with different electrodes, this screening effect produces an asymmetric barrier potential. As a result, polarization switching alters the mean barrier height for the tunneling electrons and, therefore, the electrical resistance of FTJs show bistable states with varying electric field. [96,97] This phenomenon is known as the tunneling electroresistance (TER) effect. [98][99][100][101] In general, two metal electrodes are used in FTJs. However, in recent times it is found that a semiconducting electrode at one end of the FE can give rise to larger resistive switching effect. [101,102] This larger switching effect has its origin in the Schottky barrier formation at the FE/semiconductor interface when the polarization direction moves away from the interface. This Schottky barrier additionally changes the barrier width in addition to barrier height of the FTJs, leading to a large R on/off at room temperature.
Besides the crucial role of electrodes in the emergence of TER, [103] charge screening also affects the long-term stability of FE polarization due to aforementioned E dep . Based on the FE polarization retention, a long-or short-term potentiation (LTP, STP) and depression (LTD, STD) can be designed in a device. Initially, most reports on FTJs concentrated on the bistable resistive switching effects; however, later on it is realized that FTJs can not only work as a binary memory, but multiple intermediate resistance states can be reliably accessed in FTJs through programmable control of partial switching of FE domains. [104] In micron-scale devices, large number of FE domains are formed to maintain an energetically stable configuration and control of a mixed domain phase with coexisting up and down domains is comparatively easy. However, as devices are scaled down, and we approach from multi-to monodomain or a few-domain limit, precise control of intermediate states becomes a major concern. For nanoelectronic devices utilizing ultrathin FE films, another important aspect is the interface quality of the FE films with the metal or semiconductor electrodes. In oxide FTJs, in addition to the FE polarization reversal induced resistive switching, an electric-field-enhanced reversible migration of oxygen vacancies also plays a big role. [105] Defects at the interface or inside the FE film can cause charge trapping sites that, over a significant cycles of operation, can build up significantly, hampering the normal device operation. In neural networks, this is a major concern for DNN training operation where 10 9 cycles of on-off cycles are expected from the synaptic weight elements. Therefore, for any large-scale networks concerning the nanoscale FE devices, interface quality and control of FE domain dynamics, i.e., a combination of switching and relaxation timescale, are of critical importance. With proper design of material stack and configuration, an extremely energy-efficient and versatile neural network can be created.

FeFETs
In a FeFET, a FE material replaces the gate dielectric layer of a MOSFET structure. Therefore, an applied gate voltage polarizes the gate FE layer, making the net polarization pointing toward or away from the semiconductor channel. When the polarization direction points toward the semiconductor channel, electrons accumulate at the interface between the semiconductor and the FE layer in n-type semiconductors. This downward polarization, thus, results in increased conductivity in the n-type semiconductor channel, representing the device on state. Conversely, when the polarization direction points away from the semiconductor channel, a depletion of electrons occurs at the interface resulting in the decrease in drain-source current, leading to device off state. For a p-type semiconductor channel, similarly, a reverse FE polarization determines the device on and off state. In general, a gate voltage of more than 5 V magnitude is needed to fully rotate the polarization state in the 30-50 nm FE layer of the FeFET and thus opening the full memory window (MW). However, to keep the access transistors small in CMOS readout, the limitation comes in terms of maximum programming voltage. This requirement opens up the necessity for exploring novel materials, [106] interface and device design space for maximizing the memory performance within the 3.  [19,107] Here, some of the promising results are discussed for both hafnia-and PVDF-based FeFETs for their future prospect in CMOS integrated hardware neural network (HNN) and near or in-sensor computing.

FTJs as NVMs
Solid-state FTJs, investigated within the last decade, are mainly based on oxide perovskite FEs. [101] These devices have shown promises for their application in nonvolatile resistive memory elements. Large R on/off , reproducibility, high-speed, and low operation energy are the major advantages of FTJs compared to the FE capacitor-based FeRAMs. From technology perspective, endurance of FTJs needs special attention, which is currently limited to the order of 10 6 , mostly. [108,109] A very high endurance value (>10 14 cycles) for FeRAMs based on thick FE films is reported. [110] This indicates that in ultrathin films, a right combination of FE-electrode materials and their carefully engineered interfaces must be found to reach this KPI. For oxide FE, defects such as oxygen vacancies in the tunnel barrier are a critical parameter controlling endurance, as repeated operation leads to trapped charges in the barrier, accelerating the breakdown of the device upon frequent cycling. The retention of the FTJs is also critical for NVM applications. Another important factor is the scalability of FTJs. In FTJs, scalability is not restricted by its readout process like the classical FeRAMs. For oxide perovskite and polymeric FTJs, devices with dimensions of the order of 200 nm have been demonstrated. [111][112][113] Results with devices <100 nm [114,115] need further investigations for evaluating the scalability limit of FTJs and assess their potential as NVMs and as memristors in massively parallel architectures. In Section 6.5, low readout current of the ultrascaled FTJs and their possible solutions have been discussed. Table 2 summarizes SoA KPIs of 2T memories based on HZO and P(VDF-TrFE). In some cases, FE diode and capacitor data are used as FTJ data are still rather limited. Both HfO 2 and P(VDF-TrFE) memories show potential for long-term data retention. However, in many cases, a thin insulating oxide layer is unavoidable at the FE-semiconductor interface to improve the interface quality and reduce trapping sites. This insulating layer has adverse effect on the data retention. Thus, optimal performance requires an application-specific, suitable architecture (MFM or MFIM). As can be seen from Table 2, many of the reported structures can offer suitable R on/off , operation in low-voltage range, significant MW, fast operation speed, and low thermal budget fabrication, suitable for BEOL processes. Multibit analog operation in many cases has not been studied; however, their switching pattern indicates that it is possible to have controllable multibit operation from these devices. In many cases, the endurance measurements were not carried out beyond 10 3 cycles. While retention properties are easily extrapolated, endurance data need to be studied experimentally to verify their true potential for training architectures. The best reported data for HZO based 2T memories exceed 10 9 cycles of operation, [116] while for P(VDF-TrFE)-based capacitors prevention of delamination of the top electrode is shown to improve the endurance significantly. [117] In P(VDF-TrFE), electron-induced phase decomposition due to repeated electric field cycling can cause accumulation of gases, leading to device fatigue and eventual failure. When the gas barrier is removed through use of a transparent electrode, a virtually fatigue-free FE capacitor is realized. The best value in P(VDF-TrFE) capacitor with PEDOT:PSS electrode is >10 8 cycles, which is suitable for DNN training applications.

FTJs as Synapses
Besides their use as binary NVM, FTJs can be used as memristive devices for artificial synapses in neuromorphic architectures. These FE memristors interconnected in HNNs are able to demonstrate unsupervised learning with STDP. Ultralow power HZO-based FTJ synapses have been demonstrated for HNN applications. [118,119] For the networks, high-density 3D vertical HZO FTJs were fabricated that showed a P r value of %16 μC cm À2 and nonvolatile storage at 100 ns for over 10 3 cycles. Biological synaptic features like LTP, LTD, and symmetric STDP at an energy consumption of 1.8 pJ per spike were demonstrated (Figure 4).
A pattern training in a 6 Â 6 FTJ array showed a strong tolerance to the input faults and variations. The simulation of pattern classification and recognition, performed using the backpropagation algorithm, showed >96% accuracy providing a high-potential implementation of the HZO-based FTJs in ANNs. Annealing temperature of 450 C makes them suitable for CMOS postprocessing compatible; however, an operating voltage >5 V, for operating in major loop, can still be a concern for the low-voltage CMOS readout. Further optimization of stack structures can be proved beneficial in this regard. Other reports on HZO-based FTJ synapses also confirmed efficient STDP-based learning. [119] In another work, FTJs based on metal/Al 2 O 3 /HZO/Si doublebarrier structure was demonstrated to perform as an electronic synapse. [120] The interfacial Al 2 O 3 layer and silicon substrate were shown to enable sizable TER, even when the thickness www.advancedsciencenews.com www.advintellsyst.com of HZO is above 10 nm. The Al 2 O 3 /HZO synapses show symmetric potentiation/depression characteristics and widely tunable conductance under constant modulation of pulse amplitude. However, under constant amplitude and pulse width, the potentiation and depression were highly asymmetric. Also, the operating voltage of the devices was >7 V that needs further reduction for low-voltage and low-power applications. Emulation of key synaptic functions was demonstrated using 2T FTJ memristors with a spin-coated P(VDF-TrFE) (70:30) tunnel barrier sandwiched between Au-and Nb-doped SrTiO 3 (NSTO) electrodes ( Figure 5). [65] The FTJs exhibited analog switching behavior over a five-order-of-magnitude range. The semiconducting bottom electrode-induced Schottkey barrier formation led to this large on-off ratio and a rectifying I-V characteristics that can potentially allow selector-less integration of these FTJs in crossbar arrays. The FTJs reproducibly mimicked LTP/STP, LTD/STD, paired-pulse facilitation and depression (PPF/PPD) and STDP on timescales down to nanoseconds. A good polarization retention, switching cycle reproducibility, and large range of accessible conductance states provide large versatility for these FTJs in the design of HNNs. Besides, operation at nanosecond time scale opens an avenue toward the realization of ultraenergy-efficient electronic synapses. Estimation of energy consumption in these synapses indicates that potentiation and depression of the FTJs require an energy of 1.1 pJ and 170 fJ, respectively. While this is already comparable to the synaptic energy usage in the brain, possibility of further reduction of energy consumption is predicted with downscaling the junction sizes. Assuming linear variation of tunneling current with junction area, an energy consumption of 1.2 Â 10 À17 J μm À2 for potentiation and 1.9 Â 10 À18 J μm À2 depression was predicted. In a recent work, a significant improvement in conductance update linearity is reported from the similar architecture with the nonlinearity factor decreasing from 2.7 to 1.2 for potentiation and from 5.2 to 1.5 for depression due to application of nanosecond pulsing schemes and higher domain pinning sites (Figure 5g). [66] Here, it is important to point out that many of this exciting properties arise due to FE/NSTO interface. NSTO is an n-doped semiconductor where large band bending occurs due to FE polarization induced field. However, NSTO is neither a CMOS postprocessing compatible nor a material suitable for integration on flexible substrates. Therefore, other low-temperature processable semiconductors need to be tested in similar FTJ structures. Oxide semiconductors such as indium oxide (In 2 O 3 ), indium galium zinc oxide (IGZO), or 2D semiconductors like MoS 2 or WSe 2 can be promising alternatives in this respect.

FTJs as Neurons
For neuromorphic architectures, leaky-integrate-and-fire (LIF) model of neurons is widely adopted due to their relatively simple mathematical description, yet providing sufficient accuracy in replicating essential biological features. The neuronal dynamics can be characterized in the following major features: integration of weighted synaptic inputs arriving from other neurons,  N ¼ 10, 25, 38). e) The hardware implementation for pattern training application in HZO-based FTJ array. Evolution of pattern "F" in the 6 Â 6 HZObased FTJS array. Random false training pulses involved during the second and fifth training steps showed fault tolerance. f ) Hebbian and g) anti-Hebbian STDP rule scheme in the HZO-based synaptic array. The red lines are the exponential fits to the experimental data. Reproduced with permission. [118] Copyright 2018, Royal Society of Chemistry.
www.advancedsciencenews.com www.advintellsyst.com subsequent firing when a certain threshold is reached and the recovery to their initial states. These momentary firing dynamics can be reproduced in FE devices using transient switching characteristics of the FE materials. In general, in FTJs and FeFETs, the retention of the programmed conductance states is stable due to nonvolatile nature of FE polarization. However, absence of proper screening of the polarization-bound charges can lead to significant E dep causing relaxation of the programmed conductance states. Therefore, through proper control of relaxation dynamics of FE polarization, it is possible to design a LIF neuron. [30] Two easy ways to control the LIF behavior in an FTJ involves control of relaxation by modulating the screening charge-carrier density of the electrodes and by changing the FE film thickness. In a recent work, it is shown that by decreasing the charge carrier density of the semiconductor electrode, a crossover from a NVM-to a LIF-type neuronal behavior can be obtained ( Figure 6). [29] LIF response was recorded in an FTJ with P(VDF-TrFE) as the FE and NSTO as the semiconducting bottom electrode, with 0.25 wt% Nb doping. [29] The tunneling current of the FTJ showed oscillatory response when subthreshold pulses of magnitude þ0.7 V and duration of 5 ms are applied on the device at a time interval of 100 ms (Figure 6a-c). When the initial state of the FTJ is set close to the off state, the current output resulted in bundles of spikes with a width of %300 ms and a frequency of 2.2 Hz. The þ0.7 V pulses are below threshold for off to on transition, and consequently, the system needed to integrate the effect of a series of pulses before triggering a response. With increasing amplitude of input pulses, the width of the current pulse bundles increased and their frequency decreased. Also, the duration of the individual voltage pulses was found to determine the width and frequency of the current pulse bundles. For a pulse amplitude of þ1.0 V, i.e., when the input voltage is close to threshold, a series of 5 ms pulses with an interval of 100 ms no longer generated an oscillating output current. A more pronounced integrate-and-fire response is reported from the same device with the application of longer voltage pulses. An example is depicted in Figure 6e-g where voltage pulses of amplitude þ1.0 V and a duration of 200 ms and interval of 800 ms produced a sudden integrate and fire response after about 30 s. Although the tunneling current shows initial oscillatory response, it suddenly increases, mimicking the integrate-and-fire behavior of a neuron. The first firing event marks threshold switching from a nearly off state to an on state. After this first firing event, the current amplitude decreases gradually to an intermediate level. The integration time required for LIF switching can be programmed by modulation of amplitude and frequency of the voltage pulse train where a frequency of 2.3 Hz reduced the integration time to 14 s. Further decrease in the integration time to 5.5 s with voltage pulses of amplitude þ1.1 V led to continuous firing but at the expense of neuronal recovery. This is an indication that besides control over the integration time, the pulse parameters also determine the relaxation of the tunneling current after the firing event with stronger and more frequent pulsing prolongs the FE polarization relaxation time. Because firing and recovery in the FTJ-based neuron is a sensitive balance between FE polarization switching and retention, E dep of FTJs also needs careful designing for a proper LIF functionality with most important parameters being the charge carrier concentration in the semiconducting electrode and the thickness of the FE tunnel barrier. This finding opens a new   [122] Based on FeFET model, they demonstrated that MW can be improved by optimizing the electric field distribution in the gate stack through the utilization of high-κ interlayer (IL) dielectric. The gap in the thickness and permittivity of the HZO (t FE ¼ 10 nm and ε FE ¼ 30) and SiO 2 IL (t IL ¼ 0.8 nm and ε IL ¼ 3.9) results in the nonuniform distribution of the electric field across the stack leading to: 1) lower voltage across FE causing polarization switching along nonsaturated hysteresis loops that reduce MW and 2) increased E-field in the IL that not only causes charge trapping, but also causes early dielectric breakdown. A properly designed FE/IL stack design, therefore, can significantly enhance MW, retention, and endurance in the future FeFETs. Prospect for PVDF and its copolymers have also been tested widely as FeFET gate materials for high-performing memory applications. [123,124] In most cases, the reports suggest good R on/off , MW, and retention are possible from the polymeric FeFETs. Their potential for multibit operation, linearity in synaptic weight update has been reported recently; [63] however, performance of scaled devices and operation in connected network is still in an early exploratory phase and needs deeper understanding.

FeFETs as NVMs
From a wide range of literature data, it can be safely conjectured that channel semiconductor material, optimal gate stack, and geometry design can play a major role in determining the FeFET properties. High I on/off is a general property of most reported structures; however, switching voltage, analog states, www.advancedsciencenews.com www.advintellsyst.com retention, and endurance depend critically on the abovementioned properties. For instance, Park et al. [123] reported a large switching response with a counterclockwise hysteresis in FeFETs with a 100 nm P(VDF-TrFE) as the gate FE and Si as the channel semiconductor. A 1.3 V MW was reported in the I D -V G loop when gate voltage was swept between À3 and 5 V with V D of 0.5 V. However, integration of Si as the channel semiconductor in the BEOL processes is not feasible and hence low thermal budget materials like the oxide and organic semiconductors provide viable options. Figure 7 shows examples of one oxide and one organic semiconductor based FeFET operations. Yoon et al. [124] reported one of the most promising structures with P(VDF-TrFE) as the gate insulator and oxide semiconductor Al-Zn-Sn-O layers, in which thin Al 2 O 3 is introduced between two layers, as the channel material. The field-effect mobility, subthreshold swing, on/off ratio, and gate leakage currents were obtained to be 32.2 cm 2 V À1 s À1 , 0.45 V decade À1 , 10 8 , and 10 À13 A, respectively. The MW of the FeFET was 7.5 V with a gate voltage sweep of À10 to 10 V, and remained at 1.8 V, even with a lower voltage sweep of À6 to 6 V. The transmittance of the fabricated device was more than 90% at the wavelength of 550 nm that makes it promising in transparent surface applications. Xu et al. [44] showed two ultrathin AlO x interfacial layers sandwiching an ultrathin FE film with a low E C can decrease the FeFET operation voltage significantly. Downscaling thickness of the FE film does not affect the gate leakage due to insertion of two ultrathin AlO x layers at both sides of the FE film. The endurance, mobility, and retention were found satisfactory, both in stable and under bent conditions. A transparent and flexible FeFETs on a polyethylene-naphthalate (PEN) substrate was demonstrated by Lee et al. [125] using amorphous indium gallium zinc oxide (a-IGZO) as the channel semiconductor and P(VDF-TrFE) as gate insulator. Highperformance transistors enduring hard bending tests confirmed P(VDF-TrFE) phase formation process do not damage the underlying a-IGZO channel. This low-temperature, low damaging process of P(VDF-TrFE) is one of the most suitable features for the oxide FeFETs. With the development of a reliable process, a nonvolatile pixel memory for flexible displays could become a very attractive application for the polymeric FeFETs. Similar features are reported with ZnO as the oxide channels; however in this case, MFIS structure was employed as the P(VDF-TrFE) formation process degraded the crystalline quality of ZnO. [126,127] Effect of Ambience: Ferroelectric oxides or fluoropolymer PVDF and its copolymers are generally insensitive to humidity, oxygen, or thermal changes in normal atmospheric condition limits. However, FeFETs involve a semiconductor channel which might have a strong or weak sensitivity to ambient conditions. For instance, 2D semiconductors or organic semiconductors are very sensitive to humidity and oxygen while oxide semiconductors can show eventual drift of conductance over time. To protect these devices from fast or gradual degradation, adoption of a proper encapsulation strategy is, therefore, essential.

FeFETs as Synapses
Doped hafnia-based solid state synapse is demonstrated using a single FeFET integrated in a 28 nm HKMG technology. [128] The nonvolatile, gradual switching of the FE hafnia is exploited in these devices to continuously tune the conductivity of the transistor channel. This gave rise to continuous synaptic weight   [175] Au(G)/P(VDF-TrFE)/Si*/Au(D-S) [178] Al(G)/ P(VDF-TrFE)/MoS 2 /Cr/Au(D-S) At least one component is not BEOL compatible.
www.advancedsciencenews.com www.advintellsyst.com update over a large number of subsequent switching pulses. Devices with comparatively larger channel length and width of 500 nm were employed involving a substantial amount of FE domains in the gate stack. Voltage pulses applied either at the gate and/or source/drain/bulk terminals switch the polarization of the FE in a nonvolatile manner subsequently tuning the channel conductivity. Application of progressively increasing gate pulses in the multidomain device gradually switched the device from an initially high-V th state into a low-V th state. This circuit also exhibited STDP. FeFET-based analog synapses are also demonstrated by Jerry et al., where a 5-bit symmetric potentiation and depression characteristics and a 45Â tunable range in conductance with 75 ns update pulse were demonstrated . [129] A transient Presiach model is used to accurately predict the minor loop trajectories and P r values for arbitrary pulse width, voltage, and history. A benchmarking of on-chip learning performance in terms of area, latency, energy, and accuracy of a FeFET synaptic core revealed a 10 3 -10 6 acceleration in online learning latency over multistate RRAM-based analog synapses. In a HZO-based FeFET with WO x as the channel semiconductor, Halter et al. demonstrated a voltage-controlled, symmetric and analog potentiation and depression with good linearity in weight update due to incremental voltage (Figure 8). For increasing pulse widths in the range 0.5-5 μs, no cumulative effect was observed. The operation of the FeFETs is found to be energy-efficient with writing energy of fJ range and fast programming time of 40 ns. Retention tests performed over 4-bit depth showed low noise (1%). By adjusting the channel FE thickness from 15 to 8 nm, the R on/off of the FeFET is engineered from 1 to 200% with an on-resistance >100 kΩ, depending on the channel geometry. [130] As discussed earlier, in FE analog memories, bit precision starts to become limited in scaled devices due to reducing number of available FE domains and inherent stochasticity in the FE domain switching behavior. [131] In general, implementation of off-chip training followed by reduced bit precision for inference mode and on-chip learning and inference with reduced bit precision have been proposed. However, both strategies demand efficient training algorithm taking into consideration the quantization in synaptic weights.
Analog response from FeFET synapse is reported in many other works using voltage-dependent partial polarization switching in multidomain FE thin films. [129] Recent experimental works have shown the ability to program FeFETs with voltage pulse widths as low as 50 ns [132] while the programming voltage as low as 1.8 V is reported through proper engineering of the gate stack by adding an additional metal layer between the FE capacitor and MOS capacitor. [133] In these devices, 32 conductance states (equivalent to 5-bit precision) are reported for 60 μm 2 FeFET devices , [129,132] while 8 nonoverlapping conductance states (equivalent to 3 bits) were achieved in a 0.25 μm 2 size devices. The precision of synaptic weight was proposed to be further improved by change in architecture like the two transistor-one FeFET (2T1F) hybrid weight cell that allows up to 64 states with improved nonlinearity and asymmetry factors. [134,135] Ali et al. reported high endurance in hafniabased FeFETs without retention penalty and analog states by implementing lamination of the FE layers. [136,137]  Transfer curves when V G sweep ranges symmetrically increased from À3 to 3 V to À10 to 10 V for V D of 1.0 V. c) Transfer curves when only the positive side in the V G sweep range increased from 2 to 10 V with maintaining the negative side as À12 V. d) Transfer curves when only the negative side in the V G sweep range decreased from À10 to À5 V with maintaining the positive side to be 10 V. All the measurements were carried out in dark and at room temperature. a-d) Reproduced with permission. [124] Copyright 2010, John Wiley and Sons. e) Schematic configuration of the flexible FeFET NVM. f ) Transfer characteristics of the low-voltage operating flexible FeFET NVM measured at the planar and bending states, respectively. g) Memory switching endurance and h) data storage retention characteristics of the device with a 60 nm thick P(VDF-TrFE-CTFE) ferroelectric film. (e-h) Reproduced with permission. [44] Copyright 2017, The Author(s). Published by Springer Nature, Creative Commons Attribution (CC BY) License.
www.advancedsciencenews.com www.advintellsyst.com Significant amount of work on PVDF-based FeFETs showed potential of these devices in mimicking neuroplasticity. In a recent work, Tian et al. [63] reported that the conductance of P(VDF-TrFE)based FeFETs, with 2D semiconductor MoS 2 as channel material, can be precisely manipulated to vary between more than 1000 intermediate states with the highest switching ratio of %10 4 . The quasicontinuous resistive switching in the MoS 2 channel, resulting from the controllable FE domain dynamics, mimicked the synaptic plasticity behavior such as LTP and LTD and STDP. In addition, the device showed no sign of fatigue or failure even after 10 7 cycles of continuous operation. Together with an ultralow energy consumption for each synaptic operation (less than 1 fJ), these devices can be considered as one of the potential contenders for the massive neural architecture in bioinspired networks.

FeFETs as Neurons
Accumulative nature of polarization reversal in FE layer is a promising way to induce a threshold switching behavior and has been successfully used to mimic neuronal firing activities. In nanoscale Si-doped HfO 2 -based FeFETs, two key neuronal dynamics have been demonstrated. Integration of action potentials and the subsequent firing were optimized in these devices by designing specific electrical excitations that induce particular NLS kinetics of the FE layer. To tune the firing frequency, arbitrary refractory period, and the leaky effect, E dep needs modulation as well because it dictates the time during which the FE polarization will start to relax, i.e., the leak effect will take place. The FeFET-based LIF neuronal behavior was reported from 30 nm (channel length) Â 80 nm (width) devices [30] that highlights the possibility of advanced downscaling of neuron circuits which can significantly reduce the complexity of neuromorphic architectures.

Ferroelectric Memories in Reprogrammable Arrays
A significant part of the DNN processing is VMM operation between the input vector (voltage pulses) and the weight matrix (conductance of the memristors), which essentially performs multiply-and-accumulate (MAC) operation and generates an output current vector. In this respect, IMC is a promising paradigm as it performs the computation directly into memory subarrays and in-principle can be performed in fully parallel fashion. In a recent work by Toshiba scientists, [37] it was shown that nonlinear FTJ memristors can perform linear computation at ultralow currents ( Figure 9). Using Si-doped HfO 2 -based FTJ crossbars, an analog-voltage-amplitude VMM was demonstrated. By utilizing the device nonlinearity, that remains constant for multiple conductive states, a selector-less array is obtained. This result opens possibility to exploit these features for analog VMM-intensive applications, such as neural inference engines, toward energy efficiencies above 100 TOPS W À1 .  [130] Copyright 2020, American Chemical Society.

FeFET-Based BCNNs
Chen et al. [138] reported a FeFET crossbar array-based binary convolutional neural network (BCNN) where the basic cell consisted of two FeFETs and two access transistors. In this architecture, two FeFETs, storing complementary bits, represent one weight bit. FeFET crossbar designs of array size 64 Â 64, simulated using the HSPICE FeFET models, showed write power reductions of 5600Â and 395Â compared to RRAM and CMOS equivalents, depending on the array design. Read power can be reduced by 4.1Â and 3.1Â. However, the read latency is found to be 8% higher with the FeFET approach. In overall comparison with a CMOS-based design, the FeFET-based design showed best performance in read power-delay product (PDP), indicating a promising future direction to explore and benchmark. e) Illustration of a multilayer neural network trained for the F-MNIST task to classify 28 Â 28 pixel images of garment items into ten different categories. A neural network in hardware implemented by FTJ crossbars for the weight layers can operate fully analog apart from the peripheral digital converters. X and Y represent the input value vector and output label vector, respectively. f ) Simulations of inaccurate weight transfer of the network trained on F-MNIST to FTJ crossbars implementing synaptic weight layers. Demonstrated programming precision for >8 states with σ ¼ 3.5% would reduce the network's accuracy by 1%. Thirty-two separate states programmed within σ ¼ 2% would recover the initial test accuracy. g) Computation efficiency estimations via simulations of the network. Reproduced with permission. [37] Copyright 2020, Springer Nature.

Application in DNN and SNN
DNNs are one of the most used ANNs where training and inferencing are performed based on backpropagation algorithm. Working principles of DNNs are not quite biologically inspired, as, the neuron outputs in a DNN are still real-valued numbers, processed on synchronous time-steps. However, massively parallel VMM operation is at the heart of DNN forward-inferencing and training. In a DNN, integration of device read currents along the columns of a crossbar array implements forward propagation of neuron excitations while integration along rows implements the backpropagation of error terms. From material and device perspective, ideal characteristics for more than 90% DNN training accuracy require linear and symmetric conductance change (both potentiation and depression wise) of the synapses with identical stimulating pulses, large dynamic range of conductance, and minimum variability of conductance states. Some degree of nonlinearity is tolerable, if the conductance range over which the response is nonlinear is only a small fraction of the overall conductance range. Jerry et al. [129] showed with FeFETbased 5-bit analog synapse with symmetric potentiation and depression characteristics, it is possible to attain %90% DNN online training accuracy. However, instead of an identical pulse scheme, an incremental pulse scheme is used to achieve this accuracy. Kim et al. [67] studied the influence of the FE properties and contact barrier heights in the FeFET synapses based on P(VDF-TrFE) on the training and recognition performance of a multilayer perceptron (MLP)-based neural network ( Figure 10). Two different datasets from the MNIST database, i.e., the fashion and handwritten digits, were used for the training and inference tasks. Investigation on the effect of annealing temperature of P(VDF-TrFE) and the nature of the contact metals (Ti, Cr, Pd) of the FeFET showed excellent FE properties with maximized amount of β-phase and a metal, that forms a relatively high tunneling injection barrier, can improve the dynamic conductance range (DR), defined as ratio of maximum and minimum conductance (G max /G min ) and nonlinearity of the postsynaptic current (PSC). This improvement in dynamic range and nonlinearity by suppression of tunneling current can result in improved accuracy of recognition in neural networks. The effect of the contact metal on the recognition rate revealed that the synapses with Pd contact can achieve maximum recognition rate of 75.2% which is about 10% lower in comparison to that of software NNs (86.8%), whereas the rates obtained with Ti-or Crcontacted synapses were less than 50%. This study opens the prospect of optimizations of P(VDF-TrFE) morphology, semiconductor-FE interface, and contact metals for high-performance cognitive tasks based on P(VDF-TrFE) FeFETs.
In SNNs, neurons operate on asynchronous, uni-valued, event-based spikes while learning takes place in the synapses by STDP-based local Hebbian learning rule. SNNs are efficient in learning spatiotemporal pattern in data and therefore from FE and LTP nonlinearity (lower panel). Reproduced with permission. [67] Copyright 2021, Royal Society of Chemistry.
www.advancedsciencenews.com www.advintellsyst.com device perspective, one important aspect is properly engineered FE polarization and depolarization dynamics to mimic the LIF neuron firing and implementing accumulative nature of switching for STDP-based synaptic weight update. Similar to DNNs, device-level randomness and limited bit precision of on-chip synaptic weights also affect the classification accuracy of SNNs adversely. In all FeFET-based SNNs with HZO synaptic and neuron elements, Dutta et al. [139] showed a stochastically firing neuron helps improve the SNN classification accuracy in the presence of reduced weight precision. In general, reduced bit precision results in reduced accuracy, i.e., up to 6-bit precision, a test accuracy of 95.4% is seen that starts decreasing to 91% for 5 bits and drastically down to 43.5% for 4-bit precision. However, upon adding noise, the accuracy for 5-8 bits increased to 96%, For 4-bit weights, the accuracy improved substantially with more noise around the threshold; however, starting from 3-bit precision, no improvement was found, emphasizing the importance of higher bit precision for accurate learning in SNNs.
Simulations based on both HfO 2 -based FTJ [140] and junctionless (JL) FE FinFET [141] showed pattern recognition accuracy to be %80%. This moderate accuracy rate, in both cases, is a consequence of nonideal conductance update under identical pulse schemes. An incremental pulse scheme, coming at the cost of circuit complexity, showed improvement in recognition accuracy to >90% level. In a recent work, it was shown that shorter pulses of 20 ns width is able to improve weight update linearity in FTJ synapses under identical pulse scheme. [66] Also, addition of an ultrathin dielectric capping layer on the FE layer in a FeFET can make the polarization rotation more gradual due to linearly regulated gate stack capacitance and has the potential to improve bit precision and weight update linearity. Such custom-designed pulse schemes or innovative gate stack design, with proper combination of thickness, dielectric constants (ε dielectric ) and gate geometries, improvement in linearity, and bit precision, can be obtained improving both recognition accuracies in SNNs or online training in DNNs.

Ferroelectric Devices for Wearable Intelligent Systems
Synaptic functionality under extreme bending conditions was demonstrated in ultrathin conformable organic synaptic transistors based on P(VDF-TrFE) and pentacene ( Figure 11). [63] The Figure 11. Synaptic characteristics of the flexible pentacene-PVDF-based FeFETs on different uneven surfaces and under extreme bending conditions. a) Schematics of device architecture, PVDF, and pentacene chemical structure and images of the conformable FeFETs on different uneven surfaces, device on/off ratio and MW on different surfaces. b) Images of devices on brain-shaped PDMS mold and FeFETs folded with a bending radius of 50 μm and c) LTP and LTD behavior of the FeFETs on the brain mold (red line) and the in folded condition (black line). d) PSC response of the folded devices was found to depend on the pulse width and the number of pulses. e) Repetitive LTP and LTD operations in the folded condition during 6000 spikes of presynaptic pulses. One cycle of 30 potentiating pulses was followed by subsequent 30 depressing pulses. Reproduced with permission. [64] Copyright 2019, American Chemical Society.
www.advancedsciencenews.com www.advintellsyst.com device on/off ratio, MW, and synaptic characteristics of the fabricated free-standing devices on various uneven substrates, such as thermal-shrink plastic film, jelly, textile, candy, toothbrush, and a brain-shaped PDMS mold, were tested. Also, the FeFETs were tested under extreme bending conditions, i.e., up to a bending radius of 50 μm. The fabricated synaptic transistors exhibited stable LTP/LTD features under both normal and harsh bending conditions. This performance stability suggests a new research direction for realization of wearable artificial intelligent systems. Lee et al. [59] reported a flexible, artificial, tactile sensory organ with intrinsic-synaptic functionalities. For this application, a synaptic transistor with P(VDF-TrFE):BaTiO 3 nanocomposite as the gate dielectric and pentacene as semiconducting channel was used. Triboelectric-capacitive coupling under finger touch induced FE dipole switching that modulates the postsynaptic current of the device and allowed reception and slow adaptation. Emulation of synapse-like connection of receptor cells and afferent neuron terminals in a sensory organ enables implementation of the sensor with intrinsic intelligence without link to a neuronal processor and thus defines a new paradigm in sensor technology for neurorobotics, autonomous systems, intelligent electronic skins, and prosthetics ( Figure 12).

Circuit Integration Issues
Write disturbance or nearest neighbor cross-talk is one of the key issues for the dense integration of memories. Write disturbance Figure 12. Intrinsically intelligent artificial tactile sensory organ with sensing and processing ability. The organ comprises adapting sensing mechanism and a synapse-like connection with an afferent neuron. Pressure induces influx of Ca 2þ ion through the piezo channel increasing the membrane potential. The increase in membrane potential eventually leads to synaptic firing through release of neurotransmitters. Synaptic firing occurs in response to tactile information and is processed by synaptic plasticity. a) Schematic representation of dipole switching in the FE gate layer and accumulation of holes in the FeFET channel induced by tactile stimulation (I-IV). Illustration of formation principle of P r with a change in channel conductance corresponding to synaptic weight. Relative changes in the PSC of the FeFET at b) different touch pressures, c) duration (%1 kPa), and d) touch rate (%1 kPa for 5 s). e) Reception by a flexible sensory organ occurs in a self-energy transducing way by triboelectric effect during finger touch. This eventually modulates the drain current with aligned dipoles in the BaTiO 3 NPs/P(VDF-TrFE) nanocomposite by generated triboelectric capacitive potential, resulting in a sensing and processing at the same node. Reproduced with permission. [59] Copyright 2020, The Author(s). Published by Springer Nature, Creative Commons CC BY license.
www.advancedsciencenews.com www.advintellsyst.com appears when a programming voltage across a certain column or row not only affects the selected memory cell but also affects the neighboring columns or rows causing a memory cell to deviate from its programmed state. Even though mitigation strategies are available with extra components like selectors, the ideal goal is always to minimize this cross-talk within single memory cell. FTJs with one semiconducting electrode [65] or a FE diode [116] can provide a large nonlinearity factor in a device I-V, leading to a selectivity in the direction of current flow, lowering the risk of cross-talk. Another important aspect of FE systems is the large voltage-timescale dependence. In P(VDF-TrFE)-based FTJs, a seven-order-of-magnitude change in switching timescale is reported at the expense of doubling the programming voltage. [66] This has important implications in terms of integration of FTJs in passive crossbar arrays. When the programming timescale of a memory cell varies by orders of magnitude due to a slightly less programming voltage, the array can become intrinsically robust against write disturbance. For instance, a device switching at 6 V with a 20 ns programming pulse will not switch a neighboring cell with an inadvertent 4 V pulse at the same timescale. Therefore, through material and device design, a selector-less integration of FE memories in large crossbar arrays could be possible, greatly improving the memory integration density, without affecting the reliability of the programmed memory matrix. For doped hafnia-based FTJs, a low readout current in ultrascaled devices is an issue of major concern. Current density of FTJs, with 10 nm HZO, is %10 À4 A cm À2 . A crossbar array using this current density for the 20 nm technology node, can give an on-state current %0.7 fA. In a 1024 Â 1024 array with all the WLs turned on and all the devices in the on state, the BL summed current will still be below 1 pA. Therefore, in a 1024 Â 1024 array, considering R wire and C wire ¼ 2.925 Ω and 8.8 aF, respectively, the first-order estimation of RC is larger than 1 s that can make the readout extremely slow. To overcome this issue, current values from an ultrathin 1 nm HZO is considered. [43] The projected on-state current for 1 nm HZO is equivalent to about 60 pA for a device at 20 nm node. Innovative design concept of stacked capacitors from modern DRAM processes, with a diameter to height aspect ratio of 220, is proposed as a viable choice. [142] Following this idea, a crossbar array in the 20 nm node could show a desirable summed current level on the order of 10 μA. To model a realistic data pattern of on-state and off-state devices in a 1024 Â 1024 array, quantized weights from a fully connected layer of a DNN are mapped on the FTJ cells. Evaluation of summed current, accuracy, and delay suggests that low current issues in an FTJ crossbar array can be overcome utilizing innovative design concepts.

Integrated Ferroelectric Memories for Edge Applications
Miniaturized sensor systems with built-in memory and computing functionalities are becoming the cornerstones of AI at the edge. [56,57,143] Construction of such hardware would require functional devices in which synaptic information processing capability will be merged with various sensing functionalities such as sensitivity to light, pressure, temperature, chemical analytes, etc. The most efficient way to do this is a system-level integration of sensing and computing in electronics. Recent years have witnessed a surge in research efforts for such platform where either a 2D, 2.5D or 3D integration of layers with different functionalities has been demonstrated.

CMOS Integrated HfO 2 -Based FRAM, FTJs, and FeFETs
In recent times, monolithic 3D integration of HZO-based capacitors, FTJs, and FeFETs with FEOL high-k/metal gate Si-NMOSs has been shown ( Figure 13). [131,144,145] In all cases, a low thermal budget (maximum 450 C, 80 s) processing is used to integrate HZO devices on CMOS platform. Francois et al. demonstrated scalability of TiN/HZO/TiN capacitors from 100 μm diameter down to 300 nm by cointegrating the capacitors in the BEOL of 130 nm CMOS technology. Excellent performance, like 2P R > 40 μC cm À2 , endurance >10 11 cycles, switching speeds <100 ns, operating voltages <4 V, and data retention at 125 C, is reported on the scaled bit cells. Apart from the single devices, 16 kbit 1T-1C arrays with capacitors of different sizes were demonstrated where programming and erasing were performed by voltage pulses and readout was done with an integrated sense amplifier.
For HZO FeFETs, Dutta et al. used a 1% Tungsten (W)-doped amorphous In 2 O 3 semiconducting channel material. A high remnant polarization charge density 2P R of 40 μC cm À2 with reliable switching characteristics was demonstrated in ultrascaled FeFETs with 20 nm channel length. A read MW of 0.45 V, write speed of 100 ns, and write endurance >10 8 cycle, together with 2-bit per cell synaptic weight with well-separated conductance states, were demonstrated. System-level analysis of IMC accelerators for performing inference on CIFAR-10 image dataset predicts that 22 nm BEOL FeFET can achieve 3Â higher energy efficiency compared to the 7 nm SRAM while occupying a smaller area due to area folding enabled by 3D integration.
Wafer-scale uniformity of device performance is an essential criterion for implementation in large-scale circuits. Study has been made on large-area device performance for both hafniaand P(VDF-TrFE)-based FeFETs. Jiang et al. showed a very tight distribution of device variability across 300 mm wafer of HZO capacitors, [81] while data from Global Foundries confirm similar performance from the I d -V g curves of FeFET passive arrays from across wafer programmed into 63-bit L ¼ 450 nm, W ¼ 450 nm cointegrated in 28 nm technology (Figure 13e). [146] Device yield was reported to be >90%. Results show that the scan-to-scan variability increases with decreasing junction size due to inherent variability in FE domain switching. For P(VDF-TrFE)-based FeFETs, large-area printed memory transistors with highly uniform device performance were reported in the literature. [147][148][149] Bae et al. demonstrated roll-up memory arrays [147] where Sekitani et al. [148] developed large-area flexible communication sheet with ultralow power consumption. van Breemen et al. reported 16 Â 16 passive matrix of P(VDF-TrFE)-based FeFET arrays where current modulations of %10 5 retention time of more than 12 days and fault tolerant writing were demonstrated. [149] In all cases, printing technique was used for the FE memory array fabrication. With innovative nanoimprint lithography technique, a memory cell density of 33 GB in À2 was reported from P(VDF-TrFE) memories by Hu et al., [150] which opens pathways for dense integration of these devices.

Ferroelectric Polymer-Based Memory Integrated Sensors for Smart and Adaptive Systems
Integration of flexible sensing and memory arrays has been demonstrated in the past, mainly for touch or light sensing and remembering. For instance, Sekitani et al. first demonstrated the integration of flexible pressure sensors and memory arrays on PEN substrates. [151] Human visual perception systems were emulated by integrating memristors with UV image sensors on flexible PI substrates. [28] In the artificial visual memory system, the detection of UV light by the image sensors was recorded in memristors. This provided detection and memory capacities that provided emulation of human visual memory. In another approach, a FE/electrochemical modulated organic synaptic device was integrated with organic light-sensitive elements showing improved NVM functions and three types of synaptic plasticity. [152] Organic neuromorphic devices for artificial neural network application have been discussed in detail in some recent works. [23,53,153] Ferroelectric polymers are promising for vital parameter sensing like pulse pressure and change in body temperature. [154] By combining their piezo-and pyroelectric properties, multiple parameter sensing through a single sensing element is possible. [155,156] Additionally, the nonvolatile polarization switching in these devices offers the possibility of integrating the sensing and memory performance in the same device architecture. Earlier results showed an in situ poled P(VDF-TrFE) nanowire on an Au-coated PI film enabled detection of finger motion, breathing, and pulse rate in humans. Ferroelectric skins with pressure sensing layer made of two interlocked microdome sheets for monitoring artery pulse pressure waveforms at different skin temperatures (20-40 C) before/after exercise showed the radial artery augmentation index and the radial diastolic augmentation index vary linearly with temperature. [157] These results from a promising baseline and suggest future directions for improving sensing accuracy for integration with IMC architectures. Additionally, an FeFET with photo, gas, or humidity sensing semiconductor can further broaden the horizon of sensing, while FE gate stack brings the memory and computing possibilities in the same device, making in-sensor computing possible.

Future Perspective and Outlook
Despite the fast recent progress of the low-temperature processable, FE-based NVM technology, several issues remain to be solved before their true potential is fully realized. One of the main being the low-voltage operation while keeping their best performance intact. hafnia-based FeFET technology has already  [144] Copyright 2019, IEEE. e) Reproduced with permission. [146] Copyright 2020, IEEE. f ) Reproduced with permission. [147] Copyright 2013, American Chemical Society.
www.advancedsciencenews.com www.advintellsyst.com reached a considerable matured stage of research and therefore can be predicted to become one major contributor in the field of CMOS compatible NVM and neuromorphic computing circuits. A few recent results showed promising way forward on solving the issues like programing voltage MW bottleneck and device breakdown after a million operating cycles. The field of FTJs is, however, still in its genesis, and there is high potential for improvement both from technological and fundamental perspectives. For scaled devices, randomness in switching voltages is still an issue. A targeted programming scheme has been predicted to show improved performance in this respect. [146] Another point of concern is precision of analog conducting states that can be detrimental for training accuracy. Future research in the direction of innovative gate stack and geometry design or multilayer tunnel barrier design can be useful. However, many brain-like computing architectures rely on statistical approximations and estimations of data and therefore error-free bit precision might not always be essential. Also, device aware architecture and algorithm designs can alleviate some issues to produce high throughput, noise immune, high density CIM arrays. [158] For organic FE devices, a high-voltage operation in many earlier reports was considered to be a hurdle for their utilization in wearable technologies. However, some promising but largely overlooked results suggest that through nanopatterning, [150,159] gate stack thinning and optimization, [44] and use of high mobility semiconductor components, the operating voltages can be brought down drastically. As there are no fundamental limitations for their fatigue or breakdown under continuous bias stress, it is possible to achieve more than 10 9 cycles of operations in these devices, making them potentially suitable for online training in IMC circuits. It is also possible to take care of many device-level nonidealities at the circuit level. [160] Need for ultrastretchable and bendable devices for wearable, prosthetics and artificial skin applications can be met with the flexible polymeric devices opening a new path for low-cost, large-area intelligent device applications. Ubiquitous sensing and computing platform utilizing the FE materials would be the next target to avoid the need for power-and-area hungry analog-to-digital or reverse signal conversion in the edge computing devices and lead the way toward realization of a truly bioinspired intelligent systems.