Ferroelastic Domain Walls in BiFeO3 as Memristive Networks

Electronic conduction along individual domain walls (DWs) is reported in BiFeO3 (BFO) and other nominally insulating ferroelectrics. DWs in these materials separate regions of differently oriented electrical polarization (domains) and are just a few atoms wide, providing self‐assembled nanometric conduction paths. Herein, it is shown that electronic transport is possible also from wall‐to‐wall through the dense network of as‐grown DWs in BFO thin films. Electric field cycling at different points of the network, performed locally by conducting atomic force microscopy (cAFM), induces resistive switching selectively at the DWs, both for vertical (single wall) and lateral (wall‐to‐wall) conduction. These findings are the first step toward investigating DWs as memristive networks for information processing and in-materio computing.


Introduction
[16][17] In addition, their multiple resistance values bring them close to the behaviour of synapses (non-volatile variable resistance) and neurons (volatile variable resistance), offering them as the basic elements in neuromorphic computing applications [3,18,19] .Nonetheless, the learning ability of the brain arises from a highly interconnected network of such elements in ways that are far from being understood, making the study of memristive networks highly relevant. [3,20,21] C[24] Moreover, a network of memristors can effectively behave as a memristor with increased tunability in the on/off ratios, as well as in the threshold voltages [25] , since the current flow not only depends on the history of the applied voltage, as in single memristors, but also heavily on the location of the input leads within the network. [26,27] t has also been shown that memristive networks are more robust to failure and variability than individual memristors, [28][29][30] which is of much importance, as the variability of memristive devices is the main issue in the way towards their implementation in hardware.In addition, a sufficiently large number of interconnected simple elements-such as memristors-is expected to display emergent behaviour [21,[31][32][33] , which in the case of information processing, has been reported to allow complex learning functions with extreme energy savings [19,34,35] .
In this work, networks of ferroelectric-ferroelastic domain walls (DWs), which are the boundaries between two domains (regions with differently-oriented electrical polarization), are investigated for their potential use as memristive networks.These DWs are one or two atoms wide [36] and they self-assemble in ferroelectric materials to accommodate electrical and elastic boundary conditions.The density of DWs can be tuned by the choice of substrate and the system dimensions, such that the distance between domain walls can be as small as a few tens of nanometers in thin films [37][38][39] .Although ferroelectric materials are typically insulators, the DWs in some ferroelectrics have been reported to display enhanced conductivity compared to that in the domains [40][41][42][43][44][45][46] .Conductivity at DWs was first demonstrated by artificially switching selected areas of the sample using piezo-force microscopy (PFM) [47] and, subsequently, performing conducting atomic force microscopy (cAFM) maps around the newly created DWs [40,48] .However, it was also reported that as-grown ferroelastic domain walls that form during the growth process in BiFeO 3 (BFO) could display enhanced conductivity as well [49][50][51] .[55][56] Therefore, these materials could provide dense self-assembled memristive networks.
Ferroelastic DWs are formed during the growth process to release the epitaxial strain imposed by the substrate. [57]Thus, unlike networks of metallic nanoparticles or nanowires [58][59][60] , or unlike artificiallycreated ferroelectric DWs, [61] ferroelastic DW networks provide fixed conduction channels that are not easily moved, removed or created with an electric field.Therefore, the plasticity of the network is determined by the effect of ionic migration (driven by the strong strain gradients present around the ferroelastic DWs) on the electronic band bending [49,50,62,63] , bringing some unique features.Despite their interest, previous works on self-assembled DWs mainly focus on the "vertical", out-of-plane (OOP), electrical response.In this paper, the possibility of obtaining "lateral", in-plane (IP), conduction through the DW network and, thus, to achieve charge flow parallel to the surface, along the walls, is investigated.First hints that this is, indeed, possible are presented.BFO thin films with a thickness of 55 nm were deposited by pulsed laser deposition (PLD) on TiO 2terminated (100) SrTiO 3 (STO) single crystal substrates.Two types of samples, with and without bottom electrode, have been fabricated.OOP transport measurements are performed on samples with SrRuO 3 (SRO) buffer layers acting as the bottom electrode.These samples are referred to as BFO/SRO/STO.For IP measurements, samples without bottom electrode are used.These are referred to as BFO/STO.

Results
The measurements are performed using the conductive tip of an AFM as top electrode (cAFM) in two different geometries, as shown in Figure 1.More details of sample fabrication and measurement techniques are found in the Experimental Section.
[66][67] The OOP conduction map of the same BFO/SRO/STO sample is shown in Figure 2 a).The scans are performed with a sample bias of 3 V on the bottom electrode, while the tip is grounded.The domain structure gives rise to a close-meshed, well-interconnected network of domain walls that are more conducting than the host material, in agreement with previous reports [50] . .The respective probed locations are given by the red circles on the conduction maps shown as insets.d) Fit of an I -V loop measured in the same location as indicated in c) by a model based on an equivalent circuit combining a memristor and a diode. [68]n this OOP geometry, local current-voltage (I -V ) characteristics can be obtained both inside the domains and at domain walls, by locally placing the conducting tip on selected positions at the sample surface and applying an alternating voltage signal.I -V curves measured inside a domain are shown in Figure 2 b).They were obtained applying a triangular wave with a frequency of 1 Hz and an amplitude of 3 V.A diode-like behavior is observed: while no current response is measured for negative voltages (negative polarity at the bottom electrode), positive voltages induce a maximum current of 20 pA.No significant change is observed upon further cycling.The rectifying behaviour can be explained by the different work functions of the electrodes.The existence of different Schottky barriers at both interfaces, namely the CoCr alloy tip /BFO top interface and the BFO/SRO bottom interface, has been previously reported [69,70] .
In Figure 2 c), I -V curves probing a highly conductive domain wall are shown.The same triangular voltage signal used in Figure 2 b) was applied over a duration of 12 cycles.Similar to the response inside the domains, rectifying behaviour is observed with no current response for negative voltages, while for positive voltages values of up to 10 nA, that is three orders of magnitude larger than in the domains, can be measured.In this case, the I -V characteristics evolve with electric field cycling: a maximum current of 200 pA can be reached during the first four cycles, while, from the fifth cycle on, the maximum currents increase by more than one order of magnitude.It can also be noticed that, while the first cycles show almost no hysteresis, from the eighth cycle on, a distinct hysteresis window opens up, bringing the domain wall to reach the lowest resistance values.This behavior suggests that Joule heating might cause the resistance changes at the domain walls.The lower current branch in Figure 2 c) corresponds to the initial increase in voltage from 0 V to 3 V, while the higher currents are obtained for decreasing the voltage again from 3 V to 0 V as indicated by the arrows.This counter-clockwise hysteretic response resembles the socalled eight-wise switching that involves interface changes, rather than formation of filaments to explain the resistive switching. [71,72] nterestingly, the hysteresis window is opened by an abrupt current increase of over one order of magnitude, happening at different threshold voltages, whose values vary between 2.5 V and 3 V.The threshold voltages lack a clear trend with further cycling, which again points to Joule heating as one of the drivers of the resistance change.
In Figure 2 d), a domain wall I -V loop measured at the same location as in Figure 2 c) is fitted by a model [68] , which is based on a memristor and rectifier equivalent circuit, as reported for TiO 2 memristors.and described by: where the parameters and their physical significance are described in the Supporting Information.Despite obvious differences of our material compared to the TiO 2 memristors, [68] the model captures the main shape of the I -V loop and provides a quantitative functional expression for the simulation of the OOP memristive behaviour of individual DWs, which is an important prerequisite for the design of circuits that incorporate these DWs.More information about the model and the results o the fits can be found in the Supporting Information.
As IP conductivity and connectivity of the DW network can only be investigated in the absence of a bottom electrode, these measurements are performed on the BFO/STO samples.In Figure 3 a), the BFO topography indicates a high-quality BFO layer with atomically flat terraces, which result from epitaxial growth on the terrace-step structure of the bare STO substrate.The lateral PFM amplitude and phase signals on the same BFO/STO sample are shown in Figure 3 b) and c), respectively.The ferroelectric domain structure is of the same type as that observed in the BFO/SRO/STO samples (i.e.four types of 71°down-polarized domains are present).However, due to the absence of the SRO buffer layer, the domain morphology of this sample differs from that of the BFO/SRO/STO sample shown in Figure S1 in that the BFO/STO sample exhibits longer stripe domains interrupted by smaller orthogonal domains.The domains show a well defined periodicity of approximately 190 nm, which agrees with the width of the substrate terraces.Indeed, by comparing the topography in Figure 3 a) with the PFM images in Figures 3 b) and c), a strong preference exists for the long stripe domain walls to align with the step edges.This is also directly visualized in Figure S2 (see Supporting Information).
Most long stripe domains even nucleate directly at the edge of the step terraces, as earlier reported. [73,74] herefore, it is possible to tune the periodicity and the configuration of the domain wall network, to some extent, by changing the substrate miscut (terrace width) and the orientation of the miscut (surface plane) with respect to the crystallographic planes.
A conduction map of the BFO/STO sample obtained under the application of a 4 V sample bias is shown in Figure 4 a).The right border of the scanned area is parallel to the right edge of the Pt electrode window and approximately 0.5 µm away from it.The location of the scanned area with regard to the window in the Pt electrode is shown in Figure S3 a) (see Supporting Information).Other scanned areas present similar DW structure and current levels also at longer distance (several 10 µm) from the Pt electrode edge as depicted in Figure S3 b) and c) of the Supporting Information.As in the case of the BFO/SRO/STO samples, the conductivity is clearly enhanced at the domain walls and the long-stripe domain structure is also visible in the conduction maps.Compared to the OOP conductivity maps, the observed currents are strongly reduced, as expected in this configuration, with the electrodes being further apart.Typical currents in the long DWs are between 2.5 pA and 4 pA, while the shorter, wiggling DWs exhibit currents between 5.0 pA and 7.0 pA.The latter DW type also displays a larger apparent domain wall width.Figure 4 b) shows another conduction map of the same sample directly measured next to the edge of the Pt electrode.In this scan the applied bias is reduced to 3.5 V (by close inspection, the overlapping area between the two maps can be recognized).
From Figures 4 a)-(b), a horizontal current gradient is only visible in the close proximity of the electrode edge.For a tip-Pt electrode distance larger than 2 µm almost no current gradient is visible.The distribution of the electric field in the BFO/STO sample, for a bias of 3.5 V, can be simulated using finite element methods (FEM), as shown in the Supporting Information (see Figure S4).Two types of simulations are performed.First, the electric field close to the Pt electrode is simulated (Figure S4 a)).Due to the edge effect at the 20 nm thick Pt electrode, the magnitude of the electric field sharply decreases by about 70% over only 10 nm distance to the electrode edge.This is in quantitative agreement with the observations, and we can, thus, state that the observed current gradient in Figure 4 b) is directly linked to the steep electric field gradient at the electrode edge.Second, the electric field distribution around the tip is also simulated to explain the absence of a current gradient beyond this edge effect.Such gradient is expected for an effective resistance governed by the length of the domain walls.In Figure S4 b) and c) (see Supporting Information), a FEM simulation of the IP conduction sample, including the microscope tip, is shown.For the purpose of estimating the field distribution, the BFO thin film is considered to be homogeneous (i.e. the simulation does not contain conducting DWs).The FEM shows that the potential difference is largely enhanced close to the tip, indicating that the observed conductivity corresponds to a strongly localized area around the tip, with the contribution from other areas of the network being negligible.This explains the absence of the gradient across the IP conduction maps.
However, it is also important to notice that, even in the case of a stand-alone device with extended electrodes and a well-defined (homogeneous) potential difference across a memristor/resistor network, a smooth decrease of the current at increasing distances from the electrode is not necessarily expected.To show this, the notion of effective resistance on graphs is used.The effective resistance on a graph is defined as a distance measured between a pair of nodes, by viewing the graph as an electric circuit with a 1 V voltage source connected between the selected nodes.Each edge in the network and its corresponding weight are associated to a resistor and its resistance value, respectively. [75]ith that purpose, the conduction map in Figure 4 a) was coarse-grained into 15 × 15 patches and pre-processed to enhance the contrast in order to emphasize the lack of an evenly distributed gradient (see Figure S5 a)-c) of the Supporting Information).Then, a grid-graph resistor network with a number of nodes equal to the number of patches was built.Additional diagonal edges were then also included in this lattice.One among those edges (randomly chosen for each node) was excluded to avoid local intersections of the edges, in order to maintain a two-dimensional framework. [76]Finally, a reference node representing the Pt electrode was included on the right-hand side of the network.The resistivity of the edges in the circuit graph was then fitted to reproduce the same effective conductance distribution on the graph as that obtained from the processed conduction map. [77,78] igure 5 shows that it is possible to obtain a distribution of effective conductance between each node/tip position and the Pt electrode node that does not show the evenly distributed gradient expected for increasing Euclidean distances from the Pt electrode in case of isotropic conductance.Thus, this modeling result highlights the role of the underlying network structure on the effective conductance distribution over the nodes.For the BFO/STO sample measured in Figure 4 b), also local I -V sweeps on DWs are performed.In Figure 4 c), the I -V curves obtained from triangular sweeps with 1 Hz frequency and 10 V amplitude on a DW are shown.The location of the measured DW is marked by the circle labelled as "Spot 1" in Figure 4 b).The tip-electrode distance is approximately 5 µm.The I -V characteristics are asymmetric, but clearly different from the rectifying behaviour observed in the OOP measurements shown in 2 b): while for positive voltages, a linear current increase up to 20 pA is found, the branch of negative voltages increases faster and reaches up to −60 pA.The I -V curve of every cycle looks similar and only a weak hysteretic behavior is found.
Using the same triangular waveform, I -V sweeps are applied to a DW at a different location, which is labelled as "Spot 2" in Figure 4 b).The tip-electrode distance for this DW location is approximately 1.5 µm.For the first 3 cycles, a small hysteresis window is found.Similar to the observation of Figure 4 c), ohmic-like behavior is found for positive voltages, reaching up to 40 pA, while the negative voltage branch displays a faster increase and reaches up to −130 pA.The fourth cycle shows the largest hysteresis window with an abrupt current increase at a threshold voltage of V th ∼ 9.5 V, leading to an increased maximum current of more than 100 pA.From this cycle on, the maximum negative current for negative voltages is also increased to −170 pA.Cycles 5 and 6 show a smaller hysteresis window accompanied with a less abrupt switching and intermediate current values for positive voltages.

Discussion
As mentioned above, the complex distribution of connectivity of the DW network structure makes it challenging to intuitively predict the current distribution.As seen in Figure 4 a) and b), the DW current of the long, quasi-periodic, DWs is lower than the current measured at the shorter wiggling DWs.This is the most visible DW current contrast in both conduction maps.One possible reason for this difference is a higher level of connectivity to the rest of the network for the wiggling DWs.All long DWs are oriented parallel to each other (horizontally, in the maps), so they display limited connectivity to the rest of the network.The wiggling DWs interrupt and connect to the long DWs, while being oriented in almost all possible directions, collecting the charge flow from a number of conduction paths at their location.
Moreover, the lack of current gradient in the conduction maps, which seemed puzzling at first, is shown to arise from the measurement set-up, limiting the sensitivity to the local environment of the tip.Because of this limitation, it is important to ensure that the charge flow solely occurs laterally across the DW network and does not leak through other parts of the layer stack.
A possible reason for such an alternative current path could be the presence of an unexpected conductive layer at the STO/BFO interface, for instance through the formation of a two-dimensional electron gas (2DEG). [79]The conductive interface would shunt the DW network, such that at each tip position the current flows first vertically through the DW to reach the conductive interface and then laterally through the interface towards the DWs, which are vertically connected to the Pt electrode edge.Assuming the interface conductivity being much larger than the DW conductivity, a horizontal current gradient in the conduction map would also be suppressed.
The microscopic origin of a 2DEG could be explained to a large extent by polar discontinuities depending on the formal valence states of the crystal sublattices. [79]In fact, the existence of a 2DEG at the STO/BFO interface has been shown. [80]While details about the STO substrate termination are not given, the authors report Ti diffusion across the interface, which is most likely a result of a TiO 2 -terminated STO substrate.However, in the present work, the STO substrates of the BFO/STO samples exhibit SrO-termination as explained in the Methods section.The epitaxial growth of BFO on a SrO-terminated STO substrate results in a (FeO 2 ) − /(SrO) 0 interface.Theoretically, this interface should host a two-dimensional hole gas (2DHG), as p-type carriers are attracted by the remaining negative charge.However, so far 2DHGs have been much less observed compared to 2DEGs in different material systems.Since many of these materials are oxides, typical defects such as positively charged oxygen vacancies are likely to move to the interface, neutralizing the excess negative charge and impeding the accumulation of holes.In that sense, one can argue that the (FeO 2 ) − /(SrO) 0 interface does not show a 2DHG since the more prominent but electronically equivalent (AlO 2 ) − /(SrO) 0 interface does not show a 2DHG either, but insulating behavior instead. [79]Up to now, a 2DHG has only been proven in one material system with high experimental effort to achieve extremely low oxygen vacancy densities. [81]hus, the presence of a conducting interface is unlikely.This is consistent with the fact that attempts to perform OOP conducting measurements in the BFO/STO samples by contacting the interface (using wire-bonding, in the same manner the SRO electrode is accessed in the BFO/SRO/STO samples), have not been successful.It is also consistent with the values of the voltages needed to induce observable currents in the I -V sweeps in both geometries.For a maximum voltage amplitude of 3 V, the OOP currents (see Figure 2) are up to two orders of magnitude higher than the measured IP currents (see Figure 4), even though a larger voltage amplitude of 10 V was applied to the latter.This can be explained by the very different distances between the tip and the electrodes.This distance is equal to the BFO layer thickness of 55 nm in the OOP maps; while typical tip-electrode distances for the IP conduction I -V sweeps are in the µm range, leading to lower effective electric fields.

Conclusions
Conducting atomic force microscopy (cAFM) has been used to characterize electronic transport through domain wall (DW) networks on BiFeO 3 (BFO) thin films grown on STO with and without bottom electrode.This allows to compare the out-of-plane (OOP) and in-plane (IP) conductivity and characterize both the individual DWs and the network connectivity.Local current-voltage (I -V ) sweeps in the OOP response of individual DWs show hysteresis, which can be taken as a proof of resistive switching and memristive behavior.While OOP enhanced conductivity in as-grown BFO domain walls and resistive switching behaviour of individual (artificially written) domain walls in BFO and other materials have been previously reported, the difficulties of fabricating good quality thin films without bottom electrode has made the demonstration of lateral conductivity very challenging.In this work, memristive behavior of DWs at high enough currents is observed, indicating that it originates in the local Joule heating that may induce local changes in the (defects) chemistry, as in several other memristive oxides.The memristive behaviour evolves with multiple voltage cycles at the same DW location, thus indicating plasticity of the DW network both for OOP and IP DW conduction.These results offer insight into using single DWs and DW networks for memory and neuromorphic applications, which is not only limited to BFO but can be generalized to other ferroic oxides.

Methods Section
Prior to deposition of the thin films, commercially available STO (100) substrates were etched in buffered hydrofluoric acid and annealed to obtain TiO 2 -termination and atomically smooth terraces with step edges of one unit cell [82] .For OOP conduction, a 6 nm-thick SrRuO 3 (SRO) layer was deposited using PLD in an oxygen atmosphere of 0.14 mbar at 610 °C prior to the growth of BFO, to serve as a bottom electrode.A 55 nm thick BFO layer was deposited at 0.3 mbar oxygen atmosphere at 640 °C substrate temperature.Both layers are successively deposited to preserve the quality of the interface.For both depositions a laser fluence of 2.34 J cm −2 was used.The bottom electrode was electrically contacted to the sample bias terminal of the AFM by wire-bonding.A sketch of the OOP sample layout and measurement design is shown in Figure 1 a).
For IP conduction, the layer stack lacks the bottom SRO layer and a different strategy is used.Nevertheless, care has to be taken to assure the same quality of the BFO layer.High-quality epitaxial BFO films require an underlying A-site terminated layer to grow smoothly with pronounced terrace formation [83] .In the case of OOP samples, the SRO bottom electrode layer is automatically A-site (SrO) terminated due to the high volatility of RuO 2 [84] .However, for the IP samples, the termination of the STO substrate was changed from TiO 2 to SrO by depositing a SrO monolayer using PLD.The SrO target was produced in a solid-state synthesis from commercial SrO powder going through several steps of drying, pressing and sintering.Due to the high reactivity of SrO with H 2 O, it is crucial to keep the SrO target from humid ambient atmosphere while handling it.The SrO layer was deposited at an oxygen atmosphere of 1 × 10 −5 mbar, 850 °C substrate temperature, and a laser fluence of 1.17 J cm −2 .During SrO growth, the thickness was precisely controlled by RHEED such that exactly one monolayer was deposited [85,86] .The growth parameters for the subsequent BFO deposition were the same as for the BFO deposited for the OOP conduction samples.For all depositions a laser frequency of 1 Hz was used.The heating rate was 30 °C/ min, while the sample was cooled down at a rate of 7 °C/ min in an oxygen atmosphere of 200 mbar.To perform lateral conduction measurements, a 20 nm thick Pt layer was evaporated.The Pt electrode was patterned with UV-lithography to create windows with sizes of 200 x 200 µm 2 and 100 x 100 µm 2 , through which the BFO can be contacted with an conducting AFM tip to perform cAFM measurements.The Pt electrode was wirebonded and connected to the sample bias terminal of the AFM, while the conducting tip was electrically grounded as can be seen in Figure 1 a).
Prior to all scanning probe microscopy (SPM) measurements the samples were cleaned using a Fischione Instruments Model 1020 Plasma Cleaner for 8 min with a 75% Ar / 25% O 2 gas mixture to remove any carbon-containing contamination.All SPM measurements of this work were performed in an Asylum Research Cypher ES AFM.Just before the measurement the sample was heated up in the microscope gas cell to 150 °C for 15 min to remove excess surface humidity.During the heating and the measurements (all performed at room temperature) the gas cell was constantly flushed with Ar to provide a dry and inert atmosphere.The SPM measurements were performed using Sb-doped Si tips with a conducting CoCr coating.
Prior to the cAFM measurements, the PFM maps were obtained to reveal the ferroelectric-ferrolastic domain structure, using a similar experimental configuration as shown in Figure 1 a).
In the cAFM setup, the sample bias was applied to the SRO bottom electrode (lateral Pt electrode), while the metallic tip was electrically grounded to perform OOP (IP) conduction measurements as shown in Figure 1 a) and b).In OOP and IP cAFM, two types of measurements were performed: conduction maps that collect the current across the sample under a given bias voltage, and current versus voltage curves collected at a fixed location on the sample, which was determined from the previously recorded conduction map.
To perform the FEM simulations, the Electrostatics Interface of COMSOL Multiphysics ® (COMSOL, Stockholm, Sweden) was used.
The Python language package NetworkX was used to build the circuit graph and to measure the effective resistance by its dedicated module. [77]The package SciPy was used to optimize the resistances of the edges. [78]emristor model The domain wall I -V data shown in Figure 2 d) is fitted by a model described by Equation 1: The sinh term in the equation represents a flux-controlled memristor in the ON state, in which the main current contribution is described by electron tunneling through a thin residual layer.w is proportional to the time integral of the voltage V (i.e. the magnetic flux between both terminals) and normalized to values between 0 and 1.The exponent n describes the dependence of the oxygen vacancy drift velocity on the voltage applied to the device.α and β are fitting constants characterizing the ON state.The exponential term represents a rectifier, modeling the current between both terminals in the OFF state with χ and γ as additional fitting constants.More details are given in [68] .
In Table 1 the fit parameters resulting from modeling the I -V data shown in Figure 2 d 2 d) using a memristor and rectifier model. [68]ezo-force microscopy of an BFO/STO sample In Figure S2   They exhibit similar current levels reaching up to 9 and 7 pA respectively, even though the difference in tip -Pt electrode distance between both scan areas is larger than two orders of magnitude.The larger 13 x 13 µm 2 conduction map shown in Figure S3 c) is also measured with a 4 V sample bias, but a solid Pt tip and therefore exhibits higher current levels of up to 28 pA.Also in this IP conduction map a current gradient is absent for varying tip -Pt electrode edge distance.

Finite Element Modeling
As apparent from the IP conduction maps shown in Figure S3, no current gradient for increasing tip -Pt electrode distance is found, even though it would be expected in the sense of increasing effective resistance.
To explain this finding, a finite element method (FEM) simulation is performed to illustrate the distribution of electric field and potential in the BFO layer of the BFO/STO samples as shown in Figure S4.In Figure S4 a) a two-dimensional simulation of the electric field in the Pt electrode edge vicinity is shown.The Pt electrode is set to the typical sample bias voltage of 3.5 V.The electric field is maximal directly at the Pt electrode edge, abruptly decreases within approximately 10 nm distance and slowly goes towards 0 for larger distances from the Pt electrode edge.This electric field edge effect causes the strong current gradient visible at the right side of Figure 4 b).
Figure S4 shows a three-dimensional Finite Element modelling (FEM) simulation of the b) electric potential and c) electric field in the BFO layer in the 200 x 200 µm 2 electrode window including a grounded tip.The Pt electrode voltage is the same as in a).Except in the direct tip vicinity, the electric potential is approximately equal to the sample bias of 3.5 V. Figure S4 c) shows, that the electric field is always maximal and approximately of the same strength directly at the tip regardless of the tip location.Therefore, only the strongly localized area around the tip is contributing to the measured current in cAFM measurement and other, further distant sample areas can be neglected.This explains the absence of any electrode distance related gradient apart from the case shown in Figure S4 a).The large difference in electric field strength of several orders of magnitude between Figure S4 a) and c) can be related to the existence of the grounded tip in the latter case.

Graph representation of the network
Figure S5 shows the pre-processing steps applied to the original IP conduction map from Figure 4 a) in order to obtain a distribution of effective conductance devoid of the expected gradient from the Pt electrode, which is shown in Figure 5.

Figure 1 :
Figure 1: Experimental setup and layout of samples for a) vertical (OOP) and b) lateral (IP) conduction measurements.For the OOP conduction experiments, a SrRuO 3 (SRO) layer is deposited between the STO substrate and the BFO layer to serve as bottom electrode.The SRO layer is electrically connected by means of wire-bonding.A Pt top electrode is patterned to leave square windows that enable access to the BFO surface.

Figure 2 :
Figure 2: Out-of-plane (OOP) domain wall conduction.a) OOP conduction map of a BFO/SRO/STO sample, obtained by cAFM with a 3 V sample bias and a grounded tip.The as-grown ferroelastic/ferroelectric DWs show enhanced conduction compared to the domains.b-c) OOP I -V curves probed on the same BFO/SRO/STO sample for contacting a ferroelectric domain (b)) and an individual domain wall (c)).The respective probed locations are given by the red circles on the conduction maps shown as insets.d) Fit of an I -V loop measured in the same location as indicated inc) by a model based on an equivalent circuit combining a memristor and a diode.[68]

Figure 3 :
Figure 3: a) Topography, b) lateral PFM amplitude and c) lateral PFM phase of a BFO/STO sample with a 55 nm thick BFO layer.All images show the same region of the sample.

Figure 4 :
Figure 4: IP domain wall conduction.cAFM measurements on a BFO/STO sample with a 55 nm thick BFO layer, measured in IP geometry.In a) the right border of the scanned area is parallel to the Pt electrode edge at an approximate distance of 0.5 µm and a 4 V sample bias is applied; in b) the scanned area is in the immediate proximity of the Pt electrode (visible on the right side of the map) and the sample bias is 3.5 V.The color scale maximum of 30 pA was chosen to improve visibility.The location of conduction map b) is offset by approximately 0.5 µm to the right and 0.5 µm to the bottom with respect to that in a).I -V sweeps on two DWs are shown in c) and d).Their approximate locations are given by the circles in b) labelled as Spot 1 (c)) and Spot 2 (d)).

Figure 5 :
Figure 5: Resistor network showing that an evenly distributed gradient from the Pt electrode is not necessarily expected.The red color of the edges is proportional to their resistance.The node color is proportional to the effective conductance between the node and the reference Pt electrode on the right of the network.The values are in arbitrary units (a.u).
the topography and the lateral PFM amplitude of a 2 x 2 µm 2 area of the BFO/STO sample for IP conduction are shown.The data was acquired in a single scan, showing alternating segments of both data channels.By comparing the neighboring topography and PFM segments, the spacial congruence of step terraces and ferroelectric domains is illustrated.

Figure S 2 :
Figure S 2: Combined topography and lateral PFM amplitude segments of the same 2 x 2 µm 2 area measured on the BFO/STO sample to visualize the spatial coincidence of the step terraces in the topography maps with ferroelectric domains in the PFM maps.

Figure S 3 :
Figure S 3: Supplementary IP conduction maps of different sizes, tip types and locations within the 200 x 200 µm 2 Pt electrode window.The respective scan area locations are indicated in the bottom row.The conduction maps of a) and b) are measured using a CoCr-coated Si tip and a sample bias of a) 4 V and b) 3.2 V.The conduction map in c) is recorded using a solid Pt tip and a sample bias of 4 V.

Figure S 4 :
Figure S 4: Finite element method (FEM) simulations of electric field and electric potential in the BFO layer of the BFO/STO sample with the Pt electrode at 3.5 V sample bias.a) Two-dimensional simulation showing the electric field gradient in direct vicinity of the Pt electrode edge.b) Three-dimensional simulation of the electric potential including a grounded tip with a 20 nm tip radius.The bottom figure shows the potential in a narrow color range covering 0.02 V. c) Electric field based on the same simulation shown in b) for two different tip locations: near Pt edge (top) and middle of electrode window (bottom).

Figure S 5 :
Figure S 5: Pre-processing steps for the resistor network shown in Figure 5.In a) the IP conduction map from Figure 4 a) is shown.In b) a contrast enhancement is applied to emphasize the absence of a gradient from the Pt electrode on the right of the conduction map to the tip (see Figure S2 a)).In c) the current map is coarse-grained into 15 × 15 square patches, then the mean value over each patch is measured and finally it is scaled between the range 1 × 10 −3 and 1.In d) the distribution of values obtained in the previous steps arbitrarily defined as the effective conductance measured in a grid-graph with random diagonal edges and 15 × 15 nodes, in which each edge is a resistor.

Table 1 :
) with the model described by Equation 1 are given: Fit parameters estimated by modeling the domain wall I-V data in Figure